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<h1>Blog<aclass="headerlink" href="#blog" title="Link to this heading">¶</a></h1>
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<divclass="toctree-wrapper compound">
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<ul>
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<liclass="toctree-l1"><aclass="reference internal" href="no_isa_is_the_best_isa.html">No-ISA is the Best ISA</a></li>
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<liclass="toctree-l1"><aclass="reference internal" href="pattern_seeking_brain.html">When Reverse Engineering, Your Pattern Seeking Brain Is Your Friend</a></li>
<h1>No-ISA is the Best ISA<aclass="headerlink" href="#no-isa-is-the-best-isa" title="Link to this heading">¶</a></h1>
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<p>Last Change: Oct 02, 2024</p>
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<p>This week, me and my colleague were present at the first <aclass="reference external" href="compilertech.org">compilertech.org</a> workshop talking about the work we are doing at <aclass="reference external" href="vicharak.in">Vicharak</a> involving FPGAs, Reconfigurable Computing and Compilers for such
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computers. This small blog post is a brief summary of the talk.</p>
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<p>The slides (and the extended slides) for the presentation are available at:
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<aclass="reference external" href="github.com/vicharak-in/noisa">github.com/vicharak-in/noisa</a>. Video for
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the talk will soon be available.</p>
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<sectionid="summary">
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<h2>Summary<aclass="headerlink" href="#summary" title="Link to this heading">¶</a></h2>
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<p>The talk is divided into four chapters:</p>
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<sectionid="chapter-1">
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<h3>Chapter 1<aclass="headerlink" href="#chapter-1" title="Link to this heading">¶</a></h3>
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<p>Chapter 1 lists the problems with modern compute, key problems being the
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slowdown and end of Moore’s law and Dennard scaling and the von-neumann
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bottleneck. We ask ourselves whether compute should be restricted to a small
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selection of available processors/architectures. Last slide in chapter 1 lists
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some concrete problems where using existing compute is difficult.</p>
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</section>
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<sectionid="chapter-2">
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<h3>Chapter 2<aclass="headerlink" href="#chapter-2" title="Link to this heading">¶</a></h3>
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<p>Chapters 2 and 3 include an introduction to reconfigurable/heterogeneous
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computing and EDA compilers.</p>
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<p>Reconfiguration and Heterogeneity are the two key ideas of the architecture that
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we propose. A separation from von-neumann architectures, by the way of
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flow-based reconfigurable computers is discussed. The central theme of the idea
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is to make it easy/automate the generation of <strong>hardware</strong> for our algorithms
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instead of <strong>programs</strong>. In essence, the idea is to have a unique and optimal
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hardware for every software.</p>
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</section>
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<sectionid="chapter-3">
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<h3>Chapter 3<aclass="headerlink" href="#chapter-3" title="Link to this heading">¶</a></h3>
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<p>Since solving problems through reconfigurable/heterogeneous require generation
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of hardware, EDA compilers and their efficiency has to be considered too.
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Chapter 3 is about EDA compilers being a nightmare to deal with in terms of
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flexibility, hackability, performance and adaptability.</p>
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</section>
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<sectionid="chapter-4">
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<h3>Chapter 4<aclass="headerlink" href="#chapter-4" title="Link to this heading">¶</a></h3>
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<p>The last chapter is on the work done so far. For this, we’ve designed our
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own hardware (<aclass="reference external" href="https://docs.vicharak.in/vicharak_sbcs/vaaman/vaaman-home/">Vaaman</a>) on which
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applications utilizing the Reconfigurable paradigm will be designed. Two
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applications on which we are actively working are: Gati (CNN accelerator)
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and Periplex (Peripheral Generator).</p>
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<p>Gati is a CNN accelerator that can generate custom (optimal) accelerator
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hardware for every NN model.</p>
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<p>Periplex provides easy generation and multiplexing of peripheral (UART, I2C,
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CAN, SPI etc.) along with linux device drivers for accessing them through
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