Add CITATION.cff (verilator#5057) (verilator#5058).

Author: wsnyder

CITATION.cff

@@ -0,0 +1,27 @@
+# See https://citation-file-format.github.io/
+cff-version: 1.2.0
+title: Verilator
+message: >-
+  If you use this software, please cite it using the
+  metadata from this file.
+type: software
+authors:
+  - given-names: Wilson
+    family-names: Snyder
+    email: [email protected]
+    affiliation: Veripool
+  - given-names: Paul
+    family-names: Wasson
+  - given-names: Duane
+    family-names: Galbi
+  - name: 'et al'
+repository-code: 'https://github.com/verilator/verilator'
+url: 'https://verilator.org'
+abstract: >-
+  The Verilator package converts Verilog and SystemVerilog hardware
+  description language (HDL) designs into a fast C++ or SystemC model
+  that, after compiling, can be executed.  Verilator is not a
+  traditional simulator but a compiler.
+license:
+  - LGPL-3.0-only
+  - Artistic-2.0

Changes

@@ -14,6 +14,7 @@ Verilator 5.025 devel
 **Minor:**
 
 * Support __en/__out signals on top level inout ports (#4812) (#4856). [Paul Wright]
+* Add CITATION.cff (#5057) (#5058). [Gijs Burghoorn]
 * Fix consecutive zero-delays (#5038). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix `$system` with string argument (#5042).
 * Fix width extension on delays (#5043).

docs/CONTRIBUTORS

@@ -51,6 +51,7 @@ G-A. Kamendje
 Garrett Smith
 Geza Lore
 Gianfranco Costamagna
+Gijs Burghoorn
 Glen Gibb
 Gökçe Aydos
 Graham Rushton

test_regress/t/t_dist_copyright.pl

@@ -20,6 +20,7 @@
 our $Exempt_Files_Re = qr!(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)!;
 our @Exempt_Files_List = qw(
     Artistic
+    CITATION.cff
     CPPLINT.cfg
     LICENSE
     README.rst