diff --git a/README.rst b/README.rst
index de8cde4..c83e923 100644
--- a/README.rst
+++ b/README.rst
@@ -43,19 +43,20 @@ python.
 
 .. code:: python
 
+    import pyverilator
+
     sim = pyverilator.PyVerilator.build('counter.v')
 
     # start gtkwave to view the waveforms as they are made
     sim.start_gtkwave()
 
-    # add all the io and internal signals to gtkwave
-    sim.send_signals_to_gtkwave(sim.io)
-    sim.send_signals_to_gtkwave(sim.internals)
-
     # add all the io and internal signals to gtkwave
     sim.send_to_gtkwave(sim.io)
     sim.send_to_gtkwave(sim.internals)
 
+    # set rst back to 1
+    sim.io.rst = 1
+
     # tick the automatically detected clock
     sim.clock.tick()
 
diff --git a/pyverilator/pyverilator.py b/pyverilator/pyverilator.py
index 1daa160..1d06e92 100644
--- a/pyverilator/pyverilator.py
+++ b/pyverilator/pyverilator.py
@@ -455,13 +455,13 @@ def search_for_signal_decl(signal_type, line):
                             result.group(4)) == 0:
                         # this is an internal signal
                         signal_width = int(result.group(3)) - int(result.group(4)) + 1
-                        return (signal_name, signal_width)
+                        return (signal_name.strip('&'), signal_width)
                     else:
                         return None
                 else:
                     # this is an input or an output
                     signal_width = int(result.group(3)) - int(result.group(4)) + 1
-                    return (signal_name, signal_width)
+                    return (signal_name.strip('&'), signal_width)
             else:
                 return None
 
diff --git a/pyverilator/verilatorcpp.py b/pyverilator/verilatorcpp.py
index d1eb111..642eee5 100644
--- a/pyverilator/verilatorcpp.py
+++ b/pyverilator/verilatorcpp.py
@@ -72,7 +72,7 @@ def function_definitions_cpp(top_module, inputs, outputs, internal_signals, json
         VL_PRINTF("- %s:%d: Verilog $finish\\n", filename, linenum);  // Not VL_PRINTF_MT, already on main thread
         if (Verilated::gotFinish()) {{
             VL_PRINTF("- %s:%d: Second verilog $finish, exiting\\n", filename, linenum);  // Not VL_PRINTF_MT, already on main thread
-            Verilated::flushCall();
+            Verilated::runFlushCallbacks();
             exit(0);
         }}
         Verilated::gotFinish(true);