arch-riscv: Fix incorrect vector unit-stride segment load instructions (gem5#2021)

This PR fixed the bug(gem5#1668) of vector unit-stride segment load, which
is caused by incorrect tail/mask handling logic.

Change-Id: I1a2b3c4d5e6f7890abcdef0123456789abcdef

Co-authored-by: Zhibo Hong <[email protected]>

Author: 5265325

src/arch/riscv/insts/vector.cc

@@ -654,36 +654,63 @@ VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst(ExtMachInst extMachInst,
         uint32_t index = VecMemInternalReg0 + i + (microIdx * _numSrcs);
         setSrcRegIdx(_numSrcRegs++, vecRegClass[index]);
     }
+
+    if (!extMachInst.vtype8.vta
+        || (!extMachInst.vm && !extMachInst.vtype8.vma)) {
+        oldDstIdx = _numSrcRegs;
+        setSrcRegIdx(_numSrcRegs++, destRegIdxArr[0]);
+    }
+    if (!extMachInst.vm) {
+        vmsrcIdx = _numSrcRegs;
+        setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
+    }
 }
 
 Fault
 VlSegDeIntrlvMicroInst::execute(ExecContext* xc, trace::InstRecord* traceData) const
 {
     vreg_t& tmp_d0 = *(vreg_t *)xc->getWritableRegOperand(this, 0);
     auto Vd = tmp_d0.as<uint8_t>();
-    const uint32_t elems_per_vreg =  micro_vl;
+    const uint32_t elems_per_vreg = micro_vl;
     vreg_t tmp_s;
     auto s = tmp_s.as<uint8_t>();
     uint32_t elem = 0;
     uint32_t index = field;
+
+    vreg_t tmp_v0;
+    uint8_t *v0;
+    if (!machInst.vm) {
+        xc->getRegOperand(this, vmsrcIdx, &tmp_v0);
+        v0 = tmp_v0.as<uint8_t>();
+    }
+
+    const size_t micro_vlmax = vlen / width_EEW(machInst.width);
+
+    if (!machInst.vtype8.vta || (!machInst.vm && !machInst.vtype8.vma)) {
+        RiscvISA::vreg_t old_vd;
+        xc->getRegOperand(this, oldDstIdx, &old_vd);
+        tmp_d0 = old_vd;
+    } else {
+        tmp_d0.set(0xff);
+    }
+
     for (uint32_t i = 0; i < numSrcs; i++) {
         xc->getRegOperand(this, i, &tmp_s);
         s = tmp_s.as<uint8_t>();
 
-        // copy tail/inactive elements from vtmp src
-        if (i == field) {
-            tmp_d0 = tmp_s;
-        }
-
         while (index < (i + 1) * elems_per_vreg)
         {
-            memcpy(Vd + (elem * sizeOfElement),
-                    s + ((index  %  elems_per_vreg) * sizeOfElement),
-                    sizeOfElement);
+            size_t ei = elem + micro_vlmax * microIdx;
+            if (machInst.vm || elem_mask(v0, ei)) {
+                memcpy(Vd + (elem * sizeOfElement),
+                       s + ((index % elems_per_vreg) * sizeOfElement),
+                       sizeOfElement);
+            }
             index += numSrcs;
             elem++;
         }
     }
+
     if (traceData) {
         traceData->setData(vecRegClass, &tmp_d0);
     }

src/arch/riscv/isa/templates/vector_mem.isa

@@ -1384,6 +1384,18 @@ def template VlSegConstructor {{
             remaining_vl = this->vl;
             micro_vl = std::min(remaining_vl, micro_vlmax);
             for (int i = 0; i < num_microops && micro_vl > 0; ++i) {
+                bool illegal = (_machInst.vd + i + (f * num_microops)) >= 32;
+                if (illegal) {
+                    microop = new VectorNopMicroInst(_machInst,
+                        std::make_shared<IllegalInstFault>("vd is illegal",
+                        _machInst));
+                    this->microops.push_back(microop);
+                    this->microops.front()->setFlag(IsFirstMicroop);
+                    this->microops.back()->setFlag(IsLastMicroop);
+                    this->flags[IsVector] = true;
+                    return;
+                }
+
                 microop = new %(class_name)sMicro(_machInst, micro_vl, i,
                                                   num_microops, f, NFIELDS,
                                                   elen, vlen);
@@ -1630,6 +1642,18 @@ def template VsSegConstructor {{
             remaining_vl = this->vl;
             micro_vl = std::min(remaining_vl, micro_vlmax);
             for (int i = 0; i < num_microops && micro_vl > 0; ++i) {
+                bool illegal = (_machInst.vs3 + i + (f * num_microops)) >= 32;
+                if (illegal) {
+                    microop = new VectorNopMicroInst(_machInst,
+                        std::make_shared<IllegalInstFault>("vs3 is illegal",
+                        _machInst));
+                    this->microops.push_back(microop);
+                    this->microops.front()->setFlag(IsFirstMicroop);
+                    this->microops.back()->setFlag(IsLastMicroop);
+                    this->flags[IsVector] = true;
+                    return;
+                }
+
                 microop = new VsSegIntrlvMicroInst(_machInst, micro_vl,
                     _machInst.vs3, NFIELDS, i, num_microops, f, elen, vlen,
                     size_per_elem);

src/cpu/o3/FuncUnitConfig.py

@@ -141,6 +141,7 @@ class ReadPort(FUDesc):
         OpDesc(opClass="FloatMemRead"),
         OpDesc(opClass="SimdUnitStrideLoad"),
         OpDesc(opClass="SimdUnitStrideMaskLoad"),
+        OpDesc(opClass="SimdUnitStrideSegmentedLoad"),
         OpDesc(opClass="SimdStridedLoad"),
         OpDesc(opClass="SimdIndexedLoad"),
         OpDesc(opClass="SimdUnitStrideFaultOnlyFirstLoad"),
@@ -157,6 +158,7 @@ class WritePort(FUDesc):
         OpDesc(opClass="FloatMemWrite"),
         OpDesc(opClass="SimdUnitStrideStore"),
         OpDesc(opClass="SimdUnitStrideMaskStore"),
+        OpDesc(opClass="SimdUnitStrideSegmentedStore"),
         OpDesc(opClass="SimdStridedStore"),
         OpDesc(opClass="SimdIndexedStore"),
         OpDesc(opClass="SimdWholeRegisterStore"),
@@ -175,6 +177,8 @@ class RdWrPort(FUDesc):
         OpDesc(opClass="SimdUnitStrideStore"),
         OpDesc(opClass="SimdUnitStrideMaskLoad"),
         OpDesc(opClass="SimdUnitStrideMaskStore"),
+        OpDesc(opClass="SimdUnitStrideSegmentedLoad"),
+        OpDesc(opClass="SimdUnitStrideSegmentedStore"),
         OpDesc(opClass="SimdStridedLoad"),
         OpDesc(opClass="SimdStridedStore"),
         OpDesc(opClass="SimdIndexedLoad"),