Merge pull request #837 from diffblue/chandle

SystemVerilog: `chandle` data type

Author: kroening

CHANGELOG

@@ -6,6 +6,7 @@
 * Verilog: fix for nor/nand/xnor primitive gates
 * SystemVerilog: $bitstoreal/$bitstoshortreal, $realtobits/$shortrealtobits
 * SystemVerilog: $itor, $rtoi
+* SystemVerilog: chandle
 
 # EBMC 5.4
 

regression/verilog/data-types/chandle1.desc

@@ -0,0 +1,8 @@
+CORE
+chandle1.sv
+--bound 0
+^\[main\.p0\] always main\.some_handle == null: PROVED up to bound 0$
+^\[main\.p1\] always \$typename\(main\.some_handle\) == "chandle": PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/data-types/chandle1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // IEEE 1800-2017 6.14
+  chandle some_handle = null;
+
+  p0: assert final (some_handle == null);
+  p1: assert final ($typename(some_handle) == "chandle");
+
+endmodule

src/hw_cbmc_irep_ids.h

@@ -104,7 +104,8 @@ IREP_ID_ONE(verilog_value_range)
 IREP_ID_ONE(verilog_void)
 IREP_ID_ONE(verilog_streaming_concatenation_left_to_right)
 IREP_ID_ONE(verilog_streaming_concatenation_right_to_left)
-IREP_ID_ONE(chandle)
+IREP_ID_ONE(verilog_chandle)
+IREP_ID_ONE(verilog_null)
 IREP_ID_ONE(event)
 IREP_ID_ONE(reg)
 IREP_ID_ONE(macromodule)

src/verilog/Makefile

@@ -26,6 +26,7 @@ SRC = aval_bval_encoding.cpp \
       verilog_typecheck_base.cpp \
       verilog_typecheck_expr.cpp \
       verilog_typecheck_sva.cpp \
+      verilog_types.cpp \
       verilog_y.tab.cpp \
       vtype.cpp
 

src/verilog/expr2verilog.cpp

@@ -1260,6 +1260,15 @@ expr2verilogt::resultt expr2verilogt::convert_constant(
 
     dest += '"';
   }
+  else if(type.id() == ID_verilog_chandle)
+  {
+    if(src.get_value() == ID_NULL)
+    {
+      dest = "null";
+    }
+    else
+      return convert_norep(src, precedence);
+  }
   else
     return convert_norep(src, precedence);
 
@@ -2030,6 +2039,8 @@ std::string expr2verilogt::convert(const typet &type)
 
     return dest;
   }
+  else if(type.id() == ID_verilog_chandle)
+    return "chandle";
   else if(type.id() == ID_verilog_genvar)
     return "genvar";
   else if(type.id()==ID_integer)
@@ -2040,6 +2051,8 @@ std::string expr2verilogt::convert(const typet &type)
     return "real";
   else if(type.id()==ID_verilog_realtime)
     return "realtime";
+  else if(type.id() == ID_verilog_null)
+    return "null";
   else if(type.id() == ID_verilog_enum)
   {
     return "enum";

src/verilog/parser.y

@@ -1477,7 +1477,7 @@ data_type:
 	| TOK_STRING
 	        { init($$, ID_string); }
 	| TOK_CHANDLE
-	        { init($$, ID_chandle); }
+	        { init($$, ID_verilog_chandle); }
 	| TOK_VIRTUAL interface_opt interface_identifier
 	        { init($$, "virtual_interface"); }
 	| /*scope_opt*/ type_identifier packed_dimension_brace
@@ -4039,7 +4039,7 @@ primary:  primary_literal
 	| cast
 	| assignment_pattern_expression
 	| streaming_concatenation
-        | TOK_NULL { init($$, ID_NULL); }
+        | TOK_NULL { init($$, ID_verilog_null); }
         | TOK_THIS { init($$, ID_this); }
 	;
 

src/verilog/verilog_elaborate_type.cpp

@@ -383,6 +383,10 @@ typet verilog_typecheck_exprt::elaborate_type(const typet &src)
   {
     return src;
   }
+  else if(src.id() == ID_verilog_chandle)
+  {
+    return src;
+  }
   else
   {
     throw errort().with_location(source_location)

src/verilog/verilog_lowering.cpp

@@ -19,6 +19,7 @@ Author: Daniel Kroening, [email protected]
 #include "convert_literals.h"
 #include "verilog_bits.h"
 #include "verilog_expr.h"
+#include "verilog_types.h"
 
 /// Lowers
 /// * the three Verilog real types to floatbv;
@@ -42,6 +43,10 @@ typet verilog_lowering(typet type)
   {
     return lower_to_aval_bval(type);
   }
+  else if(type.id() == ID_verilog_chandle)
+  {
+    return to_verilog_chandle_type(type).encoding();
+  }
   else
     return type;
 }
@@ -347,9 +352,26 @@ exprt verilog_lowering(exprt expr)
       result.add_source_location() = expr.source_location();
       expr = std::move(result);
     }
+    else if(expr.type().id() == ID_verilog_chandle)
+    {
+      // this is 'null'
+      return to_verilog_chandle_type(expr.type()).null_expr();
+    }
 
     return expr;
   }
+  else if(expr.id() == ID_symbol)
+  {
+    auto &symbol_expr = to_symbol_expr(expr);
+    if(expr.type().id() == ID_verilog_chandle)
+    {
+      auto &chandle_type = to_verilog_chandle_type(expr.type());
+      return symbol_exprt{
+        symbol_expr.get_identifier(), chandle_type.encoding()};
+    }
+    else
+      return expr;
+  }
   else if(expr.id() == ID_concatenation)
   {
     if(

src/verilog/verilog_synthesis.cpp

@@ -3346,7 +3346,12 @@ void verilog_synthesist::synth_assignments(
   if(!symbol.is_state_var)
     post_process_wire(symbol.name, new_value);
 
-  equal_exprt equality_expr{symbol_expr(symbol, curr_or_next), new_value};
+  auto lhs = symbol_expr(symbol, curr_or_next);
+
+  DATA_INVARIANT(
+    lhs.type() == new_value.type(), "synth_assignments type consistency");
+
+  equal_exprt equality_expr{std::move(lhs), new_value};
 
   constraints.add_to_operands(std::move(equality_expr));
 }