Verilog: this

This adds support for the System Verilog 'this' keyword.

Author: kroening

regression/verilog/expressions/this1.desc

@@ -0,0 +1,7 @@
+CORE
+this1.sv
+
+^file .* line 3: 'this' outside of method$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/expressions/this1.sv

@@ -0,0 +1,5 @@
+module main;
+
+  wire y = this;
+
+endmodule

src/verilog/parser.y

@@ -3648,6 +3648,7 @@ primary:  primary_literal
 	| cast
 	| assignment_pattern_expression
         | TOK_NULL { init($$, ID_NULL); }
+        | TOK_THIS { init($$, ID_this); }
 	;
 
 primary_literal:

src/verilog/verilog_typecheck_expr.cpp

@@ -912,6 +912,11 @@ exprt verilog_typecheck_exprt::convert_nullary_expr(nullary_exprt expr)
     expr.type() = elaborate_type(expr.type());
     return std::move(expr);
   }
+  else if(expr.id() == ID_this)
+  {
+    throw errort().with_location(expr.source_location())
+      << "'this' outside of method";
+  }
   else
   {
     throw errort().with_location(expr.source_location())