KNOWNBUG test for parameter without default value

SystemVerilog 1800-2017 allows module parameter ports without default value.

Author: kroening

regression/verilog/modules/parameter_ports2.v

@@ -6,6 +6,6 @@ endmodule
 
 module main;
 
-  sub #(123) submodule();
+  sub #(8'd123) submodule();
 
 endmodule // main

regression/verilog/modules/parameter_without_default1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+parameter_without_default1.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.

regression/verilog/modules/parameter_without_default1.sv

@@ -0,0 +1,11 @@
+// P has no default value; allowed by 1800-2017 6.20.1
+module my_module #(P);
+
+endmodule
+
+module main;
+
+  // error: didn't give value for P
+  my_module m1();
+
+endmodule