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luizinhosuratyluizinhosuraty
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sw/kernel: Add kernel module to control the pciemu virtual device
Notes : - still missing tests with kunit. - less comments than hw part as the goal is to focus on the virtual device part
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‎include/sw/module/pciemu_ioctl.h

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/* pciemu_ioctl.h - IOCTL definitions
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*
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* Copyright (c) 2023 Luiz Henrique Suraty Filho <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#ifndef _PCIEMU_IOCTL_H_
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#define _PCIEMU_IOCTL_H_
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#define PCIEMU_IOCTL_MAGIC 0xE1
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#define PCIEMU_IOCTL_DMA_TO_DEVICE _IOW(PCIEMU_IOCTL_MAGIC, 1, void *)
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#define PCIEMU_IOCTL_DMA_FROM_DEVICE _IOR(PCIEMU_IOCTL_MAGIC, 2, void *)
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#endif /* _PCIEMU_IOCTL_H_ */

‎src/sw/kernel/.gitignore

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#
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# .gitignore copied from the linux kernel
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#
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## Adding the following for kernel modules
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*.mod
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.*
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*.o
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*.o.*
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*.a
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*.s
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*.ko
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*.so
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*.so.dbg
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*.mod.c
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*.i
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*.lst
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*.symtypes
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*.order
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modules.builtin
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*.elf
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*.bin
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*.gz
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*.bz2
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*.lzma
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*.xz
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*.lzo
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*.patch
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*.gcno
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#
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# Top-level generic files
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#
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/tags
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/TAGS
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/linux
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/vmlinux
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/vmlinuz
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/System.map
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/Module.markers
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/Module.symvers
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#
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# git files that we don't want to ignore even it they are dot-files
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#
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!.gitignore
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!.mailmap
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#
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# Generated include files
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#
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include/config
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include/linux/version.h
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include/generated
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arch/*/include/generated
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# stgit generated dirs
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patches-*
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# quilt's files
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patches
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series
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# cscope files
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cscope.*
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ncscope.*
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# gnu global files
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GPATH
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GRTAGS
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GSYMS
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GTAGS
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*.orig
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*~
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\#*#

‎src/sw/kernel/Makefile

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# Makefile for the kernel module
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#
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# Copyright (c) 2023 Luiz Henrique Suraty Filho <[email protected]>
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-m += pciemu.o
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pciemu-objs += pciemu_module.o pciemu_dma.o pciemu_irq.o
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ccflags-y=-I/hostdir/include
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all:
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make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
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clean:
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make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

‎src/sw/kernel/pciemu_dma.c

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/* pciemu_dma.c - pciemu virtual device DMA operations
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*
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* These are functions that map BARs inside the kernel module and
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* access them directly from the kernel module.
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*
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* Copyright (c) 2023 Luiz Henrique Suraty Filho <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include <linux/dma-mapping.h>
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#include "pciemu_module.h"
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#include "hw/pciemu_hw.h"
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static void pciemu_dma_struct_init(struct pciemu_dma *dma, size_t ofs,
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size_t len, enum dma_data_direction drctn)
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{
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dma->offset = ofs;
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dma->len = len;
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dma->direction = drctn;
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}
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int pciemu_dma_from_host_to_device(struct pciemu_dev *pciemu_dev,
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struct page *page, size_t ofs, size_t len)
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{
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struct pci_dev *pdev = pciemu_dev->pdev;
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void __iomem *mmio = pciemu_dev->bar.mmio;
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pciemu_dma_struct_init(&pciemu_dev->dma, ofs, len, DMA_TO_DEVICE);
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pciemu_dev->dma.dma_handle =
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dma_map_page(&(pdev->dev), page, pciemu_dev->dma.offset,
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pciemu_dev->dma.len, pciemu_dev->dma.direction);
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if (dma_mapping_error(&(pdev->dev), pciemu_dev->dma.dma_handle))
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return -ENOMEM;
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dev_dbg(&(pdev->dev), "dma_handle_from = %llx\n",
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(unsigned long long)pciemu_dev->dma.dma_handle);
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dev_dbg(&(pdev->dev), "cmd = %x\n", PCIEMU_HW_DMA_DIRECTION_TO_DEVICE);
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iowrite32((u32)pciemu_dev->dma.dma_handle,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_TXDESC_SRC);
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iowrite32(PCIEMU_HW_DMA_AREA_START,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_TXDESC_DST);
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iowrite32(pciemu_dev->dma.len,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_TXDESC_LEN);
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iowrite32(PCIEMU_HW_DMA_DIRECTION_TO_DEVICE,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_CMD);
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iowrite32(1, mmio + PCIEMU_HW_BAR0_DMA_DOORBELL_RING);
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dev_dbg(&(pdev->dev), "done host->device...\n");
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return 0;
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}
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int pciemu_dma_from_device_to_host(struct pciemu_dev *pciemu_dev,
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struct page *page, size_t ofs, size_t len)
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{
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struct pci_dev *pdev = pciemu_dev->pdev;
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void __iomem *mmio = pciemu_dev->bar.mmio;
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pciemu_dma_struct_init(&pciemu_dev->dma, ofs, len, DMA_FROM_DEVICE);
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pciemu_dev->dma.dma_handle =
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dma_map_page(&(pdev->dev), page, pciemu_dev->dma.offset,
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pciemu_dev->dma.len, pciemu_dev->dma.direction);
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if (dma_mapping_error(&(pdev->dev), pciemu_dev->dma.dma_handle))
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return -ENOMEM;
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dev_dbg(&(pdev->dev), "dma_handle_to = %llx\n",
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(unsigned long long)pciemu_dev->dma.dma_handle);
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dev_dbg(&(pdev->dev), "cmd = %x\n",
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PCIEMU_HW_DMA_DIRECTION_FROM_DEVICE);
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iowrite32(PCIEMU_HW_DMA_AREA_START,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_TXDESC_SRC);
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iowrite32((u32)pciemu_dev->dma.dma_handle,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_TXDESC_DST);
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iowrite32(pciemu_dev->dma.len,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_TXDESC_LEN);
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iowrite32(PCIEMU_HW_DMA_DIRECTION_FROM_DEVICE,
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mmio + PCIEMU_HW_BAR0_DMA_CFG_CMD);
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iowrite32(1, mmio + PCIEMU_HW_BAR0_DMA_DOORBELL_RING);
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dev_dbg(&(pdev->dev), "done device->host...\n\n");
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return 0;
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}

‎src/sw/kernel/pciemu_irq.c

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/* pciemu_irq.c - pciemu virtual device IRQ operations
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*
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* These are functions that configure IRQs and the appropriate handlers.
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*
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* Copyright (c) 2023 Luiz Henrique Suraty Filho <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include "hw/pciemu_hw.h"
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#include "pciemu_module.h"
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#include <linux/pci.h>
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static irqreturn_t pciemu_irq_handler(int irq, void *data)
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{
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struct pciemu_dev *pciemu_dev = data;
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dev_dbg(&pciemu_dev->pdev->dev, "irq_handler irq = %d dev = %d\n", irq,
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pciemu_dev->major);
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dma_unmap_page((&pciemu_dev->pdev->dev), pciemu_dev->dma.dma_handle,
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pciemu_dev->dma.len, pciemu_dev->dma.direction);
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unpin_user_page(pciemu_dev->dma.page);
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/* Must do this ACK, or else the interrupt just keeps firing. */
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iowrite32(1, pciemu_dev->irq.mmio_ack_irq);
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return IRQ_HANDLED;
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}
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static int pciemu_irq_enable_msi(struct pciemu_dev *pciemu_dev)
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{
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int msi_vecs_req;
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int msi_vecs;
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int err;
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/*
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* Reserve the max msi vectors we might need
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*/
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msi_vecs_req = min_t(int, pci_msi_vec_count(pciemu_dev->pdev),
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num_online_cpus() + 1);
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dev_dbg(&pciemu_dev->pdev->dev,
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"Trying to enable MSI, requesting %d vectors\n", msi_vecs_req);
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msi_vecs = pci_alloc_irq_vectors(pciemu_dev->pdev, msi_vecs_req,
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msi_vecs_req, PCI_IRQ_MSI);
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if (msi_vecs < 0) {
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dev_err(&pciemu_dev->pdev->dev,
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"pciemu_irq_enable_msi failed, vectors %d\n", msi_vecs);
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return -ENOSPC;
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}
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if (msi_vecs != msi_vecs_req) {
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pci_free_irq_vectors(pciemu_dev->pdev);
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dev_err(&pciemu_dev->pdev->dev,
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"allocated %d MSI (out of %d requested)\n", msi_vecs,
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msi_vecs_req);
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return -ENOSPC;
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}
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pciemu_dev->irq.irq_num = pci_irq_vector(
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pciemu_dev->pdev, PCIEMU_HW_IRQ_DMA_ENDED_VECTOR);
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if (pciemu_dev->irq.irq_num < 0) {
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pci_free_irq_vectors(pciemu_dev->pdev);
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dev_err(&pciemu_dev->pdev->dev, "vector %d out of range\n",
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PCIEMU_HW_IRQ_DMA_ENDED_VECTOR);
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return -EINVAL;
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}
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err = request_irq(pciemu_dev->irq.irq_num, pciemu_irq_handler,
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PCIEMU_HW_IRQ_DMA_ENDED_VECTOR,
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"pciemu_irq_dma_ended", pciemu_dev);
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if (err) {
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dev_err(&pciemu_dev->pdev->dev,
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"failed to request irq %s (%d)\n",
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"pciemu_irq_dma_ended", err);
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pci_free_irq_vectors(pciemu_dev->pdev);
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return err;
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}
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pciemu_dev->irq.mmio_ack_irq =
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pciemu_dev->bar.mmio + PCIEMU_HW_IRQ_DMA_ACK_ADDR;
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return 0;
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}
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int pciemu_irq_enable(struct pciemu_dev *pciemu_dev)
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{
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return pciemu_irq_enable_msi(pciemu_dev);
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}

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