01.srt

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字幕校对:米哈游天下第一

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哈喽,大家好,问君能有几多愁,未到三旬又秃头的 ZOMI

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来到通用处理器 CPU 这一个章节内容

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今天回顾一下在整个 AI 芯片基础里面

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会从 CPU 到 GPU 再到 NPU

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然后再到了计算体系架构的黄金十年

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也就是超异构体系里面

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现在还是在通用处理器 CPU 这个内容

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这个内容可能会稍微有点多

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我会分开两个视频给大家去汇报的

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首先在今天我要去汇报一下

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CPU 的整体的发展历史和组成

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还有 CPU 的并行处理的架构

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现在开始第一个内容就是 CPU 的发展历史

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还有它的组成

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从发展去看它的组成

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其实世界上的第一台真正意义的计算机

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是在 1946 年的时候

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美国宾夕法利亚大学投入运行的

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当时候采用的还不是二进制

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而是十进制的数据进行处理

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那这台计算机叫做

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ENIAC 电子数字积分计算机

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ENIAC 电子数字积分计算机

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不知道大家认不认识里面的这两位美女

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现在看看世界第一台二进制的计算器

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那这台计算机其实是由冯诺依曼

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或者冯诺依曼教授去发明的

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名字叫做 EDVC 电子离散变量的自动计算机

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这里面提到冯诺依曼就很有意思了

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通过这一台计算机

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冯诺依曼就提出了他经典的冯诺依曼架构

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冯诺依曼就提出了他经典的冯诺依曼架构

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由运算器、控制器、存储器还有输出

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就是 IO 五个部分去组成

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那聊到计算机的发展历史

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就离不开计算机的组成

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直到现今为止

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无论 CPU 经过了多少代的变化

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或者晶体管的数量翻了多少番

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它的整个的组成或者构成

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有五个部分组成

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第一个就是输出、输入

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那这个可以避而不谈

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最重要的就是中间三部分

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控制单元、计算单元、ALU 还有内存单元

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通过这三个部分来组成整个 CPU 的最重要的核心内容

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中央控制处理器

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当然这里面其实只是一个简图

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实际上中央处理单元

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它的整个连线、整个 IO

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整个具体的控制流程是非常的复杂的

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接着往下看一看

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这些单元之间是怎么互相配合的

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第一个内容叫做运算器

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运算器叫做 ALU

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也叫做算术逻辑单元

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主要是负责算术的运算和逻辑的运算

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什么叫做算术运算和逻辑运算呢?

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简单的来说

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算术运算就是加减乘除

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逻辑运算就是与 或 非 异或这些内容

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输进去有可能有两个数据

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然后输出来的是一个数据

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中间还穿插一些状态码

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这个就是运算器了

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而整体的运算器也是由逻辑控制门来去组成的

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接着看看第二个内容

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寄存器

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寄存器其实分为指令寄存器和数据寄存器

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主要是两种负责一些

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暂存指令

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command

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还有 ALU 的一些操作

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ALU 算出来的结果

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往左边看一下

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整个寄存器可以有非常多不同的寄存器

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有指令寄存器、地址寄存器、累积寄存器、编程寄存器

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而很多时候完全这些寄存器是由控制单元去控制

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它什么时候存什么

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什么时候发生什么作用

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最后控制单元根据寄存器的内容

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下发到运算器 ALU 里面

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那往右边的这个图举两个简单的例子

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首先数据寄存器

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叫做 DR

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它的 bit 位宽是 16 位

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主要是存储一些临时的指令

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可以看到有非常多不同的寄存器

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不同的寄存器

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它有自己不同的作用

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也有不同的位宽

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还有自己不同的一个符号位表示

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往下看就是最重要的一个功能

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控制器负责整体的调度的工作

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包括对刚才的一些指令进行一个编码、解码

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然后从内存里面把数据读取出来

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给到寄存器

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然后向一些运算器 ALU 或者寄存器

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发出具体的指令操作

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那这个就是控制器

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也相当于整个 CPU 的大脑

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所以可以说 CPU 里面非常核心的一块

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就是控制单元控制器

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接下来看一下整个 CPU 的工作流程

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就是它的 workflow

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首先主要分开为四步

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刚才讲到了很重要的就是三个内容

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控制单元、计算单元还有内存

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那第一步就是从内存里面去读取一些指令

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给到控制单元

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控制单元就会进行

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对刚才读取的一些指令来进行解码

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变成正式的一些 command 命令

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然后 ALU 就会去执行这些 command 这些命令

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执行完之后就会存储回来内存

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汇总起来就是这四步

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内存里面读取指令、解码、执行、写回

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就是这四个工作流程

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接下来以下面这个代码例子

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ax+y（误）这么简单的一个线性操作

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看看 CPU 的三大组成是怎么分工的

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那现在可以看到

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其实里面的 double alpha

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这个就是存储

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double x 也是存储

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double y 也是存储

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包括 n 等于 2000（误）

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Int i 等于 0

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这些都是内存

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把数据存储起来的

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接着控制器就会去内存里面

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把刚才这些数据都读取出来

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读取出来之后

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真正的去运行的

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其实只有这个*和+

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就是 ALU 真正运行的

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就这么两个操作

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而这里面的 For 循环迭代

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什么时候 i++

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什么时候去相乘

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什么时候相加

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全都是由控制器去组成的

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所以可以说

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控制器和寄存器

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负责的工作是最多的

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要存储的数据

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也是最多的两个部分

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因为刚才虽然说

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这些数据都是从内存里面读出来

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但实际在运行之前

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控制器会把这些数据

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搬到寄存器里面

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然后再给 ALU 去执行

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这里面可以看到

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大量的数据交互

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大量的控制逻辑

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而真正的计算只有*和+两个

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下面回到中央处理器

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这个图可能稍微比刚才那个图

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多了一行寄存器

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就是因为刚才讲到了

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控制单元、计算单元、内存

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实际上有寄存器

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在真正执行的时候

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就会把内存的数据放到寄存器

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然后控制单元

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控制什么时候把寄存器的数据

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给到计算单元去执行

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执行完之后

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就把计算单元的结果输出

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或者放到寄存器里面

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又或者放回内存里面

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就是这么简单的一个操作

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这么简单的一个架构

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沿用至今

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CPU 的整体架构

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基本上就没有太多的变化了

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接下来看看

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CPU 的一个架构图

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下面就是整个 CPU 的架构图

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一个简图

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首先 DRAM 就是内存

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内存里面之后

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有一级的 Cache

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有二级的 Cache

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这些其实都可以当做是内存

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然后有控制器

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真正的执行单元

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就是 ALU

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可以看到

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真正执行单元的 ALU

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占的面积是非常的小的

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这里面有四个 ALU

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假设有四个 ALU 或者计算盒

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在整体电路里面

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占的绝大部分的

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就是内存

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还有控制器

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而并非计算

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所以说 CPU 是非常适合

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擅长处理逻辑控制

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而并非计算

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真正你要让计算非常好

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所以又有了 GPU

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有了 NPU

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这些后话

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后面会给大家介绍的

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下面来看一下

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CPU 的约束和限制

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实际上计算单元

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也就是 ALU

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逻辑计算单元

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它只要是用来完成

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整体的数据的计算

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其他的模块

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包括控制器

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为的就是能够

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让指令

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一条一条有序的去执行

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另外方面

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还可以提高 CPU 的主频

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也就是提高

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单位时间内的

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执行指令的条数

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来提升整体的计算的速度

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传统的 CPU

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因为这种方式

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能够很方便的去写

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非常多的应用的代码

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不过有一点值得注意的

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就是像冯诺依曼架构

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这种对指令的

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顺序执行的原则

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就保证了 CPU

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每一次只能执行一条指令

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会存在多核的情况

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一次的话可以执行多条指令

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因为原则上

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大原则受限于顺序执行

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所以计算能力的提升

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是受到限制的

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00:09:12,200 --> 00:09:15,200
于是引入了第二个内容

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也就是本节的第二章

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并行处理的架构

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00:09:18,200 --> 00:09:20,200
在并行处理架构里面

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主要有四种方式

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其实最原始的 CPU

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00:09:24,200 --> 00:09:25,200
就是单指令流

250
00:09:25,200 --> 00:09:27,175
单数据流这种方式

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第二种就是 SIMD

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00:09:27,200 --> 00:09:30,175
第二种就是 SIMD

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00:09:30,200 --> 00:09:31,200
现在来说用的最多的

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00:09:31,200 --> 00:09:32,200
包括现代的 CPU

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英特尔的

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00:09:33,200 --> 00:09:34,200
还有 AMD 的 CPU

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00:09:34,200 --> 00:09:36,200
都是 SIMB 的架构

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00:09:36,200 --> 00:09:38,200
而 MISD 和 MIND

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反倒用的比较少

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00:09:39,200 --> 00:09:41,200
下面来看看具体的例子

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它们有哪些不一样

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00:09:43,200 --> 00:09:45,200
下面来到第一个内容

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SISD Single Instruction Single Data

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00:09:48,200 --> 00:09:50,200
PU 就是 Processing Unit

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执行单元

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00:09:51,200 --> 00:09:53,200
每一次从指令流里面

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单独读取一条指令

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00:09:55,200 --> 00:09:56,200
然后从数据流里面

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单独取一条数据

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然后进行计算

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最后输出

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00:10:00,200 --> 00:10:02,200
这种方式是串行的去执行的

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00:10:02,200 --> 00:10:04,200
硬件是不支持并行的方式

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00:10:04,200 --> 00:10:06,200
而且在每一个时钟周期内

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CPU 只能够处理一个数据流

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举的最简单的例子

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就是我的指令

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做一个加法的操作

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于是我就会在数据流里面

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读取两个数据 A 和 B

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然后执行一个加法的操作

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最后输出一个 C

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这么简单的

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就是 SISD

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接下来看一下

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00:10:24,200 --> 00:10:27,200
第二个并行的硬件处理的架构

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SIMD

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SIMD 就有点意思了

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就是 Single Instruction Multi Data

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00:10:34,200 --> 00:10:35,200
指令流呢

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00:10:35,200 --> 00:10:36,200
只有一个指令

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00:10:36,200 --> 00:10:37,200
但是数据呢

293
00:10:37,200 --> 00:10:38,200
可以有多个数据

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00:10:38,200 --> 00:10:39,200
从右边的这个图

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可以看到

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00:10:40,200 --> 00:10:42,200
首先读取一条指令

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00:10:42,200 --> 00:10:45,200
这条指令假设都是加法操作

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00:10:45,200 --> 00:10:46,200
从数据流里面呢

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00:10:46,200 --> 00:10:48,200
读取不同的数据出来

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00:10:48,200 --> 00:10:50,200
最后或许计算并行的去计算

301
00:10:50,200 --> 00:10:53,200
可以看到从左边 A1 A2 A3

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00:10:53,200 --> 00:10:55,200
同时进行一个加法的操作

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00:10:55,200 --> 00:10:56,200
B1 B2 B3

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00:10:56,200 --> 00:10:58,200
所以叫做单指令流

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00:10:58,200 --> 00:11:00,200
多数据的这种方式

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00:11:00,200 --> 00:11:01,200
加法只有一个

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00:11:01,200 --> 00:11:02,200
但是数据呢

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00:11:02,200 --> 00:11:03,200
有很多个

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00:11:03,200 --> 00:11:04,200
这种的特点呢

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就是处理单元非常多

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可以看到 PU 呢

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非常多

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00:11:08,200 --> 00:11:09,200
缺点呢

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00:11:09,200 --> 00:11:10,200
就是处理的速度呢

315
00:11:10,200 --> 00:11:13,200
会受到计算的通讯的带宽

316
00:11:13,200 --> 00:11:16,200
还有通讯的延时等限制

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可以看到最大的限制

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00:11:17,200 --> 00:11:19,200
就是数据的读取的方式

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00:11:19,200 --> 00:11:21,200
指令的读取方式是很快的

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00:11:21,200 --> 00:11:24,200
从寄存器里面去读取指令

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00:11:24,200 --> 00:11:26,200
数据呢就特别的慢了

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接着呢

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00:11:27,200 --> 00:11:30,200
看一下第三个并行处理架构

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就是 MISD Multi Instruction and Single Data

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00:11:34,200 --> 00:11:35,200
这里面呢

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00:11:35,200 --> 00:11:36,200
多指令流

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00:11:36,200 --> 00:11:37,200
单数据呢就很有意思

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00:11:37,200 --> 00:11:39,200
指令流是分开多个的

329
00:11:39,200 --> 00:11:40,200
但是呢

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数据只有比较简单的一种

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那下面可以看到

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00:11:45,200 --> 00:11:47,200
左边的这个就是加减层

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00:11:47,200 --> 00:11:50,200
都有不同的计算的指令

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00:11:50,200 --> 00:11:51,200
但是呢

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00:11:51,200 --> 00:11:52,200
输入的数据呢

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00:11:52,200 --> 00:11:53,200
只有一种最后呢

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00:11:53,200 --> 00:11:54,200
输出数据

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00:11:54,200 --> 00:11:55,200
这种呢

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00:11:55,200 --> 00:11:56,200
其实可以看到

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00:11:56,200 --> 00:11:57,200
像这种奇奇怪怪的计算

341
00:11:57,200 --> 00:11:59,200
其实我至少从你来看呢

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00:11:59,200 --> 00:12:00,200
很少能够见到

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00:12:00,200 --> 00:12:02,200
所以作为一种理论的模型

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00:12:02,200 --> 00:12:05,200
并没有在实际应用当中去投产的

345
00:12:05,200 --> 00:12:06,200
所以可以看到

346
00:12:06,200 --> 00:12:07,200
类似于这种架构的芯片呢

347
00:12:07,200 --> 00:12:09,200
是非常非常的少

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00:12:09,200 --> 00:12:11,200
那最后一个就是 MIMD 了

349
00:12:11,200 --> 00:12:14,200
Multi Instruction Multi Data

350
00:12:14,200 --> 00:12:15,200
在多个数据集上面呢

351
00:12:15,200 --> 00:12:17,200
去执行多个指令流

352
00:12:17,200 --> 00:12:18,200
这种呢

353
00:12:18,200 --> 00:12:20,200
又分为共享内存 MIMD

354
00:12:20,200 --> 00:12:22,200
和分布式内存

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00:12:22,200 --> 00:12:24,200
就分开两种 MIMD

356
00:12:24,200 --> 00:12:25,200
一种是共享内存

357
00:12:25,200 --> 00:12:27,200
一种是分布式内存

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00:12:27,200 --> 00:12:28,200
那现在先看看

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00:12:28,200 --> 00:12:29,200
共享内存主要是指

360
00:12:29,200 --> 00:12:31,200
在整个 CPU

361
00:12:31,200 --> 00:12:33,200
或者在整个芯片系列里面呢

362
00:12:33,200 --> 00:12:35,200
共享所有的全局的内存

363
00:12:35,200 --> 00:12:36,200
而分布式呢

364
00:12:36,200 --> 00:12:40,200
就是跨机器进行内存的共享

365
00:12:40,200 --> 00:12:41,200
而内存共享呢

366
00:12:41,200 --> 00:12:42,200
又可以通过进程间

367
00:12:42,200 --> 00:12:44,200
进行通讯各种方式

368
00:12:44,200 --> 00:12:45,200
但是呢

369
00:12:45,200 --> 00:12:46,200
这种说实话

370
00:12:46,200 --> 00:12:47,200
用的也是比较少的

371
00:12:47,200 --> 00:12:49,200
另外用的更多的

372
00:12:49,200 --> 00:12:51,200
是 SIMT

373
00:12:51,200 --> 00:12:52,200
像 GPU 呢

374
00:12:52,200 --> 00:12:54,200
就是 SIMD 的

375
00:12:54,200 --> 00:12:55,200
另外一种演进

376
00:12:55,200 --> 00:12:57,200
变成 SIMT

377
00:12:57,200 --> 00:13:00,200
把 Data 变成 Flat

378
00:13:00,200 --> 00:13:01,200
变成线程

379
00:13:01,200 --> 00:13:03,200
单指令多线程

380
00:13:03,200 --> 00:13:04,200
右边的这个呢

381
00:13:04,200 --> 00:13:06,200
就是 GPU 的基本架构

382
00:13:06,200 --> 00:13:07,200
它可以有效的管理和执行

383
00:13:07,200 --> 00:13:10,200
非常非常多的线程

384
00:13:10,200 --> 00:13:11,200
SP 呢

385
00:13:11,200 --> 00:13:13,200
就是其中的一个线程执行器

386
00:13:14,200 --> 00:13:15,200
芯片里面呢

387
00:13:15,200 --> 00:13:16,200
就允许一条指令呢

388
00:13:16,200 --> 00:13:19,200
多个数据分开寻址

389
00:13:19,200 --> 00:13:20,200
好了

390
00:13:20,200 --> 00:13:21,200
今天的内容呢

391
00:13:21,200 --> 00:13:22,200
就这么多了

392
00:13:22,200 --> 00:13:23,200
有点水

393
00:13:23,200 --> 00:13:24,200
简单的回顾了一下

394
00:13:24,200 --> 00:13:25,200
CPU 的发展历史

395
00:13:25,200 --> 00:13:26,200
它的组成

396
00:13:26,200 --> 00:13:27,200
另外还看了

397
00:13:27,200 --> 00:13:29,200
CPU 的并行的架构

398
00:13:29,200 --> 00:13:30,200
从 SISD 呢

399
00:13:30,200 --> 00:13:32,200
到 SIMD 到 SIMT

400
00:13:32,200 --> 00:13:34,200
它的一个发展的脉络

401
00:13:34,200 --> 00:13:35,200
在接下来的内容

402
00:13:35,200 --> 00:13:36,200
看看

403
00:13:36,200 --> 00:13:37,200
ISA 指令集的架构

404
00:13:37,200 --> 00:13:39,200
还有 CPU 的应用场景

405
00:13:39,200 --> 00:13:40,200
今天内容到这里为止

406
00:13:40,200 --> 00:13:41,200
谢谢各位

407
00:13:41,200 --> 00:13:42,571
拜了个拜

408
00:13:43,078 --> 00:13:44,419
卷的不行了卷的不行了

409
00:13:44,419 --> 00:13:46,175
记得一键三连加关注哦

410
00:13:46,175 --> 00:13:46,200
所有的内容都会开源在下面这条链接里面

411
00:13:46,200 --> 00:13:49,750
所有的内容都会开源在下面这条链接里面

412
00:13:49,775 --> 00:13:51,775
拜了个拜