From d0ebc219a4be047b73df4e534b379f944ad0d733 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Mon, 17 Feb 2025 21:18:42 +0100 Subject: [PATCH 1/8] WIP: first split idea + suggested better solutions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit See PR comment (or below), for different and probably better approaches This way has been chosen for this WIP commit - to show clearly how many places'd need to be cluttered with feature flags. 1. approach no 1: - ./ci.sh indicates, that "st25r3916" is first class impl, and all others impls need to remove defaults and provide their own impl, when incompatible/different. + Cumbersome, however requires the least changes in the current codebase - slight relocations and some feature flags. Separate code for `s25r3911b` lives in nested module. * I don't prefer this solution, but it's 1st choice in PR - to show how many changes are needed to code, for them to be compatible. Minimal (?) changes to original, and st25r3911b modified only to get the code even to complile, but unlikely to work. 2. approach no 2: - "st25r3916", "st25r3911b" and any future others, are treated equally. Needs facade in `lib.rs` to detect chip? Needs moving lib.rs code to lib_st25r3916 (or sth like it). Possibly - if desired, have mocks to allow building with empty feature set, `default = []` without "Commands" and "Regs" specific to chip Might be the best approach, however would require substantial changes to current code. 3. approach no 3: - impls live in separate crates (maybe using some sort of common `st25r39`) - reduces burden of feature-cfg-disables. Signed-off-by: Krzysztof Królczyk --- ci.sh | 3 + rnfc-st25r39/Cargo.toml | 5 +- rnfc-st25r39/src/aat.rs | 13 + rnfc-st25r39/src/commands/mod.rs | 9 + rnfc-st25r39/src/commands/st25r3911b.rs | 68 + rnfc-st25r39/src/commands/st25r3916.rs | 70 + rnfc-st25r39/src/iso14443a.rs | 34 +- rnfc-st25r39/src/lib.rs | 103 +- rnfc-st25r39/src/lib_st25r3911b.rs | 538 ++++ rnfc-st25r39/src/lib_st25r3916.rs | 6 + rnfc-st25r39/src/regs_st25r3911b.rs | 2756 +++++++++++++++++ .../src/{regs.rs => regs_st25r3916.rs} | 0 .../src/yaml-regmaps/regs-st25r3911b.yaml | 1349 ++++++++ .../regs-st25r3916.yaml} | 0 14 files changed, 4877 insertions(+), 77 deletions(-) create mode 100644 rnfc-st25r39/src/commands/mod.rs create mode 100644 rnfc-st25r39/src/commands/st25r3911b.rs create mode 100644 rnfc-st25r39/src/commands/st25r3916.rs create mode 100644 rnfc-st25r39/src/lib_st25r3911b.rs create mode 100644 rnfc-st25r39/src/lib_st25r3916.rs create mode 100644 rnfc-st25r39/src/regs_st25r3911b.rs rename rnfc-st25r39/src/{regs.rs => regs_st25r3916.rs} (100%) create mode 100644 rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml rename rnfc-st25r39/src/{regs.yaml => yaml-regmaps/regs-st25r3916.yaml} (100%) diff --git a/ci.sh b/ci.sh index cb45679..5661cac 100755 --- a/ci.sh +++ b/ci.sh @@ -20,6 +20,9 @@ cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features 'log' cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features '' cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'defmt' cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'log' +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --no-default-features --features 'st25r3911b' +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --no-default-features --features 'st25r3911b,defmt' +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --no-default-features --features 'st25r3911b,log' cargo build --release --manifest-path rnfc-acr122u/Cargo.toml --features '' diff --git a/rnfc-st25r39/Cargo.toml b/rnfc-st25r39/Cargo.toml index 075aec2..bbccae7 100644 --- a/rnfc-st25r39/Cargo.toml +++ b/rnfc-st25r39/Cargo.toml @@ -5,6 +5,9 @@ edition = "2021" [features] defmt = [ "dep:defmt", "rnfc-traits/defmt", "heapless/defmt-03" ] +st25r3916 = [] +st25r3911b = [] +default = [ "st25r3916" ] [dependencies] defmt = { version = "0.3", optional = true } @@ -13,6 +16,6 @@ log = { version = "0.4.14", optional = true } embassy-time = { version = "0.4" } embassy-futures = { version = "0.1.1" } rnfc-traits = { version = "0.1.0", path = "../rnfc-traits" } -heapless = "0.8" +heapless = "0.8" embedded-hal = { version = "1" } embedded-hal-async = { version = "1" } diff --git a/rnfc-st25r39/src/aat.rs b/rnfc-st25r39/src/aat.rs index 0083cb2..3428743 100644 --- a/rnfc-st25r39/src/aat.rs +++ b/rnfc-st25r39/src/aat.rs @@ -54,14 +54,27 @@ impl St25r39 { a = new_a; b = new_b; } + #[cfg(not(feature = "st25r3911b"))] self.regs().ant_tune_a().write_value(a)?; + #[cfg(not(feature = "st25r3911b"))] self.regs().ant_tune_a().write_value(b)?; + // st25r3911b chip might offer a better approach, simlar to what lib does + // self.regs().ant_tune_ctrl().write(|v| v.set_tre(1)) ect + // and whole procedure might need to be adjusted, + // to take "CalibrateAntenna" command into account, ant_tune_target ect + #[cfg(feature = "st25r3911b")] + self.regs().ant_tune_ctrl().write_value(a.into())?; + #[cfg(feature = "st25r3911b")] + self.regs().ant_tune_ctrl().write_value(b.into())?; + Ok(()) } async fn aat_measure(&mut self, a: u8, b: u8, conf: &AatConfig) -> Result> { + #[cfg(not(feature = "st25r3911b"))] self.regs().ant_tune_a().write_value(a)?; + #[cfg(not(feature = "st25r3911b"))] self.regs().ant_tune_a().write_value(b)?; // Wait for caps to settle. diff --git a/rnfc-st25r39/src/commands/mod.rs b/rnfc-st25r39/src/commands/mod.rs new file mode 100644 index 0000000..dd03a12 --- /dev/null +++ b/rnfc-st25r39/src/commands/mod.rs @@ -0,0 +1,9 @@ +#[cfg(feature = "st25r3916")] +pub mod st25r3916; +#[cfg(feature = "st25r3916")] +pub use st25r3916::Command; + +#[cfg(feature = "st25r3911b")] +pub mod st25r3911b; +#[cfg(feature = "st25r3911b")] +pub use st25r3911b::Command; diff --git a/rnfc-st25r39/src/commands/st25r3911b.rs b/rnfc-st25r39/src/commands/st25r3911b.rs new file mode 100644 index 0000000..902c5d8 --- /dev/null +++ b/rnfc-st25r39/src/commands/st25r3911b.rs @@ -0,0 +1,68 @@ +/// Direct commands +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[allow(unused)] +pub enum Command { + /// Puts the chip in default state (same as after power-up) + SetDefault = 0xC1, + /// Stops all activities and clears FIFO same as C3 + Stop = 0xC2, + /// Stops all activities and clears FIFO same as C2 + Clear = 0xC3, + /// Transmit with CRC + TransmitWithCrc = 0xC4, + /// Transmit without CRC + TransmitWithoutCrc = 0xC5, + /// Transmit REQA + TransmitReqa = 0xC6, + /// Transmit WUPA + TransmitWupa = 0xC7, + /// NFC transmit with Initial RF Collision Avoidance + InitialRfCollision = 0xC8, + /// NFC transmit with Response RF Collision Avoidance + ResponseRfCollisionN = 0xC9, + /// NFC transmit with Response RF Collision Avoidance with n=0 + ResponseRfCollisionNzero = 0xCA, + /// Accepted in NFCIP-1 active communication bitrate detection mode + GotoNormalNFCMode = 0xCB, + /// Presets Rx and Tx configuration based on state of Mode definition register and Bit rate definition register + PresetAnalog = 0xCC, + /// Mask receive data + MaskReceiveData = 0xD0, + /// Unmask receive data + UnmaskReceiveData = 0xD1, + /// Measure singal amplitude on RFI inputs + MeasureAmplitude = 0xD3, + /// Performs gain reduction based on the current noise level + Squelch = 0xD4, + /// Reset RX Gain + ResetRxgain = 0xD5, + /// Adjust regulators + AdjustRegulators = 0xD6, + /// Starts sequence that activates the Tx, measures the modulation depth, and adapts it to comply with the specified modulation depth + CalibrateModDepth = 0xD7, + /// Starts the sequence to adjust parallel capacitances connected to TRIMx_y pins so that the antenna LC tank is in resonance + CalibrateAntenna = 0xD8, + /// Measurement of phase difference between the signal on RFO and RFI + MeasurePhase = 0xD9, + /// Clear RSSI bits and restart the measurement + ClearRssi = 0xDA, + /// Amplitude of signal present on RFI inputs is measured, result is stored in A/D converter output register + TransparentMode = 0xDC, + /// Calibrate the capacitive sensor + CalibrateCSensor = 0xDD, + /// Measure capacitance sensor + MeasureCapacitance = 0xDE, + /// Measure power supply voltage + MeasureVdd = 0xDF, + /// Start the general purpose timer + StartGpTimer = 0xE0, + /// Start the wake-up timer + StartWupTimer = 0xE1, + /// Start the mask-receive timer + StartMaskReceiveTimer = 0xE2, + /// Start the no-response timer + StartNoResponseTimer = 0xE3, + /// Enable R/W access to the test registers + TestAccess = 0xFC, +} diff --git a/rnfc-st25r39/src/commands/st25r3916.rs b/rnfc-st25r39/src/commands/st25r3916.rs new file mode 100644 index 0000000..bc2723b --- /dev/null +++ b/rnfc-st25r39/src/commands/st25r3916.rs @@ -0,0 +1,70 @@ +/// Direct commands +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[allow(unused)] +pub enum Command { + /// Puts the chip in default state (same as after power-up) + SetDefault = 0xC1, + /// Stops all activities and clears FIFO + Stop = 0xC2, + /// Transmit with CRC + TransmitWithCrc = 0xC4, + /// Transmit without CRC + TransmitWithoutCrc = 0xC5, + /// Transmit REQA + TransmitReqa = 0xC6, + /// Transmit WUPA + TransmitWupa = 0xC7, + /// NFC transmit with Initial RF Collision Avoidance + InitialRfCollision = 0xC8, + /// NFC transmit with Response RF Collision Avoidance + ResponseRfCollisionN = 0xC9, + /// Passive target logic to Sense/Idle state + GotoSense = 0xCD, + /// Passive target logic to Sleep/Halt state + GotoSleep = 0xCE, + /// Mask receive data + MaskReceiveData = 0xD0, + /// Unmask receive data + UnmaskReceiveData = 0xD1, + /// AM Modulation state change + AmModStateChange = 0xD2, + /// Measure singal amplitude on RFI inputs + MeasureAmplitude = 0xD3, + /// Reset RX Gain + ResetRxgain = 0xD5, + /// Adjust regulators + AdjustRegulators = 0xD6, + /// Starts the sequence to adjust the driver timing + CalibrateDriverTiming = 0xD8, + /// Measure phase between RFO and RFI signal + MeasurePhase = 0xD9, + /// Clear RSSI bits and restart the measurement + ClearRssi = 0xDA, + /// Clears FIFO, Collision and IRQ status + ClearFifo = 0xDB, + /// Transparent mode + TransparentMode = 0xDC, + /// Calibrate the capacitive sensor + CalibrateCSensor = 0xDD, + /// Measure capacitance + MeasureCapacitance = 0xDE, + /// Measure power supply voltage + MeasureVdd = 0xDF, + /// Start the general purpose timer + StartGpTimer = 0xE0, + /// Start the wake-up timer + StartWupTimer = 0xE1, + /// Start the mask-receive timer + StartMaskReceiveTimer = 0xE2, + /// Start the no-response timer + StartNoResponseTimer = 0xE3, + /// Start PPon2 timer + StartPpon2Timer = 0xE4, + /// Stop No Response Timer + StopNrt = 0xE8, + /// Enable R/W access to the test registers + SpaceBAccess = 0xFB, + /// Enable R/W access to the test registers + TestAccess = 0xFC, +} diff --git a/rnfc-st25r39/src/iso14443a.rs b/rnfc-st25r39/src/iso14443a.rs index 2203cce..12b97d2 100644 --- a/rnfc-st25r39/src/iso14443a.rs +++ b/rnfc-st25r39/src/iso14443a.rs @@ -124,6 +124,8 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 (false, Command::TransmitWithCrc) } }; + + #[cfg(not(feature = "st25r3911b"))] this.regs().corr_conf1().write(|w| { w.0 = 0x13; w.set_corr_s6(!is_anticoll); @@ -139,7 +141,10 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 // Disable Automatic Gain Control (AGC) for better detection of collisions if using Coherent Receiver w.set_agc_en(!is_anticoll); w.set_agc_m(true); // AGC operates during complete receive period - w.set_agc6_3(true); // 0: AGC ratio 3 + #[cfg(not(feature = "st25r3911b"))] + { + w.set_agc6_3(true); // 0: AGC ratio 3 + } w.set_sqm_dyn(true); // Automatic squelch activation after end of TX })?; @@ -147,11 +152,29 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 this.cmd(cmd)?; // Wait for tx ended + #[cfg(not(feature = "st25r3911b"))] this.irq_wait(Interrupt::Txe).await?; + // #[cfg(feature = "st25r3911b")] + // this.irq_wait(|| this.regs().irq_main().read().expect("be readable").txe()).await?; // Wait for RX started + #[cfg(not(feature = "st25r3911b"))] + this.irq_wait_timeout(Interrupt::Rxs, Duration::from_millis(fwt_ms as _)) + .await?; + // #[cfg(feature = "st25r3911b")] + // this.irq_wait_timeout( + // || this.regs().irq_main().read().expect("be readable").rxs(), + // Duration::from_millis(fwt_ms as _)); + #[cfg(feature = "st25r3911b")] + let _ = fwt_ms; + + #[cfg(not(feature = "st25r3911b"))] this.irq_wait_timeout(Interrupt::Rxs, Duration::from_millis(fwt_ms as _)) .await?; + // #[cfg(feature = "st25r3911b")] + // with_timeout(Duration::from_millis(fwt_ms as _), + // async { this.regs().irq_main().read().expect("read reg ok").txe() } + // ); // Wait for rx ended or error // The timeout should never hit, it's just for safety. @@ -201,7 +224,14 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 } let mut rx_bytes = this.regs().fifo_status1().read()? as usize; - rx_bytes |= (stat.fifo_b() as usize) << 8; + #[cfg(not(feature = "st25r3911b"))] + { + rx_bytes |= (stat.fifo_b() as usize) << 8; + } + #[cfg(feature = "st25r3911b")] + { + rx_bytes |= (stat.fifo_lb() as usize) << 8; + } if let ll::Frame::Anticoll { bits } = opts { let full_bytes = bits / 8; diff --git a/rnfc-st25r39/src/lib.rs b/rnfc-st25r39/src/lib.rs index 89b202b..6f9e0c6 100644 --- a/rnfc-st25r39/src/lib.rs +++ b/rnfc-st25r39/src/lib.rs @@ -6,19 +6,38 @@ mod fmt; mod aat; +pub mod commands; mod interface; pub mod iso14443a; -mod regs; +#[cfg(feature = "st25r3911b")] +mod lib_st25r3911b; +#[cfg(feature = "st25r3911b")] +mod regs_st25r3911b; +#[cfg(feature = "st25r3916")] +mod regs_st25r3916; +#[cfg(feature = "st25r3916")] +use self::regs_st25r3916::Regs; +#[cfg(feature = "st25r3916")] +mod lib_st25r3916; +pub mod regs { + #[doc(inline)] + #[cfg(feature = "st25r3911b")] + pub use super::regs_st25r3911b::*; + #[doc(inline)] + #[cfg(feature = "st25r3916")] + pub use super::regs_st25r3916::*; +} pub use aat::AatConfig; +pub use commands::Command; use embassy_futures::yield_now; -use embassy_time::{Duration, Instant}; +use embassy_time::Duration; +#[cfg(feature = "st25r3916")] +use embassy_time::Instant; use embedded_hal::digital::InputPin; use embedded_hal_async::digital::Wait; pub use interface::{I2cInterface, Interface, SpiInterface}; -use self::regs::Regs; - const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -28,80 +47,13 @@ pub enum Error { Timeout, } -/// Direct commands -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[allow(unused)] -enum Command { - /// Puts the chip in default state (same as after power-up) - SetDefault = 0xC1, - /// Stops all activities and clears FIFO - Stop = 0xC2, - /// Transmit with CRC - TransmitWithCrc = 0xC4, - /// Transmit without CRC - TransmitWithoutCrc = 0xC5, - /// Transmit REQA - TransmitReqa = 0xC6, - /// Transmit WUPA - TransmitWupa = 0xC7, - /// NFC transmit with Initial RF Collision Avoidance - InitialRfCollision = 0xC8, - /// NFC transmit with Response RF Collision Avoidance - ResponseRfCollisionN = 0xC9, - /// Passive target logic to Sense/Idle state - GotoSense = 0xCD, - /// Passive target logic to Sleep/Halt state - GotoSleep = 0xCE, - /// Mask receive data - MaskReceiveData = 0xD0, - /// Unmask receive data - UnmaskReceiveData = 0xD1, - /// AM Modulation state change - AmModStateChange = 0xD2, - /// Measure singal amplitude on RFI inputs - MeasureAmplitude = 0xD3, - /// Reset RX Gain - ResetRxgain = 0xD5, - /// Adjust regulators - AdjustRegulators = 0xD6, - /// Starts the sequence to adjust the driver timing - CalibrateDriverTiming = 0xD8, - /// Measure phase between RFO and RFI signal - MeasurePhase = 0xD9, - /// Clear RSSI bits and restart the measurement - ClearRssi = 0xDA, - /// Clears FIFO, Collision and IRQ status - ClearFifo = 0xDB, - /// Transparent mode - TransparentMode = 0xDC, - /// Calibrate the capacitive sensor - CalibrateCSensor = 0xDD, - /// Measure capacitance - MeasureCapacitance = 0xDE, - /// Measure power supply voltage - MeasureVdd = 0xDF, - /// Start the general purpose timer - StartGpTimer = 0xE0, - /// Start the wake-up timer - StartWupTimer = 0xE1, - /// Start the mask-receive timer - StartMaskReceiveTimer = 0xE2, - /// Start the no-response timer - StartNoResponseTimer = 0xE3, - /// Start PPon2 timer - StartPpon2Timer = 0xE4, - /// Stop No Response Timer - StopNrt = 0xE8, - /// Enable R/W access to the test registers - SpaceBAccess = 0xFB, - /// Enable R/W access to the test registers - TestAccess = 0xFC, -} +#[cfg(feature = "st25r3911b")] +use lib_st25r3911b::Interrupt; #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[allow(unused)] +#[cfg(not(feature = "st25r3911b"))] enum Interrupt { /// RFU interrupt Rfu = 0, @@ -264,6 +216,7 @@ pub struct St25r39 { mode: Mode, } +#[cfg(not(feature = "st25r3911b"))] impl St25r39 { pub async fn new(iface: I, irq: IrqPin) -> Result> { let mut this = Self { @@ -701,6 +654,8 @@ impl<'a, I: Interface, IrqPin: InputPin + Wait> Raw<'a, I, IrqPin> { self.inner.mode_off()?; Ok(()) } + + #[cfg(not(feature = "st25r3911b"))] pub async fn driver_hi_z(&mut self) -> Result<(), Error> { self.inner.mode_off()?; self.inner.regs().tx_driver().write(|w| { diff --git a/rnfc-st25r39/src/lib_st25r3911b.rs b/rnfc-st25r39/src/lib_st25r3911b.rs new file mode 100644 index 0000000..18872b9 --- /dev/null +++ b/rnfc-st25r39/src/lib_st25r3911b.rs @@ -0,0 +1,538 @@ +#![allow(async_fn_in_trait)] +#![deny(unused_must_use)] + +use embassy_futures::yield_now; +use embassy_time::{with_timeout, Duration, Instant, Timer}; +use embedded_hal::digital::InputPin; +use embedded_hal_async::digital::Wait; + +pub use crate::commands::Command; +pub use crate::interface::Interface; +use crate::regs::Regs; +use crate::{regs, Error, FieldOnError, WakeupConfig, WakeupReference, DEFAULT_TIMEOUT}; + +// TODO: This is here temporarily, just to provide abstraction similar to st25r3916. +// Thus - bits do not match. +// This chip offers 3 different registers for IRQs. +// Possibly whole IRQ handling would need to be done differently. +pub enum Interrupt { + /// IRQ due to error and wake-up timer + Err = 0, + /// IRQ due to timer or NFC event + Tim = 1, + /// bit collision interrupt + Col = 2, + /// end of transmission interrupt + Txe = 3, + /// end of receive interrupt + Rxe = 4, + /// start of receive interrupt + Rxs = 5, + /// FIFO water level interrupt + Fwl = 6, + /// oscillator stable interrupt + Osc = 7, + /// initiator bit rate recognised interrupt + Nfct = 8, + /// minimum guard time expired interrupt + Cat = 9, + /// collision during RF collision avoidance interrupt + Cac = 10, + /// external field off interrupt + Eof = 11, + /// external field on interrupt + Eon = 12, + /// general purpose timer expired interrupt + Gpe = 13, + /// no-response timer expired interrupt + Nre = 14, + /// termination of direct command interrupt + Dct = 15, + /// wake-up due to capacitance measurement + Wcap = 16, + /// wake-up due to phase interrupt + Wph = 17, + /// wake-up due to amplitude interrupt + Wam = 18, + /// wake-up interrupt + Wt = 19, + /// hard framing error interrupt + Err1 = 20, + /// soft framing error interrupt + Err2 = 21, + /// parity error interrupt + Par = 22, + /// CRC error interrupt + Crc = 23, + /// RXE with an automatic response interrupt + RxePta = 28, + /// Anticollision done and Field On interrupt + Apon = 29, +} + +/// Device starts with default configuration. Initially the oscillator is not enabled. +/// It's possible to verify register contents; then call `configure` to enable RF. +impl super::St25r39 { + pub async fn new(iface: I, irq: IrqPin) -> Result> { + let mut this = Self { + iface, + irq, + irqs: 0, + mode: super::Mode::Off, + }; + this.init().await?; + //this.configure(); + // preferably called by user, + // after checking IC_rev, ect + // otherwise we might spin forever waiting for OSC + Ok(this) + } + + pub fn regs(&mut self) -> Regs { + Regs::::new(&mut self.iface) + } + + pub fn cmd(&mut self, cmd: Command) -> Result<(), Error> { + self.iface.do_command(cmd as u8).map_err(Error::Interface) + } + + async fn cmd_wait(&mut self, cmd: Command) -> Result<(), Error> { + self.irq_clear()?; + self.cmd(cmd)?; + match self.regs().irq_timer_nfc().read()?.dcd() { + true => Ok(()), + false => Err(Error::Timeout), + } + } + + async fn is_osc_stable(&mut self) -> Result<(), Error> { + let failed = Err(Error::Timeout); + match with_timeout( + DEFAULT_TIMEOUT / 10, // table 101, Tosc max 10ms, we'll wait 50ms + async { self.regs().aux_display().read() }, + ) + .await + { + Ok(val) => { + if val?.osc_ok() { + Ok(()) + } else { + failed + } + } + Err(_) => failed, + } + } + + pub async fn enable_osc(&mut self) -> Result<(), Error> { + trace!("Starting osc..."); + if self.is_osc_stable().await.is_err() { + self.regs().op_control().write(|w| w.set_en(true))?; + } + self.is_osc_stable().await + } + + async fn init(&mut self) -> Result<(), Error> { + self.cmd(Command::SetDefault)?; + self.cmd(Command::Clear)?; + + let id = self.regs().ic_identity().read()?; + trace!("ic_type = {:02x} ic_rev = {:02x}", id.ic_type().0, id.ic_rev().0); + + Ok(()) + } + + pub async fn mcu_clk_off(&mut self) -> Result<(), Error> { + // Disable MCU_CLK (default, on power-up is 3.39MHz) + self.regs().io_conf1().write(|w| { + w.set_out_cl(regs::IoConf1OutCl::DISABLED); + w.set_osc(true); // use 27.12Mhz Xtal + })?; + + match self.regs().io_conf1().read()?.out_cl() == regs::IoConf1OutCl::DISABLED { + true => Ok(()), + false => Err(Error::Timeout), + } + } + + pub async fn configure(&mut self) -> Result<(), Error> { + self.irq_clear()?; + // Enable OSC + self.enable_osc().await?; + self.irq_clear()?; // mask osc first + + // Measure vdd + trace!("measuring vdd..."); + let vdd_mv = self.measure_vdd().await?; + trace!("measure vdd result = {}mv", vdd_mv); + + let sup3v = vdd_mv < 3600; + if sup3v { + self.regs().io_conf2().write(|w| { + w.set_sup_3v(sup3v); + })?; + trace!("using 3v3 supply mode"); + } else { + trace!("using 5v supply mode"); + } + + // Disable MCU_CLK, default on power-up 3.39MHz + self.regs().io_conf1().write(|w| { + w.set_out_cl(regs::IoConf1OutCl::DISABLED); + w.set_osc(true); // use 27.12Mhz Xtal + })?; + + // Enable minimum non-overlap + //self.regs().res_am_mod().write(|w| w.set_fa3_f(true))?; + + // Set ext field detect activ/deactiv thresholds + //self.regs().field_threshold_actv().write(|w| { + // w.set_trg(regs::FieldThresholdActvTrg::_105MV); + // w.set_rfe(regs::FieldThresholdActvRfe::_105MV); + //})?; + //self.regs().field_threshold_deactv().write(|w| { + // w.set_trg(regs::FieldThresholdDeactvTrg::_75MV); + // w.set_rfe(regs::FieldThresholdDeactvRfe::_75MV); + //})?; + + //self.regs().aux_mod().write(|w| { + // w.set_lm_ext(false); // Disable external Load Modulation + // w.set_lm_dri(true); // Enable internal Load Modulation + //})?; + + //self.regs().emd_sup_conf().write(|w| { + // w.set_rx_start_emv(true); + //})?; + + // AAT not in use + //self.regs().ant_tune_a().write_value(0x82)?; + //self.regs().ant_tune_b().write_value(0x82)?; + + // Adjust regulators + + // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. + self.regs().regulator_volt_control().write(|w| w.set_reg_s(true))?; + self.regs().regulator_volt_control().write(|w| w.set_reg_s(false))?; + + self.cmd_wait(Command::AdjustRegulators).await?; + + let res = self.regs().regulator_and_tim_disp().read()?.0; + trace!("reg result = {}", res); + + Ok(()) + } + + pub async fn mode_on(&mut self) -> Result<(), Error> { + self.mode = super::Mode::On; + self.enable_osc().await?; + + Ok(()) + } + + pub fn mode_off(&mut self) -> Result<(), Error> { + self.mode = super::Mode::Off; + self.cmd(Command::Stop)?; + // disable everything + self.regs().op_control().write(|_| {})?; + Ok(()) + } + + pub async fn measure_amplitude(&mut self) -> Result> { + self.cmd_wait(Command::MeasureAmplitude).await?; + self.regs().ad_conv_result().read() + } + + pub async fn measure_phase(&mut self) -> Result> { + self.cmd_wait(Command::MeasurePhase).await?; + self.regs().ad_conv_result().read() + } + + pub async fn measure_capacitance(&mut self) -> Result> { + self.cmd_wait(Command::MeasureCapacitance).await?; + self.regs().ad_conv_result().read() + } + + pub async fn calibrate_capacitance(&mut self) -> Result> { + self.regs().cap_sensor_control().write(|w| { + // Clear Manual calibration values to enable automatic calibration mode + w.set_cs_mcal(0); + w.set_cs_g(0b01); // 6.5v/pF, highest one + })?; + + // Don't use `cmd_wait`, the irq only fires in Ready mode (op_control.en = 1). + // Instead, wait for cap_sensor_result.cs_cal_end + self.cmd(Command::CalibrateCSensor)?; + + let deadline = Instant::now() + DEFAULT_TIMEOUT; + + let res = loop { + if Instant::now() > deadline { + return Err(Error::Timeout); + } + + let res = self.regs().cap_sensor_disp().read()?; + if res.cs_cal_err() { + panic!("Capacitive sensor calibration failed!"); + } + if res.cs_cal_end() { + break res; + } + + yield_now().await; + }; + Ok(res.cs_cal_val()) + } + + /// Change into wakeup mode, return immediately. + /// The IRQ pin will go high on wakeup. + pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { + self.mode_on().await?; + + self.mode = super::Mode::Wakeup; + debug!("Entering wakeup mode"); + + self.cmd(Command::Stop)?; + self.regs().op_control().write(|_| {})?; + self.regs().mode().write(|w| w.set_om(regs::ModeOm::INI_ISO14443A))?; + + let mut wtc = regs::WupTimerControl(0); + // let mut irqs = 0; + + wtc.set_wur(config.period as u8 & 0x10 == 0); + wtc.set_wut(config.period as u8 & 0x0F); + + if let Some(m) = config.inductive_amplitude { + let mut conf = regs::AmplitudeMeasureConf(0); + conf.set_am_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().amplitude_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_amplitude().await?; + self.regs().amplitude_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_amplitude().await?; + self.regs().amplitude_measure_ref().write_value(val)?; + conf.set_am_ae(true); + conf.set_am_aam(include_irq_measurement); + conf.set_am_aew(weight); + } + } + self.regs().amplitude_measure_conf().write_value(conf)?; + wtc.set_wam(true); + //irqs |= 1 << Interrupt::Wam as u32; + } + if let Some(m) = config.inductive_phase { + let mut conf = regs::PhaseMeasureConf(0); + conf.set_pm_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().phase_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_phase().await?; + self.regs().phase_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_phase().await?; + self.regs().phase_measure_ref().write_value(val)?; + conf.set_pm_ae(true); + conf.set_pm_aam(include_irq_measurement); + conf.set_pm_aew(weight); + } + } + self.regs().phase_measure_conf().write_value(conf)?; + wtc.set_wph(true); + // irqs |= 1 << Interrupt::Wph as u32; + } + if let Some(m) = config.capacitive { + debug!("capacitance calibrating..."); + let val = self.calibrate_capacitance().await?; + info!("capacitance calibrated: {}", val); + + let mut conf = regs::CapacitanceMeasureConf(0); + conf.set_cm_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().capacitance_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_capacitance().await?; + info!("Measured: {}", val); + self.regs().capacitance_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_capacitance().await?; + info!("Measured: {}", val); + self.regs().capacitance_measure_ref().write_value(val)?; + conf.set_cm_ae(true); + conf.set_cm_aam(include_irq_measurement); + conf.set_cm_aew(weight); + } + } + self.regs().capacitance_measure_conf().write_value(conf)?; + // wtc.set_wcap(true); // wto? + // irqs |= 1 << Interrupt::Wcap as u32; + } + + self.regs().wup_timer_control().write_value(wtc)?; + self.regs().op_control().write(|w| w.set_wu(true))?; + // self.irq_set_mask(!irqs)?; + + debug!("Entered wakeup mode, waiting for pin IRQ"); + self.irq.wait_for_high().await.unwrap(); + debug!("got pin IRQ!"); + + Ok(()) + } + + pub async fn field_on(&mut self) -> Result<(), FieldOnError> { + self.regs().mode().write(|w| { + w.set_om(regs::ModeOm::INI_ISO14443A); + })?; + // note: set automatically if command AnalogPreset is used + self.regs().aux().write(|w| { + w.set_tr_am(false); // use OOK + })?; + + // self.regs().aux_mod().write(|w| { + // w.set_lm_dri(true); // Enable internal Load Modulation + // w.set_dis_reg_am(false); // Enable regulator-based AM + // w.set_res_am(false); + // })?; + + // // Default over/under shoot protiection + // self.regs().overshoot_conf1().write_value(0x40.into())?; + // self.regs().overshoot_conf2().write_value(0x03.into())?; + // self.regs().undershoot_conf1().write_value(0x40.into())?; + // self.regs().undershoot_conf2().write_value(0x03.into())?; + + self.regs().aux().write(|w| { + // w.set_dis_corr(false); // Enable correlator reception + w.set_nfc_n(0); // todo this changes + })?; + /* + self.regs().rx_conf1().write_value(0x08.into())?; + self.regs().rx_conf2().write_value(0x2D.into())?; + self.regs().rx_conf3().write_value(0x00.into())?; + self.regs().rx_conf4().write_value(0x00.into())?; + self.regs().corr_conf1().write_value(0x51.into())?; + self.regs().corr_conf2().write_value(0x00.into())?; + */ + + self.regs().bit_rate().write(|w| { + w.set_rxrate(regs::BitRateE::_106); + w.set_txrate(regs::BitRateE::_106); + })?; + + // defaults + self.regs().iso14443a_nfc().write(|_| {})?; + + // Field ON + + // GT is done by software + // self.regs().field_on_gt().write_value(0)?; + + self.irq_clear()?; // clear + self.cmd(Command::InitialRfCollision)?; + + // loop { + // if self.irq(Interrupt::Cac) { + // return Err(FieldOnError::FieldCollision); + // } + // if self.irq(Interrupt::Apon) { + // break; + // } + + // self.irq_update()?; + // } + + self.regs().op_control().modify(|w| { + w.set_tx_en(true); + w.set_rx_en(true); + })?; + + Ok(()) + } + + async fn measure_vdd(&mut self) -> Result> { + self.regs().regulator_volt_control().write(|w| w.set_mpsv(0))?; + self.cmd_wait(Command::MeasureVdd).await?; + let res = self.regs().ad_conv_result().read()? as u32; + + // result is in units of 23.4mV + Ok((res * 234 + 5) / 10) + } + + // ======================= + // irq stuff + + // This chip offers 3 different registers to check for different IRQs + // Either an abstraction between chips would need to be build, or + #[inline] + pub fn irq(&mut self, irq: Interrupt) -> bool { + let r = self.regs().irq_main().read().expect("be readable"); + match irq { + Interrupt::Err => r.err(), + Interrupt::Tim => r.tim(), + Interrupt::Col => r.col(), + Interrupt::Txe => r.txe(), + Interrupt::Rxe => r.rxe(), + _ => todo!(), // TODO: ect huge match which doesn't make much sense? + } + } + + pub async fn irq_wait_timeout(&self, mut fn_to_call: F, timeout: Duration) -> Result<(), Error> + where + F: FnMut() -> bool, + { + match with_timeout( + timeout, + async { + while !fn_to_call() { + Timer::after_millis(5).await + } + embassy_futures::yield_now() + } + .await, + ) + .await + { + Ok(_) => Ok(()), + Err(_) => Err(Error::Timeout), + } + } + + pub async fn irq_wait(&self, fn_to_call: F) -> Result<(), Error> + where + F: Fn() -> bool, + { + self.irq_wait_timeout(fn_to_call, DEFAULT_TIMEOUT).await + } + + pub fn irq_update(&mut self) -> Result<(), Error> { + self.regs().irq_main().read()?; + Ok(()) + } + + #[inline] + fn irq_clear(&mut self) -> Result<(), Error> { + self.regs().irq_main().write(|v| v.0 = 0)?; + Ok(()) + } + + // pub fn raw(&mut self) -> Raw<'_, I, IrqPin> { + // Raw { inner: self } + // } +} diff --git a/rnfc-st25r39/src/lib_st25r3916.rs b/rnfc-st25r39/src/lib_st25r3916.rs new file mode 100644 index 0000000..3f2d6a6 --- /dev/null +++ b/rnfc-st25r39/src/lib_st25r3916.rs @@ -0,0 +1,6 @@ +// TODO - placeholder if "approach 2" described in PR is preferred, +// then specific for st25r3916 parts from "lib" could be moved here +// which would allow to align the changes between chips better, +// and possibly remove substantial amount of "cfg!" checks +// See also discussion on Matrix +// https://matrix.to/#/!YoLPkieCYHGzdjUhOK:matrix.org/$jLJeWLyptxa4kbQcl-j2hKoha9DeI_Ta6m_X0t2wmhw diff --git a/rnfc-st25r39/src/regs_st25r3911b.rs b/rnfc-st25r39/src/regs_st25r3911b.rs new file mode 100644 index 0000000..6b676fa --- /dev/null +++ b/rnfc-st25r39/src/regs_st25r3911b.rs @@ -0,0 +1,2756 @@ +#![allow(unused)] + +use core::marker::PhantomData; + +use super::Interface; +use crate::Error; + +pub struct Reg<'a, I: Interface, T: Copy> { + addr: u8, + iface: &'a mut I, + phantom: PhantomData<&'a mut T>, +} + +impl<'a, I: Interface, T: Copy + Into + From> Reg<'a, I, T> { + pub fn new(iface: &'a mut I, addr: u8) -> Self { + Self { + iface, + addr, + phantom: PhantomData, + } + } + + pub fn read(&mut self) -> Result> { + Ok(self.iface.read_reg(self.addr).map_err(Error::Interface)?.into()) + } + + pub fn write_value(&mut self, val: T) -> Result<(), Error> { + self.iface.write_reg(self.addr, val.into()).map_err(Error::Interface) + } + + pub fn modify(&mut self, f: impl FnOnce(&mut T) -> R) -> Result> { + let mut val = self.read()?; + let res = f(&mut val); + self.write_value(val)?; + Ok(res) + } +} + +impl<'a, I: Interface, T: Default + Copy + Into + From> Reg<'a, I, T> { + pub fn write(&mut self, f: impl FnOnce(&mut T) -> R) -> Result> { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val)?; + Ok(res) + } +} +pub struct Regs<'a, I: Interface> { + iface: &'a mut I, +} + +impl<'a, I: Interface> Regs<'a, I> { + pub fn new(iface: &'a mut I) -> Self { + Self { iface } + } + + /// IO configuration register 1 + pub fn io_conf1(&mut self) -> Reg<'_, I, IoConf1> { + Reg::new(self.iface, 0) + } + /// IO configuration register 2 + pub fn io_conf2(&mut self) -> Reg<'_, I, IoConf2> { + Reg::new(self.iface, 1) + } + /// Operation control register + pub fn op_control(&mut self) -> Reg<'_, I, OpControl> { + Reg::new(self.iface, 2) + } + /// Mode definition register + pub fn mode(&mut self) -> Reg<'_, I, Mode> { + Reg::new(self.iface, 3) + } + /// Bit rate definition register + pub fn bit_rate(&mut self) -> Reg<'_, I, BitRate> { + Reg::new(self.iface, 4) + } + /// ISO14443A and NFC 106kb/s settings register + pub fn iso14443a_nfc(&mut self) -> Reg<'_, I, Iso14443ANfc> { + Reg::new(self.iface, 5) + } + /// ISO14443B settings register 1 + pub fn iso14443b_1(&mut self) -> Reg<'_, I, Iso14443B1> { + Reg::new(self.iface, 6) + } + /// ISO14443B and FeliCa settings register + pub fn iso14443b_2(&mut self) -> Reg<'_, I, Iso14443B2> { + Reg::new(self.iface, 7) + } + /// Stream mode definition register + pub fn stream_mode(&mut self) -> Reg<'_, I, StreamMode> { + Reg::new(self.iface, 8) + } + /// Auxiliary definition register + pub fn aux(&mut self) -> Reg<'_, I, Aux> { + Reg::new(self.iface, 9) + } + /// Receiver configuration register 1 + pub fn rx_conf1(&mut self) -> Reg<'_, I, RxConf1> { + Reg::new(self.iface, 10) + } + /// Receiver configuration register 2 + pub fn rx_conf2(&mut self) -> Reg<'_, I, RxConf2> { + Reg::new(self.iface, 11) + } + /// Receiver configuration register 3 + pub fn rx_conf3(&mut self) -> Reg<'_, I, RxConf3> { + Reg::new(self.iface, 12) + } + /// Receiver configuration register 4 + pub fn rx_conf4(&mut self) -> Reg<'_, I, RxConf4> { + Reg::new(self.iface, 13) + } + /// Mask receive timer register + pub fn mask_rx_timer(&mut self) -> Reg<'_, I, MaskRxTimer> { + Reg::new(self.iface, 14) + } + /// No-response timer register 1 + pub fn no_response_timer1(&mut self) -> Reg<'_, I, NoResponseTimer1> { + Reg::new(self.iface, 15) + } + /// No-response timer register 2 + pub fn no_response_timer2(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 16) + } + /// General purpose and no-response timer control register + pub fn gpt_nrt_ctrl(&mut self) -> Reg<'_, I, GptNrtCtrl> { + Reg::new(self.iface, 17) + } + /// General purpose timer register 1 + pub fn gpt1(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 18) + } + /// General purpose timer register 2 + pub fn gpt2(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 19) + } + /// Main interrupt register + pub fn irq_mask_main(&mut self) -> Reg<'_, I, IrqMaskMain> { + Reg::new(self.iface, 20) + } + /// Mask timer and NFC interrupt register + pub fn irq_mask_timer_nfc(&mut self) -> Reg<'_, I, IrqMaskTimerNfc> { + Reg::new(self.iface, 21) + } + /// Mask error and wake-up interrupt register + pub fn irq_mask_error_wup(&mut self) -> Reg<'_, I, IrqMaskErrorWup> { + Reg::new(self.iface, 22) + } + /// Main interrupt register + pub fn irq_main(&mut self) -> Reg<'_, I, IrqMain> { + Reg::new(self.iface, 23) + } + /// Mask timer and NFC interrupt register + pub fn irq_timer_nfc(&mut self) -> Reg<'_, I, IrqTimerNfc> { + Reg::new(self.iface, 24) + } + /// Error and wake-up interrupt register + pub fn irq_error_wup(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 25) + } + /// FIFO status register 1 + pub fn fifo_status1(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 26) + } + /// FIFO status register 2 + pub fn fifo_status2(&mut self) -> Reg<'_, I, FifoStatus2> { + Reg::new(self.iface, 27) + } + /// Collision display register + pub fn collision_status(&mut self) -> Reg<'_, I, CollisionStatus> { + Reg::new(self.iface, 28) + } + /// Number of transmitted bytes register 1 + pub fn num_tx_bytes1(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 29) + } + /// Number of transmitted bytes register 2 + pub fn num_tx_bytes2(&mut self) -> Reg<'_, I, NumTxBytes2> { + Reg::new(self.iface, 30) + } + /// NFCIP bit rate detection display register + pub fn nfcip1_bit_rate_disp(&mut self) -> Reg<'_, I, Nfcip1BitRateDisp> { + Reg::new(self.iface, 31) + } + /// A/D converter output register + pub fn ad_conv_result(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 32) + } + /// Antenna calibration control register + pub fn ant_tune_ctrl(&mut self) -> Reg<'_, I, AntTuneCtrl> { + Reg::new(self.iface, 33) + } + /// Antenna calibration target register + pub fn ant_tune_target(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 34) + } + /// Antenna calibration display register + pub fn ant_tune_disp(&mut self) -> Reg<'_, I, AntTuneDisp> { + Reg::new(self.iface, 35) + } + /// AM modulation depth control register + pub fn am_mod_depth_ctrl(&mut self) -> Reg<'_, I, AmModDepthCtrl> { + Reg::new(self.iface, 36) + } + /// AM modulation depth display register + pub fn am_mod_depth_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 37) + } + /// RFO AM modulated level definition register + pub fn rfo_am_mod_level_def(&mut self) -> Reg<'_, I, RfoAmLevelDef> { + Reg::new(self.iface, 38) + } + /// RFO normal level definition register + pub fn rfo_normal_level_def(&mut self) -> Reg<'_, I, RfoAmLevelDef> { + Reg::new(self.iface, 39) + } + /// External field detector threshold register + pub fn ext_field_det_thr(&mut self) -> Reg<'_, I, ExtFieldDetThr> { + Reg::new(self.iface, 41) + } + /// Regulator voltage control register + pub fn regulator_volt_control(&mut self) -> Reg<'_, I, RegulatorVoltControl> { + Reg::new(self.iface, 42) + } + /// Regulator and timer display register + pub fn regulator_and_tim_disp(&mut self) -> Reg<'_, I, RegulatorAndTimDisp> { + Reg::new(self.iface, 43) + } + /// RSSI display register + pub fn rssi_result(&mut self) -> Reg<'_, I, RssiResult> { + Reg::new(self.iface, 44) + } + /// Gain reduction state register + pub fn gain_redu_state(&mut self) -> Reg<'_, I, GainReduState> { + Reg::new(self.iface, 45) + } + /// Capacitive sensor control register + pub fn cap_sensor_control(&mut self) -> Reg<'_, I, CapSensorControl> { + Reg::new(self.iface, 46) + } + /// Capacitive sensor display register + pub fn cap_sensor_disp(&mut self) -> Reg<'_, I, CapSensorDisp> { + Reg::new(self.iface, 47) + } + /// Auxiliary display register + pub fn aux_display(&mut self) -> Reg<'_, I, AuxDisplay> { + Reg::new(self.iface, 48) + } + /// Wake-up timer control register + pub fn wup_timer_control(&mut self) -> Reg<'_, I, WupTimerControl> { + Reg::new(self.iface, 49) + } + /// Amplitude measurement configuration register + pub fn amplitude_measure_conf(&mut self) -> Reg<'_, I, AmplitudeMeasureConf> { + Reg::new(self.iface, 50) + } + /// Amplitude measurement reference register + pub fn amplitude_measure_ref(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 51) + } + /// Amplitude measurement auto-averaging display + pub fn amplitude_measure_auto_avg_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 52) + } + /// Amplitude measurement display + pub fn amplitude_measure_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 53) + } + /// Phase measurement configuration + pub fn phase_measure_conf(&mut self) -> Reg<'_, I, PhaseMeasureConf> { + Reg::new(self.iface, 54) + } + /// Phase measurement reference + pub fn phase_measure_ref(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 55) + } + /// Phase measurement auto-averaging display + pub fn phase_measure_auto_avg_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 56) + } + /// Phase measurement display + pub fn phase_measure_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 57) + } + /// Capacitance measurement configuration + pub fn capacitance_measure_conf(&mut self) -> Reg<'_, I, CapacitanceMeasureConf> { + Reg::new(self.iface, 58) + } + /// Capacitance measurement reference + pub fn capacitance_measure_ref(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 59) + } + /// Capacitance measurement auto-averaging display + pub fn capacitance_measure_auto_avg_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 60) + } + /// Capacitance measurement display + pub fn capacitance_measure_disp(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 61) + } + /// IC identity register + pub fn ic_identity(&mut self) -> Reg<'_, I, IcIdentity> { + Reg::new(self.iface, 63) + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IoConf1(pub u8); +impl IoConf1 { + pub const fn lf_clk_off(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_lf_clk_off(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn out_cl(&self) -> IoConf1OutCl { + let val = (self.0 >> 1_usize) & 2; + IoConf1OutCl(val as u8) + } + pub fn set_out_cl(&mut self, val: IoConf1OutCl) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val.0 as u8) & 2) << 1_usize; + } + pub const fn osc(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_osc(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn fifo_lt(&self) -> u8 { + let val = (self.0 >> 4_usize) & 2; + val as u8 + } + pub fn set_fifo_lt(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 4_usize)) | ((val as u8) & 2) << 4_usize; + } + pub const fn rfo2(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_rfo2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn single(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_single(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for IoConf1 { + fn default() -> IoConf1 { + IoConf1(8) + } +} +impl From for IoConf1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IoConf1) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IoConf2(pub u8); +impl IoConf2 { + pub const fn slow_up(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_slow_up(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn io_18(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_io_18(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn miso_pd1(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_miso_pd1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn miso_pd2(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_miso_pd2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn vspd_off(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_vspd_off(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn sup_3v(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_sup_3v(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for IoConf2 { + fn default() -> IoConf2 { + IoConf2(0) + } +} +impl From for IoConf2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IoConf2) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct OpControl(pub u8); +impl OpControl { + pub const fn wu(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_wu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn tx_en(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_tx_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn rx_man(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_rx_man(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn rx_chn(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_rx_chn(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn rx_en(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_rx_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn en(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for OpControl { + fn default() -> OpControl { + OpControl(0) + } +} +impl From for OpControl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: OpControl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mode(pub u8); +impl Mode { + pub const fn nfc_ar(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_nfc_ar(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn om(&self) -> ModeOm { + let val = (self.0 >> 3_usize) & 4; + ModeOm(val as u8) + } + pub fn set_om(&mut self, val: ModeOm) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val.0 as u8) & 4) << 3_usize; + } + pub const fn targ(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_targ(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for Mode { + fn default() -> Mode { + Mode(8) + } +} +impl From for Mode { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Mode) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct BitRate(pub u8); +impl BitRate { + pub const fn rxrate(&self) -> BitRateE { + let val = (self.0 >> 0_usize) & 4; + BitRateE(val as u8) + } + pub fn set_rxrate(&mut self, val: BitRateE) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; + } + pub const fn txrate(&self) -> BitRateE { + let val = (self.0 >> 4_usize) & 4; + BitRateE(val as u8) + } + pub fn set_txrate(&mut self, val: BitRateE) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val.0 as u8) & 4) << 4_usize; + } +} +impl Default for BitRate { + fn default() -> BitRate { + BitRate(0) + } +} +impl From for BitRate { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: BitRate) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Iso14443ANfc(pub u8); +impl Iso14443ANfc { + pub const fn antcl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_antcl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn p_len(&self) -> u8 { + let val = (self.0 >> 1_usize) & 4; + val as u8 + } + pub fn set_p_len(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 1_usize)) | ((val as u8) & 4) << 1_usize; + } + pub const fn nfc_f0(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_nfc_f0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn no_rx_par(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_no_rx_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn no_tx_par(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_no_tx_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for Iso14443ANfc { + fn default() -> Iso14443ANfc { + Iso14443ANfc(0) + } +} +impl From for Iso14443ANfc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443ANfc) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Iso14443B1(pub u8); +impl Iso14443B1 { + pub const fn rx_st_om(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_rx_st_om(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn half(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_half(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn eof(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn sof_1(&self) -> Iso14443B1Sof1 { + let val = (self.0 >> 3_usize) & 1; + Iso14443B1Sof1(val as u8) + } + pub fn set_sof_1(&mut self, val: Iso14443B1Sof1) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val.0 as u8) & 1) << 3_usize; + } + pub const fn sof_0(&self) -> Iso14443B1Sof0 { + let val = (self.0 >> 4_usize) & 1; + Iso14443B1Sof0(val as u8) + } + pub fn set_sof_0(&mut self, val: Iso14443B1Sof0) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val.0 as u8) & 1) << 4_usize; + } + pub const fn egt(&self) -> u8 { + let val = (self.0 >> 5_usize) & 3; + val as u8 + } + pub fn set_egt(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; + } +} +impl Default for Iso14443B1 { + fn default() -> Iso14443B1 { + Iso14443B1(0) + } +} +impl From for Iso14443B1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443B1) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Iso14443B2(pub u8); +impl Iso14443B2 { + pub const fn f_p(&self) -> Iso14443B2FP { + let val = (self.0 >> 0_usize) & 2; + Iso14443B2FP(val as u8) + } + pub fn set_f_p(&mut self, val: Iso14443B2FP) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; + } + pub const fn phc_th(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_phc_th(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn eof_12(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_eof_12(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn no_eof(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_no_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn no_sof(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_no_sof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn tr1(&self) -> Iso14443B2Tr1 { + let val = (self.0 >> 6_usize) & 2; + Iso14443B2Tr1(val as u8) + } + pub fn set_tr1(&mut self, val: Iso14443B2Tr1) { + self.0 = (self.0 & !(2 << 6_usize)) | ((val.0 as u8) & 2) << 6_usize; + } +} +impl Default for Iso14443B2 { + fn default() -> Iso14443B2 { + Iso14443B2(0) + } +} +impl From for Iso14443B2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443B2) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct StreamMode(pub u8); +impl StreamMode { + pub const fn stx(&self) -> StreamModeStx { + let val = (self.0 >> 0_usize) & 3; + StreamModeStx(val as u8) + } + pub fn set_stx(&mut self, val: StreamModeStx) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; + } + pub const fn scp(&self) -> StreamModeScp { + let val = (self.0 >> 3_usize) & 2; + StreamModeScp(val as u8) + } + pub fn set_scp(&mut self, val: StreamModeScp) { + self.0 = (self.0 & !(2 << 3_usize)) | ((val.0 as u8) & 2) << 3_usize; + } + pub const fn scf(&self) -> StreamModeScf { + let val = (self.0 >> 5_usize) & 2; + StreamModeScf(val as u8) + } + pub fn set_scf(&mut self, val: StreamModeScf) { + self.0 = (self.0 & !(2 << 5_usize)) | ((val.0 as u8) & 2) << 5_usize; + } +} +impl Default for StreamMode { + fn default() -> StreamMode { + StreamMode(0) + } +} +impl From for StreamMode { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: StreamMode) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Aux(pub u8); +impl Aux { + pub const fn nfc_n(&self) -> u8 { + let val = (self.0 >> 0_usize) & 2; + val as u8 + } + pub fn set_nfc_n(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val as u8) & 2) << 0_usize; + } + pub const fn rx_tol(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_rx_tol(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn ook_hr(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_ook_hr(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn en_fd(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_en_fd(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn tr_am(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_tr_am(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn crc_2_fifo(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_crc_2_fifo(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn no_crc_rx(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_no_crc_rx(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for Aux { + fn default() -> Aux { + Aux(0) + } +} +impl From for Aux { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Aux) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxConf1(pub u8); +impl RxConf1 { + pub const fn z12k(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_z12k(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn h80(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_h80(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn h200(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_h200(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn lp(&self) -> RxConf1Lp { + let val = (self.0 >> 3_usize) & 3; + RxConf1Lp(val as u8) + } + pub fn set_lp(&mut self, val: RxConf1Lp) { + self.0 = (self.0 & !(3 << 3_usize)) | ((val.0 as u8) & 3) << 3_usize; + } + pub const fn amd_sel(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_amd_sel(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn ch_sel(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_ch_sel(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for RxConf1 { + fn default() -> RxConf1 { + RxConf1(0) + } +} +impl From for RxConf1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf1) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxConf2(pub u8); +impl RxConf2 { + pub const fn pmix_cl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_pmix_cl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn sqm_dyn(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_sqm_dyn(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn agc_alg(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_agc_alg(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn agc_m(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_agc_m(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn agc_en(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_agc_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn lf_en(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_lf_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn lf_op(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_lf_op(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn rx_lp(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_rx_lp(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for RxConf2 { + fn default() -> RxConf2 { + RxConf2(0) + } +} +impl From for RxConf2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf2) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxConf3(pub u8); +impl RxConf3 { + pub const fn rg_nfc(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_rg_nfc(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn lim(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_lim(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn rg1_pm(&self) -> u8 { + let val = (self.0 >> 2_usize) & 3; + val as u8 + } + pub fn set_rg1_pm(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 2_usize)) | ((val as u8) & 3) << 2_usize; + } + pub const fn rg1_am(&self) -> u8 { + let val = (self.0 >> 5_usize) & 3; + val as u8 + } + pub fn set_rg1_am(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; + } +} +impl Default for RxConf3 { + fn default() -> RxConf3 { + RxConf3(0) + } +} +impl From for RxConf3 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf3) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxConf4(pub u8); +impl RxConf4 { + pub const fn rg2_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 + } + pub fn set_rg2_pm(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; + } + pub const fn rg2_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_rg2_am(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + } +} +impl Default for RxConf4 { + fn default() -> RxConf4 { + RxConf4(0) + } +} +impl From for RxConf4 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf4) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct MaskRxTimer(pub u8); +impl MaskRxTimer { + pub const fn mrt0(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_mrt0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn mrt1(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_mrt1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn mrt2(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_mrt2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn mrt3(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_mrt3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn mrt4(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_mrt4(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn mrt5(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_mrt5(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn mrt6(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_mrt6(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn mrt7(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_mrt7(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for MaskRxTimer { + fn default() -> MaskRxTimer { + MaskRxTimer(0) + } +} +impl From for MaskRxTimer { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: MaskRxTimer) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct NoResponseTimer1(pub u8); +impl NoResponseTimer1 { + pub const fn nrt8(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_nrt8(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn nrt9(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_nrt9(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn nrt10(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_nrt10(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn nrt11(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_nrt11(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn nrt12(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_nrt12(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn nrt13(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_nrt13(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn nrt14(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_nrt14(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn nrt15(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_nrt15(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for NoResponseTimer1 { + fn default() -> NoResponseTimer1 { + NoResponseTimer1(0) + } +} +impl From for NoResponseTimer1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: NoResponseTimer1) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GptNrtCtrl(pub u8); +impl GptNrtCtrl { + pub const fn nrt_step(&self) -> TimerEmvControlNrtStep { + let val = (self.0 >> 0_usize) & 1; + TimerEmvControlNrtStep(val as u8) + } + pub fn set_nrt_step(&mut self, val: TimerEmvControlNrtStep) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val.0 as u8) & 1) << 0_usize; + } + pub const fn nrt_emv(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_nrt_emv(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn gptc(&self) -> TimerEmvControlGptc { + let val = (self.0 >> 5_usize) & 3; + TimerEmvControlGptc(val as u8) + } + pub fn set_gptc(&mut self, val: TimerEmvControlGptc) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val.0 as u8) & 3) << 5_usize; + } +} +impl Default for GptNrtCtrl { + fn default() -> GptNrtCtrl { + GptNrtCtrl(0) + } +} +impl From for GptNrtCtrl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: GptNrtCtrl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IrqMaskMain(pub u8); +impl IrqMaskMain { + pub const fn m_col(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_m_col(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn m_txe(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_m_txe(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn m_rxe(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_m_rxe(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn m_rxs(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_m_rxs(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn m_wl(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_m_wl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn m_osc(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_m_osc(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for IrqMaskMain { + fn default() -> IrqMaskMain { + IrqMaskMain(0) + } +} +impl From for IrqMaskMain { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IrqMaskMain) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IrqMaskTimerNfc(pub u8); +impl IrqMaskTimerNfc { + pub const fn m_nfct(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_m_nfct(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn m_cat(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_m_cat(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn m_cac(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_m_cac(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn m_eof(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_m_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn m_eon(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_m_eon(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn m_gpe(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_m_gpe(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn m_nre(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_m_nre(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn m_dcd(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_m_dcd(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for IrqMaskTimerNfc { + fn default() -> IrqMaskTimerNfc { + IrqMaskTimerNfc(0) + } +} +impl From for IrqMaskTimerNfc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IrqMaskTimerNfc) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IrqMaskErrorWup(pub u8); +impl IrqMaskErrorWup { + pub const fn m_ncap(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_m_ncap(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn m_wph(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_m_wph(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn m_wam(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_m_wam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn m_wt(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_m_wt(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn m_err1(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_m_err1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn m_err2(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_m_err2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn m_par(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_m_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn m_crc(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_m_crc(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for IrqMaskErrorWup { + fn default() -> IrqMaskErrorWup { + IrqMaskErrorWup(0) + } +} +impl From for IrqMaskErrorWup { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IrqMaskErrorWup) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IrqMain(pub u8); +impl IrqMain { + pub const fn err(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn tim(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub const fn col(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub const fn txe(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub const fn rxe(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub const fn rxs(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub const fn wl(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub const fn osc(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } +} +impl Default for IrqMain { + fn default() -> IrqMain { + IrqMain(0) + } +} +impl From for IrqMain { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IrqMain) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IrqTimerNfc(pub u8); +impl IrqTimerNfc { + pub const fn nfct(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn cat(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub const fn cac(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub const fn eof(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub const fn eon(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub const fn gpe(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub const fn nre(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub const fn dcd(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } +} +impl Default for IrqTimerNfc { + fn default() -> IrqTimerNfc { + IrqTimerNfc(0) + } +} +impl From for IrqTimerNfc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IrqTimerNfc) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct FifoStatus2(pub u8); +impl FifoStatus2 { + pub const fn np_lb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn fifo_lb(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 + } + pub const fn fifo_ovr(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub const fn fifo_unf(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } +} +impl Default for FifoStatus2 { + fn default() -> FifoStatus2 { + FifoStatus2(0) + } +} +impl From for FifoStatus2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: FifoStatus2) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CollisionStatus(pub u8); +impl CollisionStatus { + pub const fn c_pb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn c_bit(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 + } + pub const fn c_byte(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for CollisionStatus { + fn default() -> CollisionStatus { + CollisionStatus(0) + } +} +impl From for CollisionStatus { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: CollisionStatus) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct NumTxBytes2(pub u8); +impl NumTxBytes2 { + pub const fn nbtx(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; + val as u8 + } + pub fn set_nbtx(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; + } + pub const fn ntx(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; + val as u8 + } + pub fn set_ntx(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; + } +} +impl Default for NumTxBytes2 { + fn default() -> NumTxBytes2 { + NumTxBytes2(0) + } +} +impl From for NumTxBytes2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: NumTxBytes2) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Nfcip1BitRateDisp(pub u8); +impl Nfcip1BitRateDisp { + pub const fn nfc_rate(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for Nfcip1BitRateDisp { + fn default() -> Nfcip1BitRateDisp { + Nfcip1BitRateDisp(0) + } +} +impl From for Nfcip1BitRateDisp { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Nfcip1BitRateDisp) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AntTuneCtrl(pub u8); +impl AntTuneCtrl { + pub const fn tre(&self) -> u8 { + let val = (self.0 >> 3_usize) & 4; + val as u8 + } + pub fn set_tre(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; + } + pub const fn trim_s(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_trim_s(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for AntTuneCtrl { + fn default() -> AntTuneCtrl { + AntTuneCtrl(0) + } +} +impl From for AntTuneCtrl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: AntTuneCtrl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AntTuneDisp(pub u8); +impl AntTuneDisp { + pub const fn tri_err(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub const fn tri(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for AntTuneDisp { + fn default() -> AntTuneDisp { + AntTuneDisp(0) + } +} +impl From for AntTuneDisp { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: AntTuneDisp) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AmModDepthCtrl(pub u8); +impl AmModDepthCtrl { + pub const fn modd(&self) -> u8 { + let val = (self.0 >> 1_usize) & 6; + val as u8 + } + pub fn set_modd(&mut self, val: u8) { + self.0 = (self.0 & !(6 << 1_usize)) | ((val as u8) & 6) << 1_usize; + } + pub const fn am_s(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_am_s(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for AmModDepthCtrl { + fn default() -> AmModDepthCtrl { + AmModDepthCtrl(0) + } +} +impl From for AmModDepthCtrl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: AmModDepthCtrl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RfoAmLevelDef(pub u8); +impl RfoAmLevelDef { + pub const fn d0(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_d0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn d1(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_d1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn d2(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_d2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn d3(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_d3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn d4(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_d4(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn d5(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_d5(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn d6(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_d6(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn d7(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_d7(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for RfoAmLevelDef { + fn default() -> RfoAmLevelDef { + RfoAmLevelDef(0) + } +} +impl From for RfoAmLevelDef { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RfoAmLevelDef) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct ExtFieldDetThr(pub u8); +impl ExtFieldDetThr { + pub const fn rfe_t(&self) -> ThresholdDef { + let val = (self.0 >> 0_usize) & 4; + ThresholdDef(val as u8) + } + pub fn set_rfe_t(&mut self, val: ThresholdDef) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; + } + pub const fn trg_l(&self) -> ThresholdDef { + let val = (self.0 >> 4_usize) & 3; + ThresholdDef(val as u8) + } + pub fn set_trg_l(&mut self, val: ThresholdDef) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val.0 as u8) & 3) << 4_usize; + } +} +impl Default for ExtFieldDetThr { + fn default() -> ExtFieldDetThr { + ExtFieldDetThr(51) + } +} +impl From for ExtFieldDetThr { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: ExtFieldDetThr) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RegulatorVoltControl(pub u8); +impl RegulatorVoltControl { + pub const fn mpsv(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; + val as u8 + } + pub fn set_mpsv(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + } + pub const fn rege(&self) -> u8 { + let val = (self.0 >> 3_usize) & 4; + val as u8 + } + pub fn set_rege(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; + } + pub const fn reg_s(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_reg_s(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for RegulatorVoltControl { + fn default() -> RegulatorVoltControl { + RegulatorVoltControl(0) + } +} +impl From for RegulatorVoltControl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RegulatorVoltControl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RegulatorAndTimDisp(pub u8); +impl RegulatorAndTimDisp { + pub const fn mrt_on(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn nrt_on(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub const fn gpt_on(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub const fn reg(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for RegulatorAndTimDisp { + fn default() -> RegulatorAndTimDisp { + RegulatorAndTimDisp(0) + } +} +impl From for RegulatorAndTimDisp { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RegulatorAndTimDisp) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RssiResult(pub u8); +impl RssiResult { + pub const fn rssi_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 + } + pub const fn rssi_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for RssiResult { + fn default() -> RssiResult { + RssiResult(0) + } +} +impl From for RssiResult { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RssiResult) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GainReduState(pub u8); +impl GainReduState { + pub const fn gs_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 + } + pub const fn gs_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for GainReduState { + fn default() -> GainReduState { + GainReduState(0) + } +} +impl From for GainReduState { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: GainReduState) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CapSensorControl(pub u8); +impl CapSensorControl { + pub const fn cs_g(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; + val as u8 + } + pub fn set_cs_g(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; + } + pub const fn cs_mcal(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; + val as u8 + } + pub fn set_cs_mcal(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; + } +} +impl Default for CapSensorControl { + fn default() -> CapSensorControl { + CapSensorControl(0) + } +} +impl From for CapSensorControl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: CapSensorControl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CapSensorDisp(pub u8); +impl CapSensorDisp { + pub const fn cs_cal_err(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub const fn cs_cal_end(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub const fn cs_cal_val(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; + val as u8 + } +} +impl Default for CapSensorDisp { + fn default() -> CapSensorDisp { + CapSensorDisp(0) + } +} +impl From for CapSensorDisp { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: CapSensorDisp) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AuxDisplay(pub u8); +impl AuxDisplay { + pub const fn en_ac(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn nfc_t(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub const fn rx_act(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub const fn rx_on(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub const fn osc_ok(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub const fn tx_on(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub const fn efd_o(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub const fn a_cha(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } +} +impl Default for AuxDisplay { + fn default() -> AuxDisplay { + AuxDisplay(0) + } +} +impl From for AuxDisplay { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: AuxDisplay) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct WupTimerControl(pub u8); +impl WupTimerControl { + pub const fn wph(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_wph(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn wam(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_wam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn wto(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_wto(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn wut(&self) -> u8 { + let val = (self.0 >> 4_usize) & 3; + val as u8 + } + pub fn set_wut(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val as u8) & 3) << 4_usize; + } + pub const fn wur(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_wur(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for WupTimerControl { + fn default() -> WupTimerControl { + WupTimerControl(0) + } +} +impl From for WupTimerControl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: WupTimerControl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AmplitudeMeasureConf(pub u8); +impl AmplitudeMeasureConf { + pub const fn am_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_am_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn am_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; + val as u8 + } + pub fn set_am_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + } + pub const fn am_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_am_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn am_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_am_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + } +} +impl Default for AmplitudeMeasureConf { + fn default() -> AmplitudeMeasureConf { + AmplitudeMeasureConf(0) + } +} +impl From for AmplitudeMeasureConf { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: AmplitudeMeasureConf) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct PhaseMeasureConf(pub u8); +impl PhaseMeasureConf { + pub const fn pm_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_pm_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn pm_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; + val as u8 + } + pub fn set_pm_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + } + pub const fn pm_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_pm_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn pm_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_pm_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + } +} +impl Default for PhaseMeasureConf { + fn default() -> PhaseMeasureConf { + PhaseMeasureConf(0) + } +} +impl From for PhaseMeasureConf { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: PhaseMeasureConf) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CapacitanceMeasureConf(pub u8); +impl CapacitanceMeasureConf { + pub const fn cm_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_cm_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn cm_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; + val as u8 + } + pub fn set_cm_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + } + pub const fn cm_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_cm_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn cm_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_cm_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + } +} +impl Default for CapacitanceMeasureConf { + fn default() -> CapacitanceMeasureConf { + CapacitanceMeasureConf(0) + } +} +impl From for CapacitanceMeasureConf { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: CapacitanceMeasureConf) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IcIdentity(pub u8); +impl IcIdentity { + pub const fn ic_rev(&self) -> IcIdentityIcRev { + let val = (self.0 >> 0_usize) & 3; + IcIdentityIcRev(val as u8) + } + pub const fn ic_type(&self) -> IcIdentityIcType { + let val = (self.0 >> 3_usize) & 5; + IcIdentityIcType(val as u8) + } +} +impl Default for IcIdentity { + fn default() -> IcIdentity { + IcIdentity(0) + } +} +impl From for IcIdentity { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IcIdentity) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct BitRateE(pub u8); +impl BitRateE { + pub const _106: Self = Self(0x00); + pub const _212: Self = Self(0x01); + pub const _424: Self = Self(0x02); + pub const _848: Self = Self(0x03); + pub const _1695: Self = Self(0x04); + pub const _3390: Self = Self(0x05); + pub const _6780: Self = Self(0x06); +} +impl From for BitRateE { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: BitRateE) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct ThresholdDef(pub u8); +impl ThresholdDef { + pub const _75MV: Self = Self(0x00); + pub const _105MV: Self = Self(0x01); + pub const _150MV: Self = Self(0x02); + pub const _205MV: Self = Self(0x03); + pub const _290MV: Self = Self(0x04); + pub const _400MV: Self = Self(0x05); + pub const _560MV: Self = Self(0x06); + pub const _800MV: Self = Self(0x07); + pub const _25MV: Self = Self(0x08); + pub const _33MV: Self = Self(0x09); + pub const _47MV: Self = Self(0x0a); + pub const _64MV: Self = Self(0x0b); + pub const _90MV: Self = Self(0x0c); + pub const _125MV: Self = Self(0x0d); + pub const _175MV: Self = Self(0x0e); + pub const _250MV: Self = Self(0x0f); +} +impl From for ThresholdDef { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: ThresholdDef) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct WakeupTimesDef(pub u8); +impl WakeupTimesDef { + pub const _10: Self = Self(0x00); + pub const _20: Self = Self(0x01); + pub const _30: Self = Self(0x02); + pub const _40: Self = Self(0x03); + pub const _50: Self = Self(0x04); + pub const _60: Self = Self(0x05); + pub const _70: Self = Self(0x06); + pub const _80: Self = Self(0x07); +} +impl From for WakeupTimesDef { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: WakeupTimesDef) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct IcIdentityIcRev(pub u8); +impl IcIdentityIcRev { + pub const V0: Self = Self(0x00); + pub const V3_1: Self = Self(0x02); + pub const V3_3: Self = Self(0x03); + pub const V4_0: Self = Self(0x04); + pub const V4_1: Self = Self(0x05); +} +impl From for IcIdentityIcRev { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IcIdentityIcRev) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct IcIdentityIcType(pub u8); +impl IcIdentityIcType { + pub const ST25R3916: Self = Self(0x05); +} +impl From for IcIdentityIcType { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IcIdentityIcType) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct IoConf1OutCl(pub u8); +impl IoConf1OutCl { + pub const _3_39_MHZ: Self = Self(0x00); + pub const _6_78_MHZ: Self = Self(0x01); + pub const _13_86_MHZ: Self = Self(0x02); + pub const DISABLED: Self = Self(0x03); +} +impl From for IoConf1OutCl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IoConf1OutCl) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B1Sof1(pub u8); +impl Iso14443B1Sof1 { + pub const _2ETU: Self = Self(0x00); + pub const _3ETU: Self = Self(0x01); +} +impl From for Iso14443B1Sof1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443B1Sof1) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B1Sof0(pub u8); +impl Iso14443B1Sof0 { + pub const _10ETU: Self = Self(0x00); + pub const _11ETU: Self = Self(0x01); +} +impl From for Iso14443B1Sof0 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443B1Sof0) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B2FP(pub u8); +impl Iso14443B2FP { + pub const _48: Self = Self(0x00); + pub const _64: Self = Self(0x01); + pub const _80: Self = Self(0x02); + pub const _96: Self = Self(0x03); +} +impl From for Iso14443B2FP { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443B2FP) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B2Tr1(pub u8); +impl Iso14443B2Tr1 { + pub const _80FS80FS: Self = Self(0x00); + pub const _64FS32FS: Self = Self(0x01); +} +impl From for Iso14443B2Tr1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443B2Tr1) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct ModeOm(pub u8); +impl ModeOm { + pub const TARG_NFCIP1_ACTIVE_COMM_BR_DET: Self = Self(0x00); + pub const TARG_NFCIP1_ACTIVE_COMM_NORMAL: Self = Self(0x00); + pub const INI_ISO14443A: Self = Self(0x01); + pub const TARG_NFCA: Self = Self(0x01); + pub const INI_ISO14443B: Self = Self(0x02); + pub const TARG_NFCB: Self = Self(0x02); + pub const INI_FELICA: Self = Self(0x03); + pub const INI_TOPAZ: Self = Self(0x04); + pub const TARG_NFCF: Self = Self(0x04); + pub const INI_SUBCARRIER_STREAM: Self = Self(0x0e); + pub const INI_BPSK_STREAM: Self = Self(0x0f); +} +impl From for ModeOm { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: ModeOm) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct RxConf1Lp(pub u8); +impl RxConf1Lp { + pub const _1200KHZ: Self = Self(0x00); + pub const _600KHZ: Self = Self(0x01); + pub const _300KHZ: Self = Self(0x02); + pub const _2000KHZ: Self = Self(0x04); + pub const _7000KHZ: Self = Self(0x05); +} +impl From for RxConf1Lp { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf1Lp) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct StreamModeScf(pub u8); +impl StreamModeScf { + pub const BPSK848: Self = Self(0x00); + pub const SC212: Self = Self(0x00); + pub const BPSK1695: Self = Self(0x01); + pub const SC424: Self = Self(0x01); + pub const BPSK3390: Self = Self(0x02); + pub const SC848: Self = Self(0x02); + pub const BPSK106: Self = Self(0x03); + pub const SC1695: Self = Self(0x03); +} +impl From for StreamModeScf { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: StreamModeScf) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct StreamModeScp(pub u8); +impl StreamModeScp { + pub const _1PULSE: Self = Self(0x00); + pub const _2PULSES: Self = Self(0x01); + pub const _4PULSES: Self = Self(0x02); + pub const _8PULSES: Self = Self(0x03); +} +impl From for StreamModeScp { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: StreamModeScp) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct StreamModeStx(pub u8); +impl StreamModeStx { + pub const _106: Self = Self(0x00); + pub const _212: Self = Self(0x01); + pub const _424: Self = Self(0x02); + pub const _848: Self = Self(0x03); +} +impl From for StreamModeStx { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: StreamModeStx) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct TimerEmvControlGptc(pub u8); +impl TimerEmvControlGptc { + pub const NO_TRIGGER: Self = Self(0x00); + pub const ERX: Self = Self(0x01); + pub const SRX: Self = Self(0x02); + pub const ETX_NFC: Self = Self(0x03); +} +impl From for TimerEmvControlGptc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: TimerEmvControlGptc) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct TimerEmvControlNrtStep(pub u8); +impl TimerEmvControlNrtStep { + pub const _64_FC: Self = Self(0x00); + pub const _4096_FC: Self = Self(0x01); +} +impl From for TimerEmvControlNrtStep { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: TimerEmvControlNrtStep) -> u8 { + val.0 + } +} diff --git a/rnfc-st25r39/src/regs.rs b/rnfc-st25r39/src/regs_st25r3916.rs similarity index 100% rename from rnfc-st25r39/src/regs.rs rename to rnfc-st25r39/src/regs_st25r3916.rs diff --git a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml new file mode 100644 index 0000000..142b595 --- /dev/null +++ b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml @@ -0,0 +1,1349 @@ +--- +block/REGS: + items: + - name: IO_CONF1 + byte_offset: 0 + bit_size: 8 + access: RW + description: IO configuration register 1 + fieldset: IO_CONF1 + - name: IO_CONF2 + byte_offset: 1 + bit_size: 8 + access: RW + description: IO configuration register 2 + fieldset: IO_CONF2 + - name: OP_CONTROL + byte_offset: 2 + bit_size: 8 + access: RW + description: Operation control register + fieldset: OP_CONTROL + - name: MODE + byte_offset: 3 + bit_size: 8 + access: RW + description: Mode definition register + fieldset: MODE + - name: BIT_RATE + byte_offset: 4 + bit_size: 8 + access: RW + description: Bit rate definition register + fieldset: BIT_RATE + - name: ISO14443A_NFC + byte_offset: 5 + bit_size: 8 + access: RW + description: ISO14443A and NFC 106kb/s settings register + fieldset: ISO14443A_NFC + - name: ISO14443B_1 + byte_offset: 6 + bit_size: 8 + access: RW + description: ISO14443B settings register 1 + fieldset: ISO14443B_1 + - name: ISO14443B_2 + byte_offset: 7 + bit_size: 8 + access: RW + description: ISO14443B and FeliCa settings register + fieldset: ISO14443B_2 + - name: STREAM_MODE + byte_offset: 8 + bit_size: 8 + access: RW + description: Stream mode definition register + fieldset: STREAM_MODE + - name: AUX + byte_offset: 9 + bit_size: 8 + access: RW + description: Auxiliary definition register + fieldset: AUX + - name: RX_CONF1 + byte_offset: 10 + bit_size: 8 + access: RW + description: Receiver configuration register 1 + fieldset: RX_CONF1 + - name: RX_CONF2 + byte_offset: 11 + bit_size: 8 + access: RW + description: Receiver configuration register 2 + fieldset: RX_CONF2 + - name: RX_CONF3 + byte_offset: 12 + bit_size: 8 + access: RW + description: Receiver configuration register 3 + fieldset: RX_CONF3 + - name: RX_CONF4 + byte_offset: 13 + bit_size: 8 + access: RW + description: Receiver configuration register 4 + fieldset: RX_CONF4 + - name: MASK_RX_TIMER + byte_offset: 14 + bit_size: 8 + access: RW + description: Mask receive timer register + fieldset: MASK_RX_TIMER + - name: NO_RESPONSE_TIMER1 + byte_offset: 15 + bit_size: 8 + access: RW + description: No-response timer register 1 + fieldset: NO_RESPONSE_TIMER1 + - name: NO_RESPONSE_TIMER2 + byte_offset: 16 + bit_size: 8 + access: RW + description: No-response timer register 2 + - name: GPT_NRT_CTRL + byte_offset: 17 + bit_size: 8 + access: RW + description: General purpose and no-response timer control register + fieldset: GPT_NRT_CTRL + - name: GPT1 + byte_offset: 18 + bit_size: 8 + access: RW + description: General purpose timer register 1 + - name: GPT2 + byte_offset: 19 + bit_size: 8 + access: RW + description: General purpose timer register 2 + - name: IRQ_MASK_MAIN + byte_offset: 20 + bit_size: 8 + access: RW + description: Main interrupt register + fieldset: IRQ_MASK_MAIN + - name: IRQ_MASK_TIMER_NFC + byte_offset: 21 + bit_size: 8 + access: RW + description: Mask timer and NFC interrupt register + fieldset: IRQ_MASK_TIMER_NFC + - name: IRQ_MASK_ERROR_WUP + byte_offset: 22 + bit_size: 8 + access: RW + description: Mask error and wake-up interrupt register + fieldset: IRQ_MASK_ERROR_WUP + - name: IRQ_MAIN + byte_offset: 23 + bit_size: 8 + access: R + description: Main interrupt register + fieldset: IRQ_MAIN + - name: IRQ_TIMER_NFC + byte_offset: 24 + bit_size: 8 + access: R + description: Mask timer and NFC interrupt register + fieldset: IRQ_TIMER_NFC + - name: IRQ_ERROR_WUP + byte_offset: 25 + bit_size: 8 + access: R + description: Error and wake-up interrupt register + - name: FIFO_STATUS1 + byte_offset: 26 + bit_size: 8 + access: R + description: FIFO status register 1 + - name: FIFO_STATUS2 + byte_offset: 27 + bit_size: 8 + access: R + description: FIFO status register 2 + fieldset: FIFO_STATUS2 + - name: COLLISION_STATUS + byte_offset: 28 + bit_size: 8 + access: R + description: Collision display register + fieldset: COLLISION_STATUS + - name: NUM_TX_BYTES1 + byte_offset: 29 + bit_size: 8 + access: RW + description: Number of transmitted bytes register 1 + - name: NUM_TX_BYTES2 + byte_offset: 30 + bit_size: 8 + access: RW + description: Number of transmitted bytes register 2 + fieldset: NUM_TX_BYTES2 + - name: NFCIP1_BIT_RATE_DISP + byte_offset: 31 + bit_size: 8 + access: R + description: NFCIP bit rate detection display register + fieldset: NFCIP1_BIT_RATE_DISP + - name: AD_CONV_RESULT + byte_offset: 32 + bit_size: 8 + access: R + description: A/D converter output register + - name: ANT_TUNE_CTRL + byte_offset: 33 + bit_size: 8 + access: RW + description: Antenna calibration control register + fieldset: ANT_TUNE_CTRL + - name: ANT_TUNE_TARGET + byte_offset: 34 + bit_size: 8 + access: RW + description: Antenna calibration target register + - name: ANT_TUNE_DISP + byte_offset: 35 + bit_size: 8 + access: R + description: Antenna calibration display register + fieldset: ANT_TUNE_DISP + - name: AM_MOD_DEPTH_CTRL + byte_offset: 36 + bit_size: 8 + access: RW + description: AM modulation depth control register + fieldset: AM_MOD_DEPTH_CTRL + - name: AM_MOD_DEPTH_DISP + byte_offset: 37 + bit_size: 8 + access: R + description: AM modulation depth display register + - name: RFO_AM_MOD_LEVEL_DEF + byte_offset: 38 + bit_size: 8 + access: RW + description: RFO AM modulated level definition register + fieldset: RFO_AM_LEVEL_DEF + - name: RFO_NORMAL_LEVEL_DEF + byte_offset: 39 + bit_size: 8 + access: RW + description: RFO normal level definition register + fieldset: RFO_AM_LEVEL_DEF + - name: EXT_FIELD_DET_THR + byte_offset: 41 + bit_size: 8 + access: RW + description: External field detector threshold register + fieldset: EXT_FIELD_DET_THR + - name: REGULATOR_VOLT_CONTROL + byte_offset: 42 + bit_size: 8 + access: RW + description: Regulator voltage control register + fieldset: REGULATOR_VOLT_CONTROL + - name: REGULATOR_AND_TIM_DISP + byte_offset: 43 + bit_size: 8 + access: R + description: Regulator and timer display register + fieldset: REGULATOR_AND_TIM_DISP + - name: RSSI_RESULT + byte_offset: 44 + bit_size: 8 + access: R + description: RSSI display register + fieldset: RSSI_RESULT + - name: GAIN_REDU_STATE + byte_offset: 45 + bit_size: 8 + access: R + description: Gain reduction state register + fieldset: GAIN_REDU_STATE + - name: CAP_SENSOR_CONTROL + byte_offset: 46 + bit_size: 8 + access: RW + description: Capacitive sensor control register + fieldset: CAP_SENSOR_CONTROL + - name: CAP_SENSOR_DISP + byte_offset: 47 + bit_size: 8 + access: R + description: Capacitive sensor display register + fieldset: CAP_SENSOR_DISP + - name: AUX_DISPLAY + byte_offset: 48 + bit_size: 8 + access: R + description: Auxiliary display register + fieldset: AUX_DISPLAY + - name: WUP_TIMER_CONTROL + byte_offset: 49 + bit_size: 8 + access: RW + description: Wake-up timer control register + fieldset: WUP_TIMER_CONTROL + - name: AMPLITUDE_MEASURE_CONF + byte_offset: 50 + bit_size: 8 + access: RW + description: Amplitude measurement configuration register + fieldset: AMPLITUDE_MEASURE_CONF + - name: AMPLITUDE_MEASURE_REF + byte_offset: 51 + bit_size: 8 + access: RW + description: Amplitude measurement reference register + - name: AMPLITUDE_MEASURE_AUTO_AVG_DISP + byte_offset: 52 + bit_size: 8 + access: R + description: Amplitude measurement auto-averaging display + - name: AMPLITUDE_MEASURE_DISP + byte_offset: 53 + bit_size: 8 + access: R + description: Amplitude measurement display + - name: PHASE_MEASURE_CONF + byte_offset: 54 + bit_size: 8 + access: RW + description: Phase measurement configuration + fieldset: PHASE_MEASURE_CONF + - name: PHASE_MEASURE_REF + byte_offset: 55 + bit_size: 8 + access: RW + description: Phase measurement reference + - name: PHASE_MEASURE_AUTO_AVG_DISP + byte_offset: 56 + bit_size: 8 + access: R + description: Phase measurement auto-averaging display + - name: PHASE_MEASURE_DISP + byte_offset: 57 + bit_size: 8 + access: R + description: Phase measurement display + - name: CAPACITANCE_MEASURE_CONF + byte_offset: 58 + bit_size: 8 + access: RW + description: Capacitance measurement configuration + fieldset: CAPACITANCE_MEASURE_CONF + - name: CAPACITANCE_MEASURE_REF + byte_offset: 59 + bit_size: 8 + access: RW + description: Capacitance measurement reference + - name: CAPACITANCE_MEASURE_AUTO_AVG_DISP + byte_offset: 60 + bit_size: 8 + access: R + description: Capacitance measurement auto-averaging display + - name: CAPACITANCE_MEASURE_DISP + byte_offset: 61 + bit_size: 8 + access: R + description: Capacitance measurement display + - name: IC_IDENTITY + byte_offset: 63 + bit_size: 8 + access: R + description: IC identity register + fieldset: IC_IDENTITY +fieldset/IO_CONF1: + bit_size: 8 + fields: + - name: lf_clk_off + bit_offset: 0 + bit_size: 1 + - name: out_cl + bit_offset: 1 + bit_size: 2 + enum: IO_CONF1_out_cl + - name: osc + bit_offset: 3 + bit_size: 1 + default: 1 + - name: fifo_lt + bit_offset: 4 + bit_size: 2 + - name: rfo2 + bit_offset: 6 + bit_size: 1 + - name: single + bit_offset: 7 + bit_size: 1 +fieldset/IO_CONF2: + bit_size: 8 + fields: + - name: slow_up + bit_offset: 0 + bit_size: 1 + - name: io_18 + bit_offset: 2 + bit_size: 1 + - name: miso_pd1 + bit_offset: 3 + bit_size: 1 + - name: miso_pd2 + bit_offset: 4 + bit_size: 1 + - name: vspd_off + bit_offset: 6 + bit_size: 1 + - name: sup_3v + bit_offset: 7 + bit_size: 1 +fieldset/OP_CONTROL: + bit_size: 8 + fields: + - name: wu + bit_offset: 2 + bit_size: 1 + - name: tx_en + bit_offset: 3 + bit_size: 1 + - name: rx_man + bit_offset: 4 + bit_size: 1 + - name: rx_chn + bit_offset: 5 + bit_size: 1 + - name: rx_en + bit_offset: 6 + bit_size: 1 + - name: en + bit_offset: 7 + bit_size: 1 +fieldset/MODE: + bit_size: 8 + fields: + - name: nfc_ar + bit_offset: 0 + bit_size: 1 + - name: om + bit_offset: 3 + bit_size: 4 + enum: MODE_om + default: 1 + - name: targ + bit_offset: 7 + bit_size: 1 +fieldset/BIT_RATE: + bit_size: 8 + fields: + - name: rxrate + bit_offset: 0 + bit_size: 4 + enum: BIT_RATE_E + - name: txrate + bit_offset: 4 + bit_size: 4 + enum: BIT_RATE_E +fieldset/ISO14443A_NFC: + bit_size: 8 + fields: + - name: antcl + bit_offset: 0 + bit_size: 1 + - name: p_len + bit_offset: 1 + bit_size: 4 + - name: nfc_f0 + bit_offset: 5 + bit_size: 1 + - name: no_rx_par + bit_offset: 6 + bit_size: 1 + - name: no_tx_par + bit_offset: 7 + bit_size: 1 +fieldset/ISO14443B_1: + bit_size: 8 + fields: + - name: rx_st_om + bit_offset: 0 + bit_size: 1 + - name: half + bit_offset: 1 + bit_size: 1 + - name: eof + bit_offset: 2 + bit_size: 1 + - name: sof_1 + bit_offset: 3 + bit_size: 1 + enum: ISO14443B_1_sof_1 + - name: sof_0 + bit_offset: 4 + bit_size: 1 + enum: ISO14443B_1_sof_0 + - name: egt + bit_offset: 5 + bit_size: 3 +fieldset/ISO14443B_2: + bit_size: 8 + fields: + - name: f_p + bit_offset: 0 + bit_size: 2 + enum: ISO14443B_2_f_p + - name: phc_th + bit_offset: 2 + bit_size: 1 + - name: eof_12 + bit_offset: 3 + bit_size: 1 + - name: no_eof + bit_offset: 4 + bit_size: 1 + - name: no_sof + bit_offset: 5 + bit_size: 1 + - name: tr1 + bit_offset: 6 + bit_size: 2 + enum: ISO14443B_2_tr1 +fieldset/STREAM_MODE: + bit_size: 8 + fields: + - name: stx + bit_offset: 0 + bit_size: 3 + enum: STREAM_MODE_stx + - name: scp + bit_offset: 3 + bit_size: 2 + enum: STREAM_MODE_scp + - name: scf + bit_offset: 5 + bit_size: 2 + enum: STREAM_MODE_scf +fieldset/AUX: + bit_size: 8 + fields: + - name: nfc_n + bit_offset: 0 + bit_size: 2 + - name: rx_tol + bit_offset: 2 + bit_size: 1 + - name: ook_hr + bit_offset: 3 + bit_size: 1 + - name: en_fd + bit_offset: 4 + bit_size: 1 + - name: tr_am + bit_offset: 5 + bit_size: 1 + - name: crc_2_fifo + bit_offset: 6 + bit_size: 1 + - name: no_crc_rx + bit_offset: 7 + bit_size: 1 +fieldset/RX_CONF1: + bit_size: 8 + fields: + - name: z12k + bit_offset: 0 + bit_size: 1 + - name: h80 + bit_offset: 1 + bit_size: 1 + - name: h200 + bit_offset: 2 + bit_size: 1 + - name: lp + bit_offset: 3 + bit_size: 3 + enum: RX_CONF1_lp + - name: amd_sel + bit_offset: 6 + bit_size: 1 + - name: ch_sel + bit_offset: 7 + bit_size: 1 +fieldset/RX_CONF2: + bit_size: 8 + fields: + - name: pmix_cl + bit_offset: 0 + bit_size: 1 + - name: sqm_dyn + bit_offset: 1 + bit_size: 1 + - name: agc_alg + bit_offset: 2 + bit_size: 1 + - name: agc_m + bit_offset: 3 + bit_size: 1 + - name: agc_en + bit_offset: 4 + bit_size: 1 + - name: lf_en + bit_offset: 5 + bit_size: 1 + - name: lf_op + bit_offset: 6 + bit_size: 1 + - name: rx_lp + bit_offset: 7 + bit_size: 1 +fieldset/RX_CONF3: + bit_size: 8 + fields: + - name: rg_nfc + bit_offset: 0 + bit_size: 1 + - name: lim + bit_offset: 1 + bit_size: 1 + - name: rg1_pm + bit_offset: 2 + bit_size: 3 + - name: rg1_am + bit_offset: 5 + bit_size: 3 +fieldset/RX_CONF4: + bit_size: 8 + fields: + - name: rg2_pm + bit_offset: 0 + bit_size: 4 + - name: rg2_am + bit_offset: 4 + bit_size: 4 +fieldset/MASK_RX_TIMER: + bit_size: 8 + fields: + - name: mrt0 + bit_offset: 0 + bit_size: 1 + default: 0 + - name: mrt1 + bit_offset: 1 + bit_size: 1 + default: 0 + - name: mrt2 + bit_offset: 2 + bit_size: 1 + default: 0 + - name: mrt3 + bit_offset: 3 + bit_size: 1 + default: 0 + - name: mrt4 + bit_offset: 4 + bit_size: 1 + default: 0 + - name: mrt5 + bit_offset: 5 + bit_size: 1 + default: 0 + - name: mrt6 + bit_offset: 6 + bit_size: 1 + default: 0 + - name: mrt7 + bit_offset: 7 + bit_size: 1 + default: 0 +fieldset/NO_RESPONSE_TIMER1: + bit_size: 8 + fields: + - name: nrt8 + bit_offset: 0 + bit_size: 1 + default: 0 + - name: nrt9 + bit_offset: 1 + bit_size: 1 + default: 0 + - name: nrt10 + bit_offset: 2 + bit_size: 1 + default: 0 + - name: nrt11 + bit_offset: 3 + bit_size: 1 + default: 0 + - name: nrt12 + bit_offset: 4 + bit_size: 1 + default: 0 + - name: nrt13 + bit_offset: 5 + bit_size: 1 + default: 0 + - name: nrt14 + bit_offset: 6 + bit_size: 1 + default: 0 + - name: nrt15 + bit_offset: 7 + bit_size: 1 + default: 0 +fieldset/GPT_NRT_CTRL: + bit_size: 8 + fields: + - name: nrt_step + bit_offset: 0 + bit_size: 1 + enum: TIMER_EMV_CONTROL_nrt_step + - name: nrt_emv + bit_offset: 1 + bit_size: 1 + - name: gptc + bit_offset: 5 + bit_size: 3 + enum: TIMER_EMV_CONTROL_gptc +fieldset/IRQ_MASK_MAIN: + bit_size: 8 + fields: + - name: m_col + bit_offset: 2 + bit_size: 1 + - name: m_txe + bit_offset: 3 + bit_size: 1 + - name: m_rxe + bit_offset: 4 + bit_size: 1 + - name: m_rxs + bit_offset: 5 + bit_size: 1 + - name: m_wl + bit_offset: 6 + bit_size: 1 + - name: m_osc + bit_offset: 7 + bit_size: 1 +fieldset/IRQ_MASK_TIMER_NFC: + bit_size: 8 + fields: + - name: m_nfct + bit_offset: 0 + bit_size: 1 + - name: m_cat + bit_offset: 1 + bit_size: 1 + - name: m_cac + bit_offset: 2 + bit_size: 1 + - name: m_eof + bit_offset: 3 + bit_size: 1 + - name: m_eon + bit_offset: 4 + bit_size: 1 + - name: m_gpe + bit_offset: 5 + bit_size: 1 + - name: m_nre + bit_offset: 6 + bit_size: 1 + - name: m_dcd + bit_offset: 7 + bit_size: 1 +fieldset/IRQ_MASK_ERROR_WUP: + bit_size: 8 + fields: + - name: m_ncap + bit_offset: 0 + bit_size: 1 + - name: m_wph + bit_offset: 1 + bit_size: 1 + - name: m_wam + bit_offset: 2 + bit_size: 1 + - name: m_wt + bit_offset: 3 + bit_size: 1 + - name: m_err1 + bit_offset: 4 + bit_size: 1 + - name: m_err2 + bit_offset: 5 + bit_size: 1 + - name: m_par + bit_offset: 6 + bit_size: 1 + - name: m_crc + bit_offset: 7 + bit_size: 1 +fieldset/IRQ_MAIN: + bit_size: 8 + fields: + - name: err + bit_offset: 0 + bit_size: 1 + - name: tim + bit_offset: 1 + bit_size: 1 + - name: col + bit_offset: 2 + bit_size: 1 + - name: txe + bit_offset: 3 + bit_size: 1 + - name: rxe + bit_offset: 4 + bit_size: 1 + - name: rxs + bit_offset: 5 + bit_size: 1 + - name: wl + bit_offset: 6 + bit_size: 1 + - name: osc + bit_offset: 7 + bit_size: 1 +fieldset/IRQ_TIMER_NFC: + bit_size: 8 + fields: + - name: nfct + bit_offset: 0 + bit_size: 1 + - name: cat + bit_offset: 1 + bit_size: 1 + - name: cac + bit_offset: 2 + bit_size: 1 + - name: eof + bit_offset: 3 + bit_size: 1 + - name: eon + bit_offset: 4 + bit_size: 1 + - name: gpe + bit_offset: 5 + bit_size: 1 + - name: nre + bit_offset: 6 + bit_size: 1 + - name: dcd + bit_offset: 7 + bit_size: 1 +fieldset/FIFO_STATUS2: + bit_size: 8 + fields: + - name: np_lb + bit_offset: 0 + bit_size: 1 + - name: fifo_lb + bit_offset: 1 + bit_size: 3 + - name: fifo_ovr + bit_offset: 5 + bit_size: 1 + - name: fifo_unf + bit_offset: 6 + bit_size: 1 +fieldset/COLLISION_STATUS: + bit_size: 8 + fields: + - name: c_pb + bit_offset: 0 + bit_size: 1 + - name: c_bit + bit_offset: 1 + bit_size: 3 + - name: c_byte + bit_offset: 4 + bit_size: 4 +fieldset/NUM_TX_BYTES2: + bit_size: 8 + fields: + - name: nbtx + bit_offset: 0 + bit_size: 3 + - name: ntx + bit_offset: 3 + bit_size: 5 +fieldset/NFCIP1_BIT_RATE_DISP: + bit_size: 8 + fields: + - name: nfc_rate + bit_offset: 4 + bit_size: 4 +fieldset/ANT_TUNE_CTRL: + bit_size: 8 + fields: + - name: tre + bit_offset: 3 + bit_size: 4 + - name: trim_s + bit_offset: 7 + bit_size: 1 +fieldset/ANT_TUNE_DISP: + bit_size: 8 + fields: + - name: tri_err + bit_offset: 3 + bit_size: 1 + - name: tri + bit_offset: 4 + bit_size: 4 +fieldset/AM_MOD_DEPTH_CTRL: + bit_size: 8 + fields: + - name: modd + bit_offset: 1 + bit_size: 6 + - name: am_s + bit_offset: 7 + bit_size: 1 +fieldset/RFO_AM_LEVEL_DEF: + bit_size: 8 + fields: + - name: d0 + bit_offset: 0 + bit_size: 1 + default: 0 + - name: d1 + bit_offset: 1 + bit_size: 1 + default: 0 + - name: d2 + bit_offset: 2 + bit_size: 1 + default: 0 + - name: d3 + bit_offset: 3 + bit_size: 1 + default: 0 + - name: d4 + bit_offset: 4 + bit_size: 1 + default: 0 + - name: d5 + bit_offset: 5 + bit_size: 1 + default: 0 + - name: d6 + bit_offset: 6 + bit_size: 1 + default: 0 + - name: d7 + bit_offset: 7 + bit_size: 1 + default: 0 +fieldset/EXT_FIELD_DET_THR: + bit_size: 8 + fields: + - name: rfe_t + bit_offset: 0 + bit_size: 4 + default: 3 + enum: THRESHOLD_DEF + - name: trg_l + bit_offset: 4 + bit_size: 3 + default: 3 + enum: THRESHOLD_DEF +fieldset/REGULATOR_VOLT_CONTROL: + bit_size: 8 + fields: + - name: mpsv + bit_offset: 1 + bit_size: 2 + - name: rege + bit_offset: 3 + bit_size: 4 + - name: reg_s + bit_offset: 7 + bit_size: 1 +fieldset/REGULATOR_AND_TIM_DISP: + bit_size: 8 + fields: + - name: mrt_on + bit_offset: 0 + bit_size: 1 + - name: nrt_on + bit_offset: 1 + bit_size: 1 + - name: gpt_on + bit_offset: 2 + bit_size: 1 + - name: reg + bit_offset: 4 + bit_size: 4 +fieldset/RSSI_RESULT: + bit_size: 8 + fields: + - name: rssi_pm + bit_offset: 0 + bit_size: 4 + - name: rssi_am + bit_offset: 4 + bit_size: 4 +fieldset/GAIN_REDU_STATE: + bit_size: 8 + fields: + - name: gs_pm + bit_offset: 0 + bit_size: 4 + - name: gs_am + bit_offset: 4 + bit_size: 4 +fieldset/CAP_SENSOR_CONTROL: + bit_size: 8 + fields: + - name: cs_g + bit_offset: 0 + bit_size: 3 + - name: cs_mcal + bit_offset: 3 + bit_size: 5 +fieldset/CAP_SENSOR_DISP: + bit_size: 8 + fields: + - name: cs_cal_err + bit_offset: 1 + bit_size: 1 + - name: cs_cal_end + bit_offset: 2 + bit_size: 1 + - name: cs_cal_val + bit_offset: 3 + bit_size: 5 +fieldset/AUX_DISPLAY: + bit_size: 8 + fields: + - name: en_ac + bit_offset: 0 + bit_size: 1 + - name: nfc_t + bit_offset: 1 + bit_size: 1 + - name: rx_act + bit_offset: 2 + bit_size: 1 + - name: rx_on + bit_offset: 3 + bit_size: 1 + - name: osc_ok + bit_offset: 4 + bit_size: 1 + - name: tx_on + bit_offset: 5 + bit_size: 1 + - name: efd_o + bit_offset: 6 + bit_size: 1 + - name: a_cha + bit_offset: 7 + bit_size: 1 +fieldset/WUP_TIMER_CONTROL: + bit_size: 8 + fields: + - name: wph + bit_offset: 1 + bit_size: 1 + - name: wam + bit_offset: 2 + bit_size: 1 + - name: wto + bit_offset: 3 + bit_size: 1 + - name: wut + bit_offset: 4 + bit_size: 3 + - name: wur + bit_offset: 7 + bit_size: 1 +fieldset/AMPLITUDE_MEASURE_CONF: + bit_size: 8 + fields: + - name: am_ae + bit_offset: 0 + bit_size: 1 + - name: am_aew + bit_offset: 1 + bit_size: 2 + - name: am_aam + bit_offset: 3 + bit_size: 1 + - name: am_d + bit_offset: 4 + bit_size: 4 +fieldset/PHASE_MEASURE_CONF: + bit_size: 8 + fields: + - name: pm_ae + bit_offset: 0 + bit_size: 1 + - name: pm_aew + bit_offset: 1 + bit_size: 2 + - name: pm_aam + bit_offset: 3 + bit_size: 1 + - name: pm_d + bit_offset: 4 + bit_size: 4 +fieldset/CAPACITANCE_MEASURE_CONF: + bit_size: 8 + fields: + - name: cm_ae + bit_offset: 0 + bit_size: 1 + - name: cm_aew + bit_offset: 1 + bit_size: 2 + - name: cm_aam + bit_offset: 3 + bit_size: 1 + - name: cm_d + bit_offset: 4 + bit_size: 4 +fieldset/IC_IDENTITY: + bit_size: 8 + fields: + - name: ic_rev + bit_offset: 0 + bit_size: 3 + enum: IC_IDENTITY_ic_rev + - name: ic_type + bit_offset: 3 + bit_size: 5 + enum: IC_IDENTITY_ic_type +enum/BIT_RATE_E: + bit_size: 4 + variants: + - name: 106 + value: 0 + - name: 212 + value: 1 + - name: 424 + value: 2 + - name: 848 + value: 3 + - name: 1695 + value: 4 + - name: 3390 + value: 5 + - name: 6780 + value: 6 +enum/THRESHOLD_DEF: + bit_size: 8 + variants: + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 + - name: 25mv + value: 8 + - name: 33mv + value: 9 + - name: 47mv + value: 10 + - name: 64mv + value: 11 + - name: 90mv + value: 12 + - name: 125mv + value: 13 + - name: 175mv + value: 14 + - name: 250mv + value: 15 +enum/WAKEUP_TIMES_DEF: + bit_size: 8 + variants: + - name: 10 + value: 0 + - name: 20 + value: 1 + - name: 30 + value: 2 + - name: 40 + value: 3 + - name: 50 + value: 4 + - name: 60 + value: 5 + - name: 70 + value: 6 + - name: 80 + value: 7 +enum/IC_IDENTITY_ic_rev: + bit_size: 3 + variants: + - name: v0 + value: 0 + - name: v3_1 + value: 2 + - name: v3_3 + value: 3 + - name: v4_0 + value: 4 + - name: v4_1 + value: 5 +enum/IC_IDENTITY_ic_type: + bit_size: 5 + variants: + - name: st25r3916 + value: 5 +enum/IO_CONF1_out_cl: + bit_size: 2 + variants: + - name: _3_39_mhz + value: 0 + - name: _6_78_mhz + value: 1 + - name: _13_86_mhz + value: 2 + - name: disabled + value: 3 +enum/ISO14443B_1_sof_1: + bit_size: 1 + variants: + - name: 2etu + value: 0 + - name: 3etu + value: 1 +enum/ISO14443B_1_sof_0: + bit_size: 1 + variants: + - name: 10etu + value: 0 + - name: 11etu + value: 1 +enum/ISO14443B_2_f_p: + bit_size: 2 + variants: + - name: 48 + value: 0 + - name: 64 + value: 1 + - name: 80 + value: 2 + - name: 96 + value: 3 +enum/ISO14443B_2_tr1: + bit_size: 2 + variants: + - name: 80fs80fs + value: 0 + - name: 64fs32fs + value: 1 +enum/MODE_om: + bit_size: 4 + variants: + - name: targ_nfcip1_active_comm_br_det + value: 0 + - name: targ_nfcip1_active_comm_normal + value: 0 + - name: ini_iso14443a + value: 1 + - name: targ_nfca + value: 1 + - name: ini_iso14443b + value: 2 + - name: targ_nfcb + value: 2 + - name: ini_felica + value: 3 + - name: ini_topaz + value: 4 + - name: targ_nfcf + value: 4 + - name: ini_subcarrier_stream + value: 14 + - name: ini_bpsk_stream + value: 15 +enum/RX_CONF1_lp: + bit_size: 3 + variants: + - name: 1200khz + value: 0 + - name: 600khz + value: 1 + - name: 300khz + value: 2 + - name: 2000khz + value: 4 + - name: 7000khz + value: 5 +enum/STREAM_MODE_scf: + bit_size: 2 + variants: + - name: bpsk848 + value: 0 + - name: sc212 + value: 0 + - name: bpsk1695 + value: 1 + - name: sc424 + value: 1 + - name: bpsk3390 + value: 2 + - name: sc848 + value: 2 + - name: bpsk106 + value: 3 + - name: sc1695 + value: 3 +enum/STREAM_MODE_scp: + bit_size: 2 + variants: + - name: 1pulse + value: 0 + - name: 2pulses + value: 1 + - name: 4pulses + value: 2 + - name: 8pulses + value: 3 +enum/STREAM_MODE_stx: + bit_size: 3 + variants: + - name: 106 + value: 0 + - name: 212 + value: 1 + - name: 424 + value: 2 + - name: 848 + value: 3 +enum/TIMER_EMV_CONTROL_gptc: + bit_size: 3 + variants: + - name: no_trigger + value: 0 + - name: erx + value: 1 + - name: srx + value: 2 + - name: etx_nfc + value: 3 +enum/TIMER_EMV_CONTROL_nrt_step: + bit_size: 1 + variants: + - name: 64_fc + value: 0 + - name: 4096_fc + value: 1 diff --git a/rnfc-st25r39/src/regs.yaml b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml similarity index 100% rename from rnfc-st25r39/src/regs.yaml rename to rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml From b97bb58ad85d9e983553bf762b4279129225509f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Tue, 18 Feb 2025 18:22:13 +0100 Subject: [PATCH 2/8] multichip support, approach 2 discussed in PR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Królczyk --- ci.sh | 12 +- examples/st25r39-disco/src/main.rs | 3 +- rnfc-st25r39/Cargo.toml | 4 +- rnfc-st25r39/src/aat.rs | 9 +- .../{st25r3911b.rs => cmds_st25r3911b.rs} | 0 .../{st25r3916.rs => cmds_st25r3916.rs} | 0 rnfc-st25r39/src/commands/mod.rs | 13 +- rnfc-st25r39/src/commands/stub.rs | 15 + .../src/{ => impls}/lib_st25r3911b.rs | 18 +- rnfc-st25r39/src/impls/lib_st25r3916.rs | 530 +++++++++++++++ rnfc-st25r39/src/impls/mod.rs | 95 +++ rnfc-st25r39/src/impls/stub.rs | 59 ++ rnfc-st25r39/src/iso14443a.rs | 24 +- rnfc-st25r39/src/lib.rs | 636 +----------------- rnfc-st25r39/src/lib_st25r3916.rs | 6 - rnfc-st25r39/src/regs/mod.rs | 67 ++ .../src/{ => regs}/regs_st25r3911b.rs | 3 +- rnfc-st25r39/src/{ => regs}/regs_st25r3916.rs | 3 +- rnfc-st25r39/src/regs/stub.rs | 310 +++++++++ 19 files changed, 1133 insertions(+), 674 deletions(-) rename rnfc-st25r39/src/commands/{st25r3911b.rs => cmds_st25r3911b.rs} (100%) rename rnfc-st25r39/src/commands/{st25r3916.rs => cmds_st25r3916.rs} (100%) create mode 100644 rnfc-st25r39/src/commands/stub.rs rename rnfc-st25r39/src/{ => impls}/lib_st25r3911b.rs (97%) create mode 100644 rnfc-st25r39/src/impls/lib_st25r3916.rs create mode 100644 rnfc-st25r39/src/impls/mod.rs create mode 100644 rnfc-st25r39/src/impls/stub.rs delete mode 100644 rnfc-st25r39/src/lib_st25r3916.rs create mode 100644 rnfc-st25r39/src/regs/mod.rs rename rnfc-st25r39/src/{ => regs}/regs_st25r3911b.rs (99%) rename rnfc-st25r39/src/{ => regs}/regs_st25r3916.rs (99%) create mode 100644 rnfc-st25r39/src/regs/stub.rs diff --git a/ci.sh b/ci.sh index 5661cac..6eb022c 100755 --- a/ci.sh +++ b/ci.sh @@ -17,12 +17,14 @@ cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features '' cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features 'defmt' cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features 'log' +echo "no-features" cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features '' -cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'defmt' -cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'log' -cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --no-default-features --features 'st25r3911b' -cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --no-default-features --features 'st25r3911b,defmt' -cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --no-default-features --features 'st25r3911b,log' +echo "st25r3916" +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3916, defmt' +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3916, log' +echo "st25r3911b" +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3911b, defmt' +cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3911b, log' cargo build --release --manifest-path rnfc-acr122u/Cargo.toml --features '' diff --git a/examples/st25r39-disco/src/main.rs b/examples/st25r39-disco/src/main.rs index 7b571d3..0928483 100644 --- a/examples/st25r39-disco/src/main.rs +++ b/examples/st25r39-disco/src/main.rs @@ -19,7 +19,8 @@ use embassy_time::{Duration, Timer}; use rnfc::iso14443a::Poller; use rnfc::iso_dep::IsoDepA; use rnfc::traits::iso_dep::Reader; -use rnfc_st25r39::{SpiInterface, St25r39, WakeupConfig, WakeupMethodConfig, WakeupPeriod, WakeupReference}; +use rnfc_st25r39::impls::{WakeupConfig, WakeupMethodConfig, WakeupPeriod, WakeupReference}; +use rnfc_st25r39::{SpiInterface, St25r39}; use {defmt_rtt as _, panic_probe as _}; #[embassy_executor::main] diff --git a/rnfc-st25r39/Cargo.toml b/rnfc-st25r39/Cargo.toml index bbccae7..13af157 100644 --- a/rnfc-st25r39/Cargo.toml +++ b/rnfc-st25r39/Cargo.toml @@ -4,10 +4,10 @@ version = "0.1.0" edition = "2021" [features] -defmt = [ "dep:defmt", "rnfc-traits/defmt", "heapless/defmt-03" ] +defmt = ["dep:defmt", "rnfc-traits/defmt", "heapless/defmt-03"] st25r3916 = [] st25r3911b = [] -default = [ "st25r3916" ] +default = [] [dependencies] defmt = { version = "0.3", optional = true } diff --git a/rnfc-st25r39/src/aat.rs b/rnfc-st25r39/src/aat.rs index 3428743..ea2fa81 100644 --- a/rnfc-st25r39/src/aat.rs +++ b/rnfc-st25r39/src/aat.rs @@ -54,9 +54,10 @@ impl St25r39 { a = new_a; b = new_b; } - #[cfg(not(feature = "st25r3911b"))] + + #[cfg(feature = "st25r3916")] self.regs().ant_tune_a().write_value(a)?; - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] self.regs().ant_tune_a().write_value(b)?; // st25r3911b chip might offer a better approach, simlar to what lib does @@ -72,9 +73,9 @@ impl St25r39 { } async fn aat_measure(&mut self, a: u8, b: u8, conf: &AatConfig) -> Result> { - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] self.regs().ant_tune_a().write_value(a)?; - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] self.regs().ant_tune_a().write_value(b)?; // Wait for caps to settle. diff --git a/rnfc-st25r39/src/commands/st25r3911b.rs b/rnfc-st25r39/src/commands/cmds_st25r3911b.rs similarity index 100% rename from rnfc-st25r39/src/commands/st25r3911b.rs rename to rnfc-st25r39/src/commands/cmds_st25r3911b.rs diff --git a/rnfc-st25r39/src/commands/st25r3916.rs b/rnfc-st25r39/src/commands/cmds_st25r3916.rs similarity index 100% rename from rnfc-st25r39/src/commands/st25r3916.rs rename to rnfc-st25r39/src/commands/cmds_st25r3916.rs diff --git a/rnfc-st25r39/src/commands/mod.rs b/rnfc-st25r39/src/commands/mod.rs index dd03a12..7e21b7c 100644 --- a/rnfc-st25r39/src/commands/mod.rs +++ b/rnfc-st25r39/src/commands/mod.rs @@ -1,9 +1,14 @@ #[cfg(feature = "st25r3916")] -pub mod st25r3916; +pub mod cmds_st25r3916; #[cfg(feature = "st25r3916")] -pub use st25r3916::Command; +pub use cmds_st25r3916::Command; #[cfg(feature = "st25r3911b")] -pub mod st25r3911b; +pub mod cmds_st25r3911b; #[cfg(feature = "st25r3911b")] -pub use st25r3911b::Command; +pub use cmds_st25r3911b::Command; + +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +mod stub; +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +pub use stub::Command; diff --git a/rnfc-st25r39/src/commands/stub.rs b/rnfc-st25r39/src/commands/stub.rs new file mode 100644 index 0000000..cbbcd59 --- /dev/null +++ b/rnfc-st25r39/src/commands/stub.rs @@ -0,0 +1,15 @@ +/// Direct commands +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[allow(unused)] +pub enum Command { + Stop, + SetDefault = 0xCA, + SetOther = 0xFE, + // required by iso14443a + ResetRxgain, + TransmitReqa, + TransmitWupa, + TransmitWithoutCrc, + TransmitWithCrc, +} diff --git a/rnfc-st25r39/src/lib_st25r3911b.rs b/rnfc-st25r39/src/impls/lib_st25r3911b.rs similarity index 97% rename from rnfc-st25r39/src/lib_st25r3911b.rs rename to rnfc-st25r39/src/impls/lib_st25r3911b.rs index 18872b9..4a44eab 100644 --- a/rnfc-st25r39/src/lib_st25r3911b.rs +++ b/rnfc-st25r39/src/impls/lib_st25r3911b.rs @@ -6,10 +6,12 @@ use embassy_time::{with_timeout, Duration, Instant, Timer}; use embedded_hal::digital::InputPin; use embedded_hal_async::digital::Wait; -pub use crate::commands::Command; -pub use crate::interface::Interface; +use crate::commands::Command; +use crate::impls::{FieldOnError, WakeupConfig, WakeupReference}; +use crate::interface::Interface; use crate::regs::Regs; -use crate::{regs, Error, FieldOnError, WakeupConfig, WakeupReference, DEFAULT_TIMEOUT}; +use crate::{regs, Error, Mode, St25r39}; +const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); // TODO: This is here temporarily, just to provide abstraction similar to st25r3916. // Thus - bits do not match. @@ -72,13 +74,13 @@ pub enum Interrupt { /// Device starts with default configuration. Initially the oscillator is not enabled. /// It's possible to verify register contents; then call `configure` to enable RF. -impl super::St25r39 { +impl St25r39 { pub async fn new(iface: I, irq: IrqPin) -> Result> { let mut this = Self { iface, irq, irqs: 0, - mode: super::Mode::Off, + mode: Mode::Off, }; this.init().await?; //this.configure(); @@ -223,14 +225,14 @@ impl super::St25r39 { } pub async fn mode_on(&mut self) -> Result<(), Error> { - self.mode = super::Mode::On; + self.mode = Mode::On; self.enable_osc().await?; Ok(()) } pub fn mode_off(&mut self) -> Result<(), Error> { - self.mode = super::Mode::Off; + self.mode = Mode::Off; self.cmd(Command::Stop)?; // disable everything self.regs().op_control().write(|_| {})?; @@ -288,7 +290,7 @@ impl super::St25r39 { pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { self.mode_on().await?; - self.mode = super::Mode::Wakeup; + self.mode = Mode::Wakeup; debug!("Entering wakeup mode"); self.cmd(Command::Stop)?; diff --git a/rnfc-st25r39/src/impls/lib_st25r3916.rs b/rnfc-st25r39/src/impls/lib_st25r3916.rs new file mode 100644 index 0000000..aca8787 --- /dev/null +++ b/rnfc-st25r39/src/impls/lib_st25r3916.rs @@ -0,0 +1,530 @@ +use embassy_futures::yield_now; +use embassy_time::{Duration, Instant}; +use embedded_hal::digital::InputPin; +use embedded_hal_async::digital::Wait; + +// use crate::aat::AatConfig; +use crate::commands::Command; +use crate::interface::Interface; +use crate::regs::{self, Regs}; +use crate::{Error, Mode, St25r39}; +pub const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); +use crate::impls::*; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[allow(unused)] +pub enum Interrupt { + /// RFU interrupt + Rfu = 0, + /// automatic reception restart interrupt + RxRest = 1, + /// bit collision interrupt + Col = 2, + /// end of transmission interrupt + Txe = 3, + /// end of receive interrupt + Rxe = 4, + /// start of receive interrupt + Rxs = 5, + /// FIFO water level interrupt + Fwl = 6, + /// oscillator stable interrupt + Osc = 7, + /// initiator bit rate recognised interrupt + Nfct = 8, + /// minimum guard time expired interrupt + Cat = 9, + /// collision during RF collision avoidance interrupt + Cac = 10, + /// external field off interrupt + Eof = 11, + /// external field on interrupt + Eon = 12, + /// general purpose timer expired interrupt + Gpe = 13, + /// no-response timer expired interrupt + Nre = 14, + /// termination of direct command interrupt + Dct = 15, + /// wake-up due to capacitance measurement + Wcap = 16, + /// wake-up due to phase interrupt + Wph = 17, + /// wake-up due to amplitude interrupt + Wam = 18, + /// wake-up interrupt + Wt = 19, + /// hard framing error interrupt + Err1 = 20, + /// soft framing error interrupt + Err2 = 21, + /// parity error interrupt + Par = 22, + /// CRC error interrupt + Crc = 23, + /// 106kb/s Passive target state interrupt: Active + WuA = 24, + /// 106kb/s Passive target state interrupt: Active* + WuAX = 25, + /// RFU2 interrupt + Rfu2 = 26, + /// 212/424b/s Passive target interrupt: Active + WuF = 27, + /// RXE with an automatic response interrupt + RxePta = 28, + /// Anticollision done and Field On interrupt + Apon = 29, + /// Passive target slot number water level interrupt + SlWl = 30, + /// PPON2 Field on waiting Timer interrupt + Ppon2 = 31, +} + +impl St25r39 { + pub async fn new(iface: I, irq: IrqPin) -> Result> { + let mut this = Self { + iface, + irq, + irqs: 0, + mode: Mode::On, + }; + this.init().await?; + Ok(this) + } + + pub fn regs(&mut self) -> Regs { + Regs::new(&mut self.iface) + } + + pub fn cmd(&mut self, cmd: Command) -> Result<(), Error> { + self.iface.do_command(cmd as u8).map_err(Error::Interface) + } + + async fn cmd_wait(&mut self, cmd: Command) -> Result<(), Error> { + self.irq_clear()?; + self.cmd(cmd)?; + self.irq_wait(Interrupt::Dct).await + } + + async fn enable_osc(&mut self) -> Result<(), Error> { + trace!("Starting osc..."); + self.regs().op_control().write(|w| w.set_en(true))?; + while !self.regs().aux_display().read()?.osc_ok() {} + Ok(()) + } + + async fn init(&mut self) -> Result<(), Error> { + self.cmd(Command::SetDefault)?; + + self.regs().test_unk().write(|w| { + w.set_dis_overheat_prot(true); + })?; + + let id = self.regs().ic_identity().read()?; + trace!("ic_type = {:02x} ic_rev = {:02x}", id.ic_type().0, id.ic_rev().0); + + // Enable OSC + self.enable_osc().await?; + + // Measure vdd + trace!("measuring vdd..."); + let vdd_mv = self.measure_vdd().await?; + trace!("measure vdd result = {}mv", vdd_mv); + + let sup3v = vdd_mv < 3600; + if sup3v { + trace!("using 3v3 supply mode"); + } else { + trace!("using 5v supply mode"); + } + + self.regs().io_conf2().write(|w| { + w.set_sup_3v(sup3v); + })?; + + // Disable MCU_CLK + self.regs().io_conf1().write(|w| { + w.set_out_cl(regs::IoConf1OutCl::DISABLED); + w.set_lf_clk_off(true); + })?; + + // Enable minimum non-overlap + //self.regs().res_am_mod().write(|w| w.set_fa3_f(true))?; + + // Set ext field detect activ/deactiv thresholds + //self.regs().field_threshold_actv().write(|w| { + // w.set_trg(regs::FieldThresholdActvTrg::_105MV); + // w.set_rfe(regs::FieldThresholdActvRfe::_105MV); + //})?; + //self.regs().field_threshold_deactv().write(|w| { + // w.set_trg(regs::FieldThresholdDeactvTrg::_75MV); + // w.set_rfe(regs::FieldThresholdDeactvRfe::_75MV); + //})?; + + //self.regs().aux_mod().write(|w| { + // w.set_lm_ext(false); // Disable external Load Modulation + // w.set_lm_dri(true); // Enable internal Load Modulation + //})?; + + //self.regs().emd_sup_conf().write(|w| { + // w.set_rx_start_emv(true); + //})?; + + // AAT not in use + //self.regs().ant_tune_a().write_value(0x82)?; + //self.regs().ant_tune_b().write_value(0x82)?; + + self.regs().op_control().modify(|w| { + w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); + })?; + + // Adjust regulators + + // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. + self.regs().regulator_control().write(|w| w.set_reg_s(true))?; + self.regs().regulator_control().write(|w| w.set_reg_s(false))?; + + self.cmd_wait(Command::AdjustRegulators).await?; + + let res = self.regs().regulator_result().read()?.0; + trace!("reg result = {}", res); + + Ok(()) + } + + pub(crate) fn mode_off(&mut self) -> Result<(), Error> { + self.mode = Mode::Off; + self.cmd(Command::Stop)?; + // disable everything + self.regs().op_control().write(|_| {})?; + Ok(()) + } + + pub async fn measure_amplitude(&mut self) -> Result> { + self.cmd_wait(Command::MeasureAmplitude).await?; + self.regs().ad_result().read() + } + + pub async fn measure_phase(&mut self) -> Result> { + self.cmd_wait(Command::MeasurePhase).await?; + self.regs().ad_result().read() + } + + pub async fn measure_capacitance(&mut self) -> Result> { + self.cmd_wait(Command::MeasureCapacitance).await?; + self.regs().ad_result().read() + } + + pub async fn calibrate_capacitance(&mut self) -> Result> { + self.regs().cap_sensor_control().write(|w| { + // Clear Manual calibration values to enable automatic calibration mode + w.set_cs_mcal(0); + w.set_cs_g(0b01); // 6.5v/pF, highest one + })?; + + // Don't use `cmd_wait`, the irq only fires in Ready mode (op_control.en = 1). + // Instead, wait for cap_sensor_result.cs_cal_end + self.cmd(Command::CalibrateCSensor)?; + + let deadline = Instant::now() + DEFAULT_TIMEOUT; + + let res = loop { + if Instant::now() > deadline { + return Err(Error::Timeout); + } + + let res = self.regs().cap_sensor_result().read()?; + if res.cs_cal_err() { + panic!("Capacitive sensor calibration failed!"); + } + if res.cs_cal_end() { + break res; + } + + yield_now().await; + }; + Ok(res.cs_cal_val()) + } + + pub(crate) async fn mode_on(&mut self) -> Result<(), Error> { + self.mode = Mode::On; + self.enable_osc().await?; + + self.regs().op_control().modify(|w| { + w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); + })?; + self.regs().tx_driver().write(|w| { + w.set_d_res(3); + })?; + Ok(()) + } + + /// Change into wakeup mode, return immediately. + /// The IRQ pin will go high on wakeup. + pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { + self.mode_on().await?; + + self.mode = Mode::Wakeup; + debug!("Entering wakeup mode"); + + self.cmd(Command::Stop)?; + self.regs().op_control().write(|_| {})?; + self.regs().mode().write(|w| w.set_om(regs::ModeOm::INI_ISO14443A))?; + + let mut wtc = regs::WupTimerControl(0); + let mut irqs = 0; + + wtc.set_wur(config.period as u8 & 0x10 == 0); + wtc.set_wut(config.period as u8 & 0x0F); + + if let Some(m) = config.inductive_amplitude { + let mut conf = regs::AmplitudeMeasureConf(0); + conf.set_am_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().amplitude_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_amplitude().await?; + self.regs().amplitude_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_amplitude().await?; + self.regs().amplitude_measure_ref().write_value(val)?; + conf.set_am_ae(true); + conf.set_am_aam(include_irq_measurement); + conf.set_am_aew(weight); + } + } + self.regs().amplitude_measure_conf().write_value(conf)?; + wtc.set_wam(true); + irqs |= 1 << Interrupt::Wam as u32; + } + if let Some(m) = config.inductive_phase { + let mut conf = regs::PhaseMeasureConf(0); + conf.set_pm_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().phase_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_phase().await?; + self.regs().phase_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_phase().await?; + self.regs().phase_measure_ref().write_value(val)?; + conf.set_pm_ae(true); + conf.set_pm_aam(include_irq_measurement); + conf.set_pm_aew(weight); + } + } + self.regs().phase_measure_conf().write_value(conf)?; + wtc.set_wph(true); + irqs |= 1 << Interrupt::Wph as u32; + } + if let Some(m) = config.capacitive { + debug!("capacitance calibrating..."); + let val = self.calibrate_capacitance().await?; + info!("capacitance calibrated: {}", val); + + let mut conf = regs::CapacitanceMeasureConf(0); + conf.set_cm_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().capacitance_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_capacitance().await?; + info!("Measured: {}", val); + self.regs().capacitance_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_capacitance().await?; + info!("Measured: {}", val); + self.regs().capacitance_measure_ref().write_value(val)?; + conf.set_cm_ae(true); + conf.set_cm_aam(include_irq_measurement); + conf.set_cm_aew(weight); + } + } + self.regs().capacitance_measure_conf().write_value(conf)?; + wtc.set_wcap(true); + irqs |= 1 << Interrupt::Wcap as u32; + } + + self.irq_clear()?; + + self.regs().wup_timer_control().write_value(wtc)?; + self.regs().op_control().write(|w| w.set_wu(true))?; + self.irq_set_mask(!irqs)?; + + debug!("Entered wakeup mode, waiting for pin IRQ"); + self.irq.wait_for_high().await.unwrap(); + debug!("got pin IRQ!"); + + Ok(()) + } + + pub async fn field_on(&mut self) -> Result<(), FieldOnError> { + self.regs().mode().write(|w| { + w.set_om(regs::ModeOm::INI_ISO14443A); + w.set_tr_am(false); // use OOK + })?; + self.regs().tx_driver().write(|w| { + w.set_am_mod(regs::TxDriverAmMod::_12PERCENT); + })?; + self.regs().aux_mod().write(|w| { + w.set_lm_dri(true); // Enable internal Load Modulation + w.set_dis_reg_am(false); // Enable regulator-based AM + w.set_res_am(false); + })?; + + // Default over/under shoot protiection + self.regs().overshoot_conf1().write_value(0x40.into())?; + self.regs().overshoot_conf2().write_value(0x03.into())?; + self.regs().undershoot_conf1().write_value(0x40.into())?; + self.regs().undershoot_conf2().write_value(0x03.into())?; + + self.regs().aux().write(|w| { + w.set_dis_corr(false); // Enable correlator reception + w.set_nfc_n(0); // todo this changes + })?; + /* + self.regs().rx_conf1().write_value(0x08.into())?; + self.regs().rx_conf2().write_value(0x2D.into())?; + self.regs().rx_conf3().write_value(0x00.into())?; + self.regs().rx_conf4().write_value(0x00.into())?; + self.regs().corr_conf1().write_value(0x51.into())?; + self.regs().corr_conf2().write_value(0x00.into())?; + */ + + self.regs().bit_rate().write(|w| { + w.set_rxrate(regs::BitRateE::_106); + w.set_txrate(regs::BitRateE::_106); + })?; + + // defaults + self.regs().iso14443a_nfc().write(|_| {})?; + + // Field ON + + // GT is done by software + self.regs().field_on_gt().write_value(0)?; + + self.irq_clear()?; // clear + self.cmd(Command::InitialRfCollision)?; + + loop { + if self.irq(Interrupt::Cac) { + return Err(FieldOnError::FieldCollision); + } + if self.irq(Interrupt::Apon) { + break; + } + + self.irq_update()?; + } + + self.regs().op_control().modify(|w| { + w.set_tx_en(true); + w.set_rx_en(true); + })?; + + Ok(()) + } + + async fn measure_vdd(&mut self) -> Result> { + self.regs() + .regulator_control() + .write(|w| w.set_mpsv(regs::RegulatorControlMpsv::VDD))?; + self.cmd_wait(Command::MeasureVdd).await?; + let res = self.regs().ad_result().read()? as u32; + + // result is in units of 23.4mV + Ok((res * 234 + 5) / 10) + } + + // ======================= + // irq stuff + + pub fn irq(&self, irq: Interrupt) -> bool { + return (self.irqs & (1 << (irq as u8))) != 0; + } + + pub async fn irq_wait_timeout(&mut self, irq: Interrupt, timeout: Duration) -> Result<(), Error> { + let deadline = Instant::now() + timeout; + self.irq_update()?; + while !self.irq(irq) { + if Instant::now() > deadline { + return Err(Error::Timeout); + } + yield_now().await; + self.irq_update()?; + } + Ok(()) + } + + pub async fn irq_wait(&mut self, irq: Interrupt) -> Result<(), Error> { + self.irq_wait_timeout(irq, DEFAULT_TIMEOUT).await + } + + pub fn irq_update(&mut self) -> Result<(), Error> { + for i in 0..4 { + self.irqs |= (self.regs().irq_main(i).read()? as u32) << (i * 8); + } + Ok(()) + } + + fn irq_clear(&mut self) -> Result<(), Error> { + self.irq_update()?; + self.irqs = 0; + Ok(()) + } + + fn irq_set_mask(&mut self, mask: u32) -> Result<(), Error> { + for i in 0..4 { + self.regs().irq_mask(i).write_value((mask >> (i * 8)) as u8)?; + } + Ok(()) + } + + pub fn raw(&mut self) -> Raw<'_, I, IrqPin> { + Raw { inner: self } + } +} + +pub struct Raw<'a, I: Interface, IrqPin: InputPin + Wait> { + inner: &'a mut St25r39, +} + +impl<'a, I: Interface, IrqPin: InputPin + Wait> Raw<'a, I, IrqPin> { + pub async fn field_on(&mut self) -> Result<(), FieldOnError> { + self.inner.mode_on().await?; + self.inner.field_on().await?; + Ok(()) + } + pub async fn field_off(&mut self) -> Result<(), Error> { + self.inner.mode_off()?; + Ok(()) + } + + pub async fn driver_hi_z(&mut self) -> Result<(), Error> { + self.inner.mode_off()?; + self.inner.regs().tx_driver().write(|w| { + w.set_d_res(15); // hi-z + })?; + + Ok(()) + } +} diff --git a/rnfc-st25r39/src/impls/mod.rs b/rnfc-st25r39/src/impls/mod.rs new file mode 100644 index 0000000..f2e07a0 --- /dev/null +++ b/rnfc-st25r39/src/impls/mod.rs @@ -0,0 +1,95 @@ +#[cfg(feature = "st25r3916")] +pub mod lib_st25r3916; +#[cfg(feature = "st25r3916")] +pub use lib_st25r3916::*; + +#[cfg(feature = "st25r3911b")] +pub mod lib_st25r3911b; +#[cfg(feature = "st25r3911b")] +pub use lib_st25r3911b::*; + +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +mod stub; +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +pub use stub::*; + +// TODO: check wup and other wake-up registers in st25r3911b +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WakeupPeriod { + /// 10ms + Ms10 = 0x00, + /// 20ms + Ms20 = 0x01, + /// 30ms + Ms30 = 0x02, + /// 40ms + Ms40 = 0x03, + /// 50ms + Ms50 = 0x04, + /// 60ms + Ms60 = 0x05, + /// 70ms + Ms70 = 0x06, + /// 80ms + Ms80 = 0x07, + /// 100ms + Ms100 = 0x10, + /// 200ms + Ms200 = 0x11, + /// 300ms + Ms300 = 0x12, + /// 400ms + Ms400 = 0x13, + /// 500ms + Ms500 = 0x14, + /// 600ms + Ms600 = 0x15, + /// 700ms + Ms700 = 0x16, + /// 800ms + Ms800 = 0x17, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct WakeupConfig { + pub period: WakeupPeriod, + pub inductive_amplitude: Option, + pub inductive_phase: Option, + pub capacitive: Option, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct WakeupMethodConfig { + pub delta: u8, + pub reference: WakeupReference, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WakeupReference { + Manual(u8), + Automatic, + AutoAverage { include_irq_measurement: bool, weight: u8 }, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FieldOnError { + /// There's some other device emitting its own field, so we shouldn't + /// turn ours on. + FieldCollision, + Interface(T), + Timeout, +} + +impl From> for FieldOnError { + fn from(val: crate::Error) -> Self { + match val { + crate::Error::Interface(e) => FieldOnError::Interface(e), + crate::Error::Timeout => FieldOnError::Timeout, + } + } +} diff --git a/rnfc-st25r39/src/impls/stub.rs b/rnfc-st25r39/src/impls/stub.rs new file mode 100644 index 0000000..b863f37 --- /dev/null +++ b/rnfc-st25r39/src/impls/stub.rs @@ -0,0 +1,59 @@ +use embedded_hal::digital::InputPin; +use embedded_hal_async::digital::Wait; + +use super::WakeupConfig; +use crate::commands::Command; +use crate::impls::FieldOnError; +use crate::regs::Regs; +use crate::{Error, Interface, Mode, St25r39}; + +impl St25r39 { + pub async fn new(iface: I, irq: IrqPin) -> Result> { + Ok(Self { + iface, + irq, + irqs: 0, + mode: Mode::Off, + }) + } + pub async fn mode_on(&mut self) -> Result<(), FieldOnError> { + self.mode = Mode::On; + let _ = Mode::Wakeup; + Ok(()) + } + pub fn mode_off(&mut self) -> Result<(), FieldOnError> { + self.mode = Mode::Off; + let _ = self.irq; + Ok(()) + } + pub async fn field_on(&self) -> Result<(), FieldOnError> { + Ok(()) + } + pub async fn field_off(&self) -> Result<(), Error> { + Ok(()) + } + pub fn cmd(&mut self, _cmd: Command) -> Result<(), Error> { + Ok(()) + } + pub fn regs(&mut self) -> Regs { + crate::regs::Regs::new(&mut self.iface) + } + pub fn irq_update(&mut self) -> Result<(), Error> { + Ok(()) + } + pub fn irq(&mut self, _irq: Interrupt) -> bool { + true + } + pub async fn wait_for_card(&self, _: WakeupConfig) -> Result<(), Error> { + Ok(()) + } +} + +pub enum Interrupt { + // required by iso14443a + Err1, + Par, + Crc, + Col, + Rxe, +} diff --git a/rnfc-st25r39/src/iso14443a.rs b/rnfc-st25r39/src/iso14443a.rs index 12b97d2..6a6abbb 100644 --- a/rnfc-st25r39/src/iso14443a.rs +++ b/rnfc-st25r39/src/iso14443a.rs @@ -1,10 +1,16 @@ use core::fmt::Debug; -use embassy_time::{with_timeout, Timer}; +use embassy_futures::yield_now; +use embassy_time::{with_timeout, Duration, Timer}; +use embedded_hal::digital::InputPin; +use embedded_hal_async::digital::Wait; use rnfc_traits::iso14443a_ll as ll; +use crate::commands::Command; use crate::fmt::Bytes; -use crate::*; +use crate::impls::{FieldOnError, Interrupt}; +use crate::interface::Interface; +use crate::St25r39; #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -125,7 +131,7 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 } }; - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] this.regs().corr_conf1().write(|w| { w.0 = 0x13; w.set_corr_s6(!is_anticoll); @@ -141,7 +147,7 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 // Disable Automatic Gain Control (AGC) for better detection of collisions if using Coherent Receiver w.set_agc_en(!is_anticoll); w.set_agc_m(true); // AGC operates during complete receive period - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] { w.set_agc6_3(true); // 0: AGC ratio 3 } @@ -152,23 +158,23 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 this.cmd(cmd)?; // Wait for tx ended - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] this.irq_wait(Interrupt::Txe).await?; // #[cfg(feature = "st25r3911b")] // this.irq_wait(|| this.regs().irq_main().read().expect("be readable").txe()).await?; // Wait for RX started - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] this.irq_wait_timeout(Interrupt::Rxs, Duration::from_millis(fwt_ms as _)) .await?; // #[cfg(feature = "st25r3911b")] // this.irq_wait_timeout( // || this.regs().irq_main().read().expect("be readable").rxs(), // Duration::from_millis(fwt_ms as _)); - #[cfg(feature = "st25r3911b")] + #[cfg(not(feature = "st25r3916"))] let _ = fwt_ms; - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] this.irq_wait_timeout(Interrupt::Rxs, Duration::from_millis(fwt_ms as _)) .await?; // #[cfg(feature = "st25r3911b")] @@ -224,7 +230,7 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 } let mut rx_bytes = this.regs().fifo_status1().read()? as usize; - #[cfg(not(feature = "st25r3911b"))] + #[cfg(feature = "st25r3916")] { rx_bytes |= (stat.fifo_b() as usize) << 8; } diff --git a/rnfc-st25r39/src/lib.rs b/rnfc-st25r39/src/lib.rs index 6f9e0c6..1d083db 100644 --- a/rnfc-st25r39/src/lib.rs +++ b/rnfc-st25r39/src/lib.rs @@ -5,41 +5,20 @@ // This must go FIRST so that other mods see its macros. mod fmt; +// no-chip-specified, maybe it'd be useful to have common api +// or support a mock, in case some tests to validate calculations? +#[cfg(any(feature = "st25r3911b", feature = "st25r3916"))] mod aat; pub mod commands; +pub mod impls; mod interface; pub mod iso14443a; +pub mod regs; -#[cfg(feature = "st25r3911b")] -mod lib_st25r3911b; -#[cfg(feature = "st25r3911b")] -mod regs_st25r3911b; -#[cfg(feature = "st25r3916")] -mod regs_st25r3916; -#[cfg(feature = "st25r3916")] -use self::regs_st25r3916::Regs; -#[cfg(feature = "st25r3916")] -mod lib_st25r3916; -pub mod regs { - #[doc(inline)] - #[cfg(feature = "st25r3911b")] - pub use super::regs_st25r3911b::*; - #[doc(inline)] - #[cfg(feature = "st25r3916")] - pub use super::regs_st25r3916::*; -} -pub use aat::AatConfig; -pub use commands::Command; -use embassy_futures::yield_now; -use embassy_time::Duration; -#[cfg(feature = "st25r3916")] -use embassy_time::Instant; use embedded_hal::digital::InputPin; use embedded_hal_async::digital::Wait; pub use interface::{I2cInterface, Interface, SpiInterface}; -const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); - #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Error { @@ -47,161 +26,6 @@ pub enum Error { Timeout, } -#[cfg(feature = "st25r3911b")] -use lib_st25r3911b::Interrupt; - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[allow(unused)] -#[cfg(not(feature = "st25r3911b"))] -enum Interrupt { - /// RFU interrupt - Rfu = 0, - /// automatic reception restart interrupt - RxRest = 1, - /// bit collision interrupt - Col = 2, - /// end of transmission interrupt - Txe = 3, - /// end of receive interrupt - Rxe = 4, - /// start of receive interrupt - Rxs = 5, - /// FIFO water level interrupt - Fwl = 6, - /// oscillator stable interrupt - Osc = 7, - /// initiator bit rate recognised interrupt - Nfct = 8, - /// minimum guard time expired interrupt - Cat = 9, - /// collision during RF collision avoidance interrupt - Cac = 10, - /// external field off interrupt - Eof = 11, - /// external field on interrupt - Eon = 12, - /// general purpose timer expired interrupt - Gpe = 13, - /// no-response timer expired interrupt - Nre = 14, - /// termination of direct command interrupt - Dct = 15, - /// wake-up due to capacitance measurement - Wcap = 16, - /// wake-up due to phase interrupt - Wph = 17, - /// wake-up due to amplitude interrupt - Wam = 18, - /// wake-up interrupt - Wt = 19, - /// hard framing error interrupt - Err1 = 20, - /// soft framing error interrupt - Err2 = 21, - /// parity error interrupt - Par = 22, - /// CRC error interrupt - Crc = 23, - /// 106kb/s Passive target state interrupt: Active - WuA = 24, - /// 106kb/s Passive target state interrupt: Active* - WuAX = 25, - /// RFU2 interrupt - Rfu2 = 26, - /// 212/424b/s Passive target interrupt: Active - WuF = 27, - /// RXE with an automatic response interrupt - RxePta = 28, - /// Anticollision done and Field On interrupt - Apon = 29, - /// Passive target slot number water level interrupt - SlWl = 30, - /// PPON2 Field on waiting Timer interrupt - Ppon2 = 31, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct WakeupConfig { - pub period: WakeupPeriod, - pub inductive_amplitude: Option, - pub inductive_phase: Option, - pub capacitive: Option, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct WakeupMethodConfig { - pub delta: u8, - pub reference: WakeupReference, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WakeupReference { - Manual(u8), - Automatic, - AutoAverage { include_irq_measurement: bool, weight: u8 }, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] - -pub enum WakeupPeriod { - /// 10ms - Ms10 = 0x00, - /// 20ms - Ms20 = 0x01, - /// 30ms - Ms30 = 0x02, - /// 40ms - Ms40 = 0x03, - /// 50ms - Ms50 = 0x04, - /// 60ms - Ms60 = 0x05, - /// 70ms - Ms70 = 0x06, - /// 80ms - Ms80 = 0x07, - /// 100ms - Ms100 = 0x10, - /// 200ms - Ms200 = 0x11, - /// 300ms - Ms300 = 0x12, - /// 400ms - Ms400 = 0x13, - /// 500ms - Ms500 = 0x14, - /// 600ms - Ms600 = 0x15, - /// 700ms - Ms700 = 0x16, - /// 800ms - Ms800 = 0x17, -} - -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FieldOnError { - /// There's some other device emitting its own field, so we shouldn't - /// turn ours on. - FieldCollision, - Interface(T), - Timeout, -} - -impl From> for FieldOnError { - fn from(val: Error) -> Self { - match val { - Error::Interface(e) => FieldOnError::Interface(e), - Error::Timeout => FieldOnError::Timeout, - } - } -} - #[derive(PartialEq, Eq, Clone, Copy)] enum Mode { Off, @@ -215,453 +39,3 @@ pub struct St25r39 { irqs: u32, mode: Mode, } - -#[cfg(not(feature = "st25r3911b"))] -impl St25r39 { - pub async fn new(iface: I, irq: IrqPin) -> Result> { - let mut this = Self { - iface, - irq, - irqs: 0, - mode: Mode::On, - }; - this.init().await?; - Ok(this) - } - - fn regs(&mut self) -> Regs { - Regs::new(&mut self.iface) - } - - fn cmd(&mut self, cmd: Command) -> Result<(), Error> { - self.iface.do_command(cmd as u8).map_err(Error::Interface) - } - - async fn cmd_wait(&mut self, cmd: Command) -> Result<(), Error> { - self.irq_clear()?; - self.cmd(cmd)?; - self.irq_wait(Interrupt::Dct).await - } - - async fn enable_osc(&mut self) -> Result<(), Error> { - trace!("Starting osc..."); - self.regs().op_control().write(|w| w.set_en(true))?; - while !self.regs().aux_display().read()?.osc_ok() {} - Ok(()) - } - - async fn init(&mut self) -> Result<(), Error> { - self.cmd(Command::SetDefault)?; - - self.regs().test_unk().write(|w| { - w.set_dis_overheat_prot(true); - })?; - - let id = self.regs().ic_identity().read()?; - trace!("ic_type = {:02x} ic_rev = {:02x}", id.ic_type().0, id.ic_rev().0); - - // Enable OSC - self.enable_osc().await?; - - // Measure vdd - trace!("measuring vdd..."); - let vdd_mv = self.measure_vdd().await?; - trace!("measure vdd result = {}mv", vdd_mv); - - let sup3v = vdd_mv < 3600; - if sup3v { - trace!("using 3v3 supply mode"); - } else { - trace!("using 5v supply mode"); - } - - self.regs().io_conf2().write(|w| { - w.set_sup_3v(sup3v); - })?; - - // Disable MCU_CLK - self.regs().io_conf1().write(|w| { - w.set_out_cl(regs::IoConf1OutCl::DISABLED); - w.set_lf_clk_off(true); - })?; - - // Enable minimum non-overlap - //self.regs().res_am_mod().write(|w| w.set_fa3_f(true))?; - - // Set ext field detect activ/deactiv thresholds - //self.regs().field_threshold_actv().write(|w| { - // w.set_trg(regs::FieldThresholdActvTrg::_105MV); - // w.set_rfe(regs::FieldThresholdActvRfe::_105MV); - //})?; - //self.regs().field_threshold_deactv().write(|w| { - // w.set_trg(regs::FieldThresholdDeactvTrg::_75MV); - // w.set_rfe(regs::FieldThresholdDeactvRfe::_75MV); - //})?; - - //self.regs().aux_mod().write(|w| { - // w.set_lm_ext(false); // Disable external Load Modulation - // w.set_lm_dri(true); // Enable internal Load Modulation - //})?; - - //self.regs().emd_sup_conf().write(|w| { - // w.set_rx_start_emv(true); - //})?; - - // AAT not in use - //self.regs().ant_tune_a().write_value(0x82)?; - //self.regs().ant_tune_b().write_value(0x82)?; - - self.regs().op_control().modify(|w| { - w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); - })?; - - // Adjust regulators - - // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. - self.regs().regulator_control().write(|w| w.set_reg_s(true))?; - self.regs().regulator_control().write(|w| w.set_reg_s(false))?; - - self.cmd_wait(Command::AdjustRegulators).await?; - - let res = self.regs().regulator_result().read()?.0; - trace!("reg result = {}", res); - - Ok(()) - } - - pub(crate) fn mode_off(&mut self) -> Result<(), Error> { - self.mode = Mode::Off; - self.cmd(Command::Stop)?; - // disable everything - self.regs().op_control().write(|_| {})?; - Ok(()) - } - - pub async fn measure_amplitude(&mut self) -> Result> { - self.cmd_wait(Command::MeasureAmplitude).await?; - self.regs().ad_result().read() - } - - pub async fn measure_phase(&mut self) -> Result> { - self.cmd_wait(Command::MeasurePhase).await?; - self.regs().ad_result().read() - } - - pub async fn measure_capacitance(&mut self) -> Result> { - self.cmd_wait(Command::MeasureCapacitance).await?; - self.regs().ad_result().read() - } - - pub async fn calibrate_capacitance(&mut self) -> Result> { - self.regs().cap_sensor_control().write(|w| { - // Clear Manual calibration values to enable automatic calibration mode - w.set_cs_mcal(0); - w.set_cs_g(0b01); // 6.5v/pF, highest one - })?; - - // Don't use `cmd_wait`, the irq only fires in Ready mode (op_control.en = 1). - // Instead, wait for cap_sensor_result.cs_cal_end - self.cmd(Command::CalibrateCSensor)?; - - let deadline = Instant::now() + DEFAULT_TIMEOUT; - - let res = loop { - if Instant::now() > deadline { - return Err(Error::Timeout); - } - - let res = self.regs().cap_sensor_result().read()?; - if res.cs_cal_err() { - panic!("Capacitive sensor calibration failed!"); - } - if res.cs_cal_end() { - break res; - } - - yield_now().await; - }; - Ok(res.cs_cal_val()) - } - - pub(crate) async fn mode_on(&mut self) -> Result<(), Error> { - self.mode = Mode::On; - self.enable_osc().await?; - - self.regs().op_control().modify(|w| { - w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); - })?; - self.regs().tx_driver().write(|w| { - w.set_d_res(3); - })?; - Ok(()) - } - - /// Change into wakeup mode, return immediately. - /// The IRQ pin will go high on wakeup. - pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { - self.mode_on().await?; - - self.mode = Mode::Wakeup; - debug!("Entering wakeup mode"); - - self.cmd(Command::Stop)?; - self.regs().op_control().write(|_| {})?; - self.regs().mode().write(|w| w.set_om(regs::ModeOm::INI_ISO14443A))?; - - let mut wtc = regs::WupTimerControl(0); - let mut irqs = 0; - - wtc.set_wur(config.period as u8 & 0x10 == 0); - wtc.set_wut(config.period as u8 & 0x0F); - - if let Some(m) = config.inductive_amplitude { - let mut conf = regs::AmplitudeMeasureConf(0); - conf.set_am_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().amplitude_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_amplitude().await?; - self.regs().amplitude_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_amplitude().await?; - self.regs().amplitude_measure_ref().write_value(val)?; - conf.set_am_ae(true); - conf.set_am_aam(include_irq_measurement); - conf.set_am_aew(weight); - } - } - self.regs().amplitude_measure_conf().write_value(conf)?; - wtc.set_wam(true); - irqs |= 1 << Interrupt::Wam as u32; - } - if let Some(m) = config.inductive_phase { - let mut conf = regs::PhaseMeasureConf(0); - conf.set_pm_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().phase_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_phase().await?; - self.regs().phase_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_phase().await?; - self.regs().phase_measure_ref().write_value(val)?; - conf.set_pm_ae(true); - conf.set_pm_aam(include_irq_measurement); - conf.set_pm_aew(weight); - } - } - self.regs().phase_measure_conf().write_value(conf)?; - wtc.set_wph(true); - irqs |= 1 << Interrupt::Wph as u32; - } - if let Some(m) = config.capacitive { - debug!("capacitance calibrating..."); - let val = self.calibrate_capacitance().await?; - info!("capacitance calibrated: {}", val); - - let mut conf = regs::CapacitanceMeasureConf(0); - conf.set_cm_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().capacitance_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_capacitance().await?; - info!("Measured: {}", val); - self.regs().capacitance_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_capacitance().await?; - info!("Measured: {}", val); - self.regs().capacitance_measure_ref().write_value(val)?; - conf.set_cm_ae(true); - conf.set_cm_aam(include_irq_measurement); - conf.set_cm_aew(weight); - } - } - self.regs().capacitance_measure_conf().write_value(conf)?; - wtc.set_wcap(true); - irqs |= 1 << Interrupt::Wcap as u32; - } - - self.irq_clear()?; - - self.regs().wup_timer_control().write_value(wtc)?; - self.regs().op_control().write(|w| w.set_wu(true))?; - self.irq_set_mask(!irqs)?; - - debug!("Entered wakeup mode, waiting for pin IRQ"); - self.irq.wait_for_high().await.unwrap(); - debug!("got pin IRQ!"); - - Ok(()) - } - - async fn field_on(&mut self) -> Result<(), FieldOnError> { - self.regs().mode().write(|w| { - w.set_om(regs::ModeOm::INI_ISO14443A); - w.set_tr_am(false); // use OOK - })?; - self.regs().tx_driver().write(|w| { - w.set_am_mod(regs::TxDriverAmMod::_12PERCENT); - })?; - self.regs().aux_mod().write(|w| { - w.set_lm_dri(true); // Enable internal Load Modulation - w.set_dis_reg_am(false); // Enable regulator-based AM - w.set_res_am(false); - })?; - - // Default over/under shoot protiection - self.regs().overshoot_conf1().write_value(0x40.into())?; - self.regs().overshoot_conf2().write_value(0x03.into())?; - self.regs().undershoot_conf1().write_value(0x40.into())?; - self.regs().undershoot_conf2().write_value(0x03.into())?; - - self.regs().aux().write(|w| { - w.set_dis_corr(false); // Enable correlator reception - w.set_nfc_n(0); // todo this changes - })?; - /* - self.regs().rx_conf1().write_value(0x08.into())?; - self.regs().rx_conf2().write_value(0x2D.into())?; - self.regs().rx_conf3().write_value(0x00.into())?; - self.regs().rx_conf4().write_value(0x00.into())?; - self.regs().corr_conf1().write_value(0x51.into())?; - self.regs().corr_conf2().write_value(0x00.into())?; - */ - - self.regs().bit_rate().write(|w| { - w.set_rxrate(regs::BitRateE::_106); - w.set_txrate(regs::BitRateE::_106); - })?; - - // defaults - self.regs().iso14443a_nfc().write(|_| {})?; - - // Field ON - - // GT is done by software - self.regs().field_on_gt().write_value(0)?; - - self.irq_clear()?; // clear - self.cmd(Command::InitialRfCollision)?; - - loop { - if self.irq(Interrupt::Cac) { - return Err(FieldOnError::FieldCollision); - } - if self.irq(Interrupt::Apon) { - break; - } - - self.irq_update()?; - } - - self.regs().op_control().modify(|w| { - w.set_tx_en(true); - w.set_rx_en(true); - })?; - - Ok(()) - } - - async fn measure_vdd(&mut self) -> Result> { - self.regs() - .regulator_control() - .write(|w| w.set_mpsv(regs::RegulatorControlMpsv::VDD))?; - self.cmd_wait(Command::MeasureVdd).await?; - let res = self.regs().ad_result().read()? as u32; - - // result is in units of 23.4mV - Ok((res * 234 + 5) / 10) - } - - // ======================= - // irq stuff - - fn irq(&self, irq: Interrupt) -> bool { - return (self.irqs & (1 << (irq as u8))) != 0; - } - - async fn irq_wait_timeout(&mut self, irq: Interrupt, timeout: Duration) -> Result<(), Error> { - let deadline = Instant::now() + timeout; - self.irq_update()?; - while !self.irq(irq) { - if Instant::now() > deadline { - return Err(Error::Timeout); - } - yield_now().await; - self.irq_update()?; - } - Ok(()) - } - - async fn irq_wait(&mut self, irq: Interrupt) -> Result<(), Error> { - self.irq_wait_timeout(irq, DEFAULT_TIMEOUT).await - } - - fn irq_update(&mut self) -> Result<(), Error> { - for i in 0..4 { - self.irqs |= (self.regs().irq_main(i).read()? as u32) << (i * 8); - } - Ok(()) - } - - fn irq_clear(&mut self) -> Result<(), Error> { - self.irq_update()?; - self.irqs = 0; - Ok(()) - } - - fn irq_set_mask(&mut self, mask: u32) -> Result<(), Error> { - for i in 0..4 { - self.regs().irq_mask(i).write_value((mask >> (i * 8)) as u8)?; - } - Ok(()) - } - - pub fn raw(&mut self) -> Raw<'_, I, IrqPin> { - Raw { inner: self } - } -} - -pub struct Raw<'a, I: Interface, IrqPin: InputPin + Wait> { - inner: &'a mut St25r39, -} - -impl<'a, I: Interface, IrqPin: InputPin + Wait> Raw<'a, I, IrqPin> { - pub async fn field_on(&mut self) -> Result<(), FieldOnError> { - self.inner.mode_on().await?; - self.inner.field_on().await?; - Ok(()) - } - pub async fn field_off(&mut self) -> Result<(), Error> { - self.inner.mode_off()?; - Ok(()) - } - - #[cfg(not(feature = "st25r3911b"))] - pub async fn driver_hi_z(&mut self) -> Result<(), Error> { - self.inner.mode_off()?; - self.inner.regs().tx_driver().write(|w| { - w.set_d_res(15); // hi-z - })?; - - Ok(()) - } -} diff --git a/rnfc-st25r39/src/lib_st25r3916.rs b/rnfc-st25r39/src/lib_st25r3916.rs deleted file mode 100644 index 3f2d6a6..0000000 --- a/rnfc-st25r39/src/lib_st25r3916.rs +++ /dev/null @@ -1,6 +0,0 @@ -// TODO - placeholder if "approach 2" described in PR is preferred, -// then specific for st25r3916 parts from "lib" could be moved here -// which would allow to align the changes between chips better, -// and possibly remove substantial amount of "cfg!" checks -// See also discussion on Matrix -// https://matrix.to/#/!YoLPkieCYHGzdjUhOK:matrix.org/$jLJeWLyptxa4kbQcl-j2hKoha9DeI_Ta6m_X0t2wmhw diff --git a/rnfc-st25r39/src/regs/mod.rs b/rnfc-st25r39/src/regs/mod.rs new file mode 100644 index 0000000..e32b24c --- /dev/null +++ b/rnfc-st25r39/src/regs/mod.rs @@ -0,0 +1,67 @@ +#[cfg(feature = "st25r3911b")] +mod regs_st25r3911b; + +#[cfg(feature = "st25r3911b")] +pub use regs_st25r3911b::*; + +#[cfg(feature = "st25r3916")] +mod regs_st25r3916; +#[cfg(feature = "st25r3916")] +pub use regs_st25r3916::*; + +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +mod stub; +use core::marker::PhantomData; + +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +pub use stub::*; + +use crate::interface::Interface; +use crate::Error; + +// TODO: if this api is set, then maybe one somehow could remove some bolierplate generation for regs +pub struct Reg<'a, I: Interface, T: Copy> { + addr: u8, + iface: &'a mut I, + phantom: PhantomData<&'a mut T>, +} + +impl<'a, I: Interface, T: Copy + Into + From> Reg<'a, I, T> { + pub fn new(iface: &'a mut I, addr: u8) -> Self { + Self { + iface, + addr, + phantom: PhantomData, + } + } + + pub fn read(&mut self) -> Result> { + Ok(self.iface.read_reg(self.addr).map_err(Error::Interface)?.into()) + } + + pub fn write_value(&mut self, val: T) -> Result<(), Error> { + self.iface.write_reg(self.addr, val.into()).map_err(Error::Interface) + } + + pub fn modify(&mut self, f: impl FnOnce(&mut T) -> R) -> Result> { + let mut val = self.read()?; + let res = f(&mut val); + self.write_value(val)?; + Ok(res) + } +} + +impl<'a, I: Interface, T: Default + Copy + Into + From> Reg<'a, I, T> { + pub fn write(&mut self, f: impl FnOnce(&mut T) -> R) -> Result> { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val)?; + Ok(res) + } +} + +// just for stub +#[cfg(not(any(feature = "st25r3911b", feature = "st25r3916")))] +pub struct Regs<'a, I: Interface> { + iface: &'a mut I, +} diff --git a/rnfc-st25r39/src/regs_st25r3911b.rs b/rnfc-st25r39/src/regs/regs_st25r3911b.rs similarity index 99% rename from rnfc-st25r39/src/regs_st25r3911b.rs rename to rnfc-st25r39/src/regs/regs_st25r3911b.rs index 6b676fa..68fa643 100644 --- a/rnfc-st25r39/src/regs_st25r3911b.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3911b.rs @@ -2,8 +2,7 @@ use core::marker::PhantomData; -use super::Interface; -use crate::Error; +use crate::{Error, Interface}; pub struct Reg<'a, I: Interface, T: Copy> { addr: u8, diff --git a/rnfc-st25r39/src/regs_st25r3916.rs b/rnfc-st25r39/src/regs/regs_st25r3916.rs similarity index 99% rename from rnfc-st25r39/src/regs_st25r3916.rs rename to rnfc-st25r39/src/regs/regs_st25r3916.rs index 7746439..3efdb61 100644 --- a/rnfc-st25r39/src/regs_st25r3916.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3916.rs @@ -2,8 +2,7 @@ use core::marker::PhantomData; -use super::Interface; -use crate::Error; +use crate::{Error, Interface}; pub struct Reg<'a, I: Interface, T: Copy> { addr: u8, diff --git a/rnfc-st25r39/src/regs/stub.rs b/rnfc-st25r39/src/regs/stub.rs new file mode 100644 index 0000000..7e765fd --- /dev/null +++ b/rnfc-st25r39/src/regs/stub.rs @@ -0,0 +1,310 @@ +use super::{Reg, Regs}; +use crate::Interface; + +impl<'a, I: Interface> Regs<'a, I> { + pub fn new(iface: &'a mut I) -> Self { + Self { iface } + } + + /// IO configuration register 1 + pub fn io_conf1(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 0) + } + pub fn aux(&mut self) -> Reg<'_, I, Aux> { + Reg::new(self.iface, 1) + } + pub fn rx_conf2(&mut self) -> Reg<'_, I, RxConf2> { + Reg::new(self.iface, 0) + } + pub fn num_tx_bytes2(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 0) + } + pub fn num_tx_bytes1(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 0) + } + pub fn fifo_status1(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 0) + } + pub fn fifo_status2(&mut self) -> Reg<'_, I, FifoStatus2> { + Reg::new(self.iface, 0) + } + pub fn iso14443a_nfc(&mut self) -> Reg<'_, I, Iso14443ANfc> { + Reg::new(self.iface, 0) + } + pub fn collision_status(&mut self) -> Reg<'_, I, CollisionStatus> { + Reg::new(self.iface, 0) + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Aux(pub u8); +impl Aux { + pub const fn nfc_n(&self) -> u8 { + let val = (self.0 >> 0_usize) & 2; + val as u8 + } + pub fn set_nfc_n(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val as u8) & 2) << 0_usize; + } + pub const fn rx_tol(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_rx_tol(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn ook_hr(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_ook_hr(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn en_fd(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_en_fd(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn tr_am(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_tr_am(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn crc_2_fifo(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_crc_2_fifo(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn no_crc_rx(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_no_crc_rx(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for Aux { + fn default() -> Aux { + Aux(0) + } +} +impl From for Aux { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Aux) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxConf2(pub u8); +impl RxConf2 { + pub const fn pmix_cl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_pmix_cl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn sqm_dyn(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_sqm_dyn(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn agc_alg(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_agc_alg(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn agc_m(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_agc_m(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn agc_en(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_agc_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn lf_en(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_lf_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn lf_op(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_lf_op(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn rx_lp(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_rx_lp(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for RxConf2 { + fn default() -> RxConf2 { + RxConf2(0) + } +} +impl From for RxConf2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf2) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct FifoStatus2(pub u8); +impl FifoStatus2 { + pub const fn np_lb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn fifo_lb(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 + } + pub const fn fifo_ovr(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub const fn fifo_unf(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } +} +impl Default for FifoStatus2 { + fn default() -> FifoStatus2 { + FifoStatus2(0) + } +} +impl From for FifoStatus2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: FifoStatus2) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Iso14443ANfc(pub u8); +impl Iso14443ANfc { + pub const fn antcl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_antcl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn p_len(&self) -> u8 { + let val = (self.0 >> 1_usize) & 4; + val as u8 + } + pub fn set_p_len(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 1_usize)) | ((val as u8) & 4) << 1_usize; + } + pub const fn nfc_f0(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_nfc_f0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn no_rx_par(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_no_rx_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn no_tx_par(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_no_tx_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for Iso14443ANfc { + fn default() -> Iso14443ANfc { + Iso14443ANfc(0) + } +} +impl From for Iso14443ANfc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: Iso14443ANfc) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CollisionStatus(pub u8); +impl CollisionStatus { + pub const fn c_pb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub const fn c_bit(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 + } + pub const fn c_byte(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } +} +impl Default for CollisionStatus { + fn default() -> CollisionStatus { + CollisionStatus(0) + } +} +impl From for CollisionStatus { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: CollisionStatus) -> u8 { + val.0 + } +} From 33ab5f5f16466c8438edf2fd5d5543624e99c7ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Tue, 18 Feb 2025 22:31:44 +0100 Subject: [PATCH 3/8] regs: small yaml files fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Królczyk --- .../src/yaml-regmaps/regs-st25r3911b.yaml | 785 +++++++++--------- .../src/yaml-regmaps/regs-st25r3916.yaml | 2 +- 2 files changed, 403 insertions(+), 384 deletions(-) diff --git a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml index 142b595..6bc8d8c 100644 --- a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml +++ b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml @@ -1,360 +1,359 @@ ---- block/REGS: items: - - name: IO_CONF1 - byte_offset: 0 - bit_size: 8 - access: RW - description: IO configuration register 1 - fieldset: IO_CONF1 - - name: IO_CONF2 - byte_offset: 1 - bit_size: 8 - access: RW - description: IO configuration register 2 - fieldset: IO_CONF2 - - name: OP_CONTROL - byte_offset: 2 - bit_size: 8 - access: RW - description: Operation control register - fieldset: OP_CONTROL - - name: MODE - byte_offset: 3 - bit_size: 8 - access: RW - description: Mode definition register - fieldset: MODE - - name: BIT_RATE - byte_offset: 4 - bit_size: 8 - access: RW - description: Bit rate definition register - fieldset: BIT_RATE - - name: ISO14443A_NFC - byte_offset: 5 - bit_size: 8 - access: RW - description: ISO14443A and NFC 106kb/s settings register - fieldset: ISO14443A_NFC - - name: ISO14443B_1 - byte_offset: 6 - bit_size: 8 - access: RW - description: ISO14443B settings register 1 - fieldset: ISO14443B_1 - - name: ISO14443B_2 - byte_offset: 7 - bit_size: 8 - access: RW - description: ISO14443B and FeliCa settings register - fieldset: ISO14443B_2 - - name: STREAM_MODE - byte_offset: 8 - bit_size: 8 - access: RW - description: Stream mode definition register - fieldset: STREAM_MODE - - name: AUX - byte_offset: 9 - bit_size: 8 - access: RW - description: Auxiliary definition register - fieldset: AUX - - name: RX_CONF1 - byte_offset: 10 - bit_size: 8 - access: RW - description: Receiver configuration register 1 - fieldset: RX_CONF1 - - name: RX_CONF2 - byte_offset: 11 - bit_size: 8 - access: RW - description: Receiver configuration register 2 - fieldset: RX_CONF2 - - name: RX_CONF3 - byte_offset: 12 - bit_size: 8 - access: RW - description: Receiver configuration register 3 - fieldset: RX_CONF3 - - name: RX_CONF4 - byte_offset: 13 - bit_size: 8 - access: RW - description: Receiver configuration register 4 - fieldset: RX_CONF4 - - name: MASK_RX_TIMER - byte_offset: 14 - bit_size: 8 - access: RW - description: Mask receive timer register - fieldset: MASK_RX_TIMER - - name: NO_RESPONSE_TIMER1 - byte_offset: 15 - bit_size: 8 - access: RW - description: No-response timer register 1 - fieldset: NO_RESPONSE_TIMER1 - - name: NO_RESPONSE_TIMER2 - byte_offset: 16 - bit_size: 8 - access: RW - description: No-response timer register 2 - - name: GPT_NRT_CTRL - byte_offset: 17 - bit_size: 8 - access: RW - description: General purpose and no-response timer control register - fieldset: GPT_NRT_CTRL - - name: GPT1 - byte_offset: 18 - bit_size: 8 - access: RW - description: General purpose timer register 1 - - name: GPT2 - byte_offset: 19 - bit_size: 8 - access: RW - description: General purpose timer register 2 - - name: IRQ_MASK_MAIN - byte_offset: 20 - bit_size: 8 - access: RW - description: Main interrupt register - fieldset: IRQ_MASK_MAIN - - name: IRQ_MASK_TIMER_NFC - byte_offset: 21 - bit_size: 8 - access: RW - description: Mask timer and NFC interrupt register - fieldset: IRQ_MASK_TIMER_NFC - - name: IRQ_MASK_ERROR_WUP - byte_offset: 22 - bit_size: 8 - access: RW - description: Mask error and wake-up interrupt register - fieldset: IRQ_MASK_ERROR_WUP - - name: IRQ_MAIN - byte_offset: 23 - bit_size: 8 - access: R - description: Main interrupt register - fieldset: IRQ_MAIN - - name: IRQ_TIMER_NFC - byte_offset: 24 - bit_size: 8 - access: R - description: Mask timer and NFC interrupt register - fieldset: IRQ_TIMER_NFC - - name: IRQ_ERROR_WUP - byte_offset: 25 - bit_size: 8 - access: R - description: Error and wake-up interrupt register - - name: FIFO_STATUS1 - byte_offset: 26 - bit_size: 8 - access: R - description: FIFO status register 1 - - name: FIFO_STATUS2 - byte_offset: 27 - bit_size: 8 - access: R - description: FIFO status register 2 - fieldset: FIFO_STATUS2 - - name: COLLISION_STATUS - byte_offset: 28 - bit_size: 8 - access: R - description: Collision display register - fieldset: COLLISION_STATUS - - name: NUM_TX_BYTES1 - byte_offset: 29 - bit_size: 8 - access: RW - description: Number of transmitted bytes register 1 - - name: NUM_TX_BYTES2 - byte_offset: 30 - bit_size: 8 - access: RW - description: Number of transmitted bytes register 2 - fieldset: NUM_TX_BYTES2 - - name: NFCIP1_BIT_RATE_DISP - byte_offset: 31 - bit_size: 8 - access: R - description: NFCIP bit rate detection display register - fieldset: NFCIP1_BIT_RATE_DISP - - name: AD_CONV_RESULT - byte_offset: 32 - bit_size: 8 - access: R - description: A/D converter output register - - name: ANT_TUNE_CTRL - byte_offset: 33 - bit_size: 8 - access: RW - description: Antenna calibration control register - fieldset: ANT_TUNE_CTRL - - name: ANT_TUNE_TARGET - byte_offset: 34 - bit_size: 8 - access: RW - description: Antenna calibration target register - - name: ANT_TUNE_DISP - byte_offset: 35 - bit_size: 8 - access: R - description: Antenna calibration display register - fieldset: ANT_TUNE_DISP - - name: AM_MOD_DEPTH_CTRL - byte_offset: 36 - bit_size: 8 - access: RW - description: AM modulation depth control register - fieldset: AM_MOD_DEPTH_CTRL - - name: AM_MOD_DEPTH_DISP - byte_offset: 37 - bit_size: 8 - access: R - description: AM modulation depth display register - - name: RFO_AM_MOD_LEVEL_DEF - byte_offset: 38 - bit_size: 8 - access: RW - description: RFO AM modulated level definition register - fieldset: RFO_AM_LEVEL_DEF - - name: RFO_NORMAL_LEVEL_DEF - byte_offset: 39 - bit_size: 8 - access: RW - description: RFO normal level definition register - fieldset: RFO_AM_LEVEL_DEF - - name: EXT_FIELD_DET_THR - byte_offset: 41 - bit_size: 8 - access: RW - description: External field detector threshold register - fieldset: EXT_FIELD_DET_THR - - name: REGULATOR_VOLT_CONTROL - byte_offset: 42 - bit_size: 8 - access: RW - description: Regulator voltage control register - fieldset: REGULATOR_VOLT_CONTROL - - name: REGULATOR_AND_TIM_DISP - byte_offset: 43 - bit_size: 8 - access: R - description: Regulator and timer display register - fieldset: REGULATOR_AND_TIM_DISP - - name: RSSI_RESULT - byte_offset: 44 - bit_size: 8 - access: R - description: RSSI display register - fieldset: RSSI_RESULT - - name: GAIN_REDU_STATE - byte_offset: 45 - bit_size: 8 - access: R - description: Gain reduction state register - fieldset: GAIN_REDU_STATE - - name: CAP_SENSOR_CONTROL - byte_offset: 46 - bit_size: 8 - access: RW - description: Capacitive sensor control register - fieldset: CAP_SENSOR_CONTROL - - name: CAP_SENSOR_DISP - byte_offset: 47 - bit_size: 8 - access: R - description: Capacitive sensor display register - fieldset: CAP_SENSOR_DISP - - name: AUX_DISPLAY - byte_offset: 48 - bit_size: 8 - access: R - description: Auxiliary display register - fieldset: AUX_DISPLAY - - name: WUP_TIMER_CONTROL - byte_offset: 49 - bit_size: 8 - access: RW - description: Wake-up timer control register - fieldset: WUP_TIMER_CONTROL - - name: AMPLITUDE_MEASURE_CONF - byte_offset: 50 - bit_size: 8 - access: RW - description: Amplitude measurement configuration register - fieldset: AMPLITUDE_MEASURE_CONF - - name: AMPLITUDE_MEASURE_REF - byte_offset: 51 - bit_size: 8 - access: RW - description: Amplitude measurement reference register - - name: AMPLITUDE_MEASURE_AUTO_AVG_DISP - byte_offset: 52 - bit_size: 8 - access: R - description: Amplitude measurement auto-averaging display - - name: AMPLITUDE_MEASURE_DISP - byte_offset: 53 - bit_size: 8 - access: R - description: Amplitude measurement display - - name: PHASE_MEASURE_CONF - byte_offset: 54 - bit_size: 8 - access: RW - description: Phase measurement configuration - fieldset: PHASE_MEASURE_CONF - - name: PHASE_MEASURE_REF - byte_offset: 55 - bit_size: 8 - access: RW - description: Phase measurement reference - - name: PHASE_MEASURE_AUTO_AVG_DISP - byte_offset: 56 - bit_size: 8 - access: R - description: Phase measurement auto-averaging display - - name: PHASE_MEASURE_DISP - byte_offset: 57 - bit_size: 8 - access: R - description: Phase measurement display - - name: CAPACITANCE_MEASURE_CONF - byte_offset: 58 - bit_size: 8 - access: RW - description: Capacitance measurement configuration - fieldset: CAPACITANCE_MEASURE_CONF - - name: CAPACITANCE_MEASURE_REF - byte_offset: 59 - bit_size: 8 - access: RW - description: Capacitance measurement reference - - name: CAPACITANCE_MEASURE_AUTO_AVG_DISP - byte_offset: 60 - bit_size: 8 - access: R - description: Capacitance measurement auto-averaging display - - name: CAPACITANCE_MEASURE_DISP - byte_offset: 61 - bit_size: 8 - access: R - description: Capacitance measurement display - - name: IC_IDENTITY - byte_offset: 63 - bit_size: 8 - access: R - description: IC identity register - fieldset: IC_IDENTITY + - name: IO_CONF1 + byte_offset: 0 + bit_size: 8 + access: ReadWrite + description: IO configuration register 1 + fieldset: IO_CONF1 + - name: IO_CONF2 + byte_offset: 1 + bit_size: 8 + access: ReadWrite + description: IO configuration register 2 + fieldset: IO_CONF2 + - name: OP_CONTROL + byte_offset: 2 + bit_size: 8 + access: ReadWrite + description: Operation control register + fieldset: OP_CONTROL + - name: MODE + byte_offset: 3 + bit_size: 8 + access: ReadWrite + description: Mode definition register + fieldset: MODE + - name: BIT_RATE + byte_offset: 4 + bit_size: 8 + access: ReadWrite + description: Bit rate definition register + fieldset: BIT_RATE + - name: ISO14443A_NFC + byte_offset: 5 + bit_size: 8 + access: ReadWrite + description: ISO14443A and NFC 106kb/s settings register + fieldset: ISO14443A_NFC + - name: ISO14443B_1 + byte_offset: 6 + bit_size: 8 + access: ReadWrite + description: ISO14443B settings register 1 + fieldset: ISO14443B_1 + - name: ISO14443B_2 + byte_offset: 7 + bit_size: 8 + access: ReadWrite + description: ISO14443B and FeliCa settings register + fieldset: ISO14443B_2 + - name: STREAM_MODE + byte_offset: 8 + bit_size: 8 + access: ReadWrite + description: Stream mode definition register + fieldset: STREAM_MODE + - name: AUX + byte_offset: 9 + bit_size: 8 + access: ReadWrite + description: Auxiliary definition register + fieldset: AUX + - name: RX_CONF1 + byte_offset: 10 + bit_size: 8 + access: ReadWrite + description: Receiver configuration register 1 + fieldset: RX_CONF1 + - name: RX_CONF2 + byte_offset: 11 + bit_size: 8 + access: ReadWrite + description: Receiver configuration register 2 + fieldset: RX_CONF2 + - name: RX_CONF3 + byte_offset: 12 + bit_size: 8 + access: ReadWrite + description: Receiver configuration register 3 + fieldset: RX_CONF3 + - name: RX_CONF4 + byte_offset: 13 + bit_size: 8 + access: ReadWrite + description: Receiver configuration register 4 + fieldset: RX_CONF4 + - name: MASK_RX_TIMER + byte_offset: 14 + bit_size: 8 + access: ReadWrite + description: Mask receive timer register + fieldset: MASK_RX_TIMER + - name: NO_RESPONSE_TIMER1 + byte_offset: 15 + bit_size: 8 + access: ReadWrite + description: No-response timer register 1 + fieldset: NO_RESPONSE_TIMER1 + - name: NO_RESPONSE_TIMER2 + byte_offset: 16 + bit_size: 8 + access: ReadWrite + description: No-response timer register 2 + - name: GPT_NRT_CTRL + byte_offset: 17 + bit_size: 8 + access: ReadWrite + description: General purpose and no-response timer control register + fieldset: GPT_NRT_CTRL + - name: GPT1 + byte_offset: 18 + bit_size: 8 + access: ReadWrite + description: General purpose timer register 1 + - name: GPT2 + byte_offset: 19 + bit_size: 8 + access: ReadWrite + description: General purpose timer register 2 + - name: IRQ_MASK_MAIN + byte_offset: 20 + bit_size: 8 + access: ReadWrite + description: Main interrupt register + fieldset: IRQ_MASK_MAIN + - name: IRQ_MASK_TIMER_NFC + byte_offset: 21 + bit_size: 8 + access: ReadWrite + description: Mask timer and NFC interrupt register + fieldset: IRQ_MASK_TIMER_NFC + - name: IRQ_MASK_ERROR_WUP + byte_offset: 22 + bit_size: 8 + access: ReadWrite + description: Mask error and wake-up interrupt register + fieldset: IRQ_MASK_ERROR_WUP + - name: IRQ_MAIN + byte_offset: 23 + bit_size: 8 + access: Read + description: Main interrupt register + fieldset: IRQ_MAIN + - name: IRQ_TIMER_NFC + byte_offset: 24 + bit_size: 8 + access: Read + description: Mask timer and NFC interrupt register + fieldset: IRQ_TIMER_NFC + - name: IRQ_ERROR_WUP + byte_offset: 25 + bit_size: 8 + access: Read + description: Error and wake-up interrupt register + - name: FIFO_STATUS1 + byte_offset: 26 + bit_size: 8 + access: Read + description: FIFO status register 1 + - name: FIFO_STATUS2 + byte_offset: 27 + bit_size: 8 + access: Read + description: FIFO status register 2 + fieldset: FIFO_STATUS2 + - name: COLLISION_STATUS + byte_offset: 28 + bit_size: 8 + access: Read + description: Collision display register + fieldset: COLLISION_STATUS + - name: NUM_TX_BYTES1 + byte_offset: 29 + bit_size: 8 + access: ReadWrite + description: Number of transmitted bytes register 1 + - name: NUM_TX_BYTES2 + byte_offset: 30 + bit_size: 8 + access: ReadWrite + description: Number of transmitted bytes register 2 + fieldset: NUM_TX_BYTES2 + - name: NFCIP1_BIT_RATE_DISP + byte_offset: 31 + bit_size: 8 + access: Read + description: NFCIP bit rate detection display register + fieldset: NFCIP1_BIT_RATE_DISP + - name: AD_CONV_RESULT + byte_offset: 32 + bit_size: 8 + access: Read + description: A/D converter output register + - name: ANT_TUNE_CTRL + byte_offset: 33 + bit_size: 8 + access: ReadWrite + description: Antenna calibration control register + fieldset: ANT_TUNE_CTRL + - name: ANT_TUNE_TARGET + byte_offset: 34 + bit_size: 8 + access: ReadWrite + description: Antenna calibration target register + - name: ANT_TUNE_DISP + byte_offset: 35 + bit_size: 8 + access: Read + description: Antenna calibration display register + fieldset: ANT_TUNE_DISP + - name: AM_MOD_DEPTH_CTRL + byte_offset: 36 + bit_size: 8 + access: ReadWrite + description: AM modulation depth control register + fieldset: AM_MOD_DEPTH_CTRL + - name: AM_MOD_DEPTH_DISP + byte_offset: 37 + bit_size: 8 + access: Read + description: AM modulation depth display register + - name: RFO_AM_MOD_LEVEL_DEF + byte_offset: 38 + bit_size: 8 + access: ReadWrite + description: RFO AM modulated level definition register + fieldset: RFO_AM_LEVEL_DEF + - name: RFO_NORMAL_LEVEL_DEF + byte_offset: 39 + bit_size: 8 + access: ReadWrite + description: RFO normal level definition register + fieldset: RFO_AM_LEVEL_DEF + - name: EXT_FIELD_DET_THR + byte_offset: 41 + bit_size: 8 + access: ReadWrite + description: External field detector threshold register + fieldset: EXT_FIELD_DET_THR + - name: REGULATOR_VOLT_CONTROL + byte_offset: 42 + bit_size: 8 + access: ReadWrite + description: Regulator voltage control register + fieldset: REGULATOR_VOLT_CONTROL + - name: REGULATOR_AND_TIM_DISP + byte_offset: 43 + bit_size: 8 + access: Read + description: Regulator and timer display register + fieldset: REGULATOR_AND_TIM_DISP + - name: RSSI_RESULT + byte_offset: 44 + bit_size: 8 + access: Read + description: RSSI display register + fieldset: RSSI_RESULT + - name: GAIN_REDU_STATE + byte_offset: 45 + bit_size: 8 + access: Read + description: Gain reduction state register + fieldset: GAIN_REDU_STATE + - name: CAP_SENSOR_CONTROL + byte_offset: 46 + bit_size: 8 + access: ReadWrite + description: Capacitive sensor control register + fieldset: CAP_SENSOR_CONTROL + - name: CAP_SENSOR_DISP + byte_offset: 47 + bit_size: 8 + access: Read + description: Capacitive sensor display register + fieldset: CAP_SENSOR_DISP + - name: AUX_DISPLAY + byte_offset: 48 + bit_size: 8 + access: Read + description: Auxiliary display register + fieldset: AUX_DISPLAY + - name: WUP_TIMER_CONTROL + byte_offset: 49 + bit_size: 8 + access: ReadWrite + description: Wake-up timer control register + fieldset: WUP_TIMER_CONTROL + - name: AMPLITUDE_MEASURE_CONF + byte_offset: 50 + bit_size: 8 + access: ReadWrite + description: Amplitude measurement configuration register + fieldset: AMPLITUDE_MEASURE_CONF + - name: AMPLITUDE_MEASURE_REF + byte_offset: 51 + bit_size: 8 + access: ReadWrite + description: Amplitude measurement reference register + - name: AMPLITUDE_MEASURE_AUTO_AVG_DISP + byte_offset: 52 + bit_size: 8 + access: Read + description: Amplitude measurement auto-averaging display + - name: AMPLITUDE_MEASURE_DISP + byte_offset: 53 + bit_size: 8 + access: Read + description: Amplitude measurement display + - name: PHASE_MEASURE_CONF + byte_offset: 54 + bit_size: 8 + access: ReadWrite + description: Phase measurement configuration + fieldset: PHASE_MEASURE_CONF + - name: PHASE_MEASURE_REF + byte_offset: 55 + bit_size: 8 + access: ReadWrite + description: Phase measurement reference + - name: PHASE_MEASURE_AUTO_AVG_DISP + byte_offset: 56 + bit_size: 8 + access: Read + description: Phase measurement auto-averaging display + - name: PHASE_MEASURE_DISP + byte_offset: 57 + bit_size: 8 + access: Read + description: Phase measurement display + - name: CAPACITANCE_MEASURE_CONF + byte_offset: 58 + bit_size: 8 + access: ReadWrite + description: Capacitance measurement configuration + fieldset: CAPACITANCE_MEASURE_CONF + - name: CAPACITANCE_MEASURE_REF + byte_offset: 59 + bit_size: 8 + access: ReadWrite + description: Capacitance measurement reference + - name: CAPACITANCE_MEASURE_AUTO_AVG_DISP + byte_offset: 60 + bit_size: 8 + access: Read + description: Capacitance measurement auto-averaging display + - name: CAPACITANCE_MEASURE_DISP + byte_offset: 61 + bit_size: 8 + access: Read + description: Capacitance measurement display + - name: IC_IDENTITY + byte_offset: 63 + bit_size: 8 + access: Read + description: IC identity register + fieldset: IC_IDENTITY fieldset/IO_CONF1: bit_size: 8 fields: @@ -945,12 +944,12 @@ fieldset/EXT_FIELD_DET_THR: bit_offset: 0 bit_size: 4 default: 3 - enum: THRESHOLD_DEF + enum: THRESHOLD_DEF_2 - name: trg_l bit_offset: 4 bit_size: 3 default: 3 - enum: THRESHOLD_DEF + enum: THRESHOLD_DEF_1 fieldset/REGULATOR_VOLT_CONTROL: bit_size: 8 fields: @@ -1121,22 +1120,41 @@ fieldset/IC_IDENTITY: enum/BIT_RATE_E: bit_size: 4 variants: - - name: 106 + - name: '106' value: 0 - - name: 212 + - name: '212' value: 1 - - name: 424 + - name: '424' value: 2 - - name: 848 + - name: '848' value: 3 - - name: 1695 + - name: '1695' value: 4 - - name: 3390 + - name: '3390' value: 5 - - name: 6780 + - name: '6780' value: 6 -enum/THRESHOLD_DEF: - bit_size: 8 +enum/THRESHOLD_DEF_1: + bit_size: 3 + variants: + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 +enum/THRESHOLD_DEF_2: + bit_size: 4 variants: - name: 75mv value: 0 @@ -1171,23 +1189,24 @@ enum/THRESHOLD_DEF: - name: 250mv value: 15 enum/WAKEUP_TIMES_DEF: - bit_size: 8 + bit_size: 3 + description: Typical wake-up time, values for wur=1; multiply by 10 for wur=0 variants: - - name: 10 + - name: '10' value: 0 - - name: 20 + - name: '20' value: 1 - - name: 30 + - name: '30' value: 2 - - name: 40 + - name: '40' value: 3 - - name: 50 + - name: '50' value: 4 - - name: 60 + - name: '60' value: 5 - - name: 70 + - name: '70' value: 6 - - name: 80 + - name: '80' value: 7 enum/IC_IDENTITY_ic_rev: bit_size: 3 @@ -1235,13 +1254,13 @@ enum/ISO14443B_1_sof_0: enum/ISO14443B_2_f_p: bit_size: 2 variants: - - name: 48 + - name: '48' value: 0 - - name: 64 + - name: '64' value: 1 - - name: 80 + - name: '80' value: 2 - - name: 96 + - name: '96' value: 3 enum/ISO14443B_2_tr1: bit_size: 2 @@ -1321,13 +1340,13 @@ enum/STREAM_MODE_scp: enum/STREAM_MODE_stx: bit_size: 3 variants: - - name: 106 + - name: '106' value: 0 - - name: 212 + - name: '212' value: 1 - - name: 424 + - name: '424' value: 2 - - name: 848 + - name: '848' value: 3 enum/TIMER_EMV_CONTROL_gptc: bit_size: 3 diff --git a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml index aaade4f..cc39f51 100644 --- a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml +++ b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml @@ -1137,7 +1137,7 @@ enum/AUX_nfc_id: value: 0 - name: 7bytes value: 1 -enum/BIT_RATE: +enum/BIT_RATE_E: bit_size: 2 variants: - name: "106" From 5d0969880d59a06972c242eebac6fd830c65c48f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Tue, 18 Feb 2025 22:38:11 +0100 Subject: [PATCH 4/8] regs: apply alphabetical formatting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit while it is deterministic, it might be less readable if anyone reads Yaml/Regs file, to verify correctness with datasheet (in case no automatic conversion like svd to yaml is possible). It also seems that formatting strips 'access' field from Regs. Signed-off-by: Krzysztof Królczyk --- rnfc-st25r39/src/regs/regs_st25r3911b.rs | 2229 +++++------ rnfc-st25r39/src/regs/regs_st25r3916.rs | 3505 +++++++++-------- .../src/yaml-regmaps/regs-st25r3911b.yaml | 1176 +++--- .../src/yaml-regmaps/regs-st25r3916.yaml | 2627 ++++++------ 4 files changed, 4765 insertions(+), 4772 deletions(-) diff --git a/rnfc-st25r39/src/regs/regs_st25r3911b.rs b/rnfc-st25r39/src/regs/regs_st25r3911b.rs index 68fa643..3a365ac 100644 --- a/rnfc-st25r39/src/regs/regs_st25r3911b.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3911b.rs @@ -304,228 +304,266 @@ impl<'a, I: Interface> Regs<'a, I> { #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IoConf1(pub u8); -impl IoConf1 { - pub const fn lf_clk_off(&self) -> bool { +pub struct AmplitudeMeasureConf(pub u8); +impl AmplitudeMeasureConf { + pub const fn am_ae(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_lf_clk_off(&mut self, val: bool) { + pub fn set_am_ae(&mut self, val: bool) { self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn out_cl(&self) -> IoConf1OutCl { + pub const fn am_aew(&self) -> u8 { let val = (self.0 >> 1_usize) & 2; - IoConf1OutCl(val as u8) + val as u8 } - pub fn set_out_cl(&mut self, val: IoConf1OutCl) { - self.0 = (self.0 & !(2 << 1_usize)) | ((val.0 as u8) & 2) << 1_usize; + pub fn set_am_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; } - pub const fn osc(&self) -> bool { + pub const fn am_aam(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_osc(&mut self, val: bool) { + pub fn set_am_aam(&mut self, val: bool) { self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn fifo_lt(&self) -> u8 { - let val = (self.0 >> 4_usize) & 2; + pub const fn am_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; val as u8 } - pub fn set_fifo_lt(&mut self, val: u8) { - self.0 = (self.0 & !(2 << 4_usize)) | ((val as u8) & 2) << 4_usize; + pub fn set_am_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } - pub const fn rfo2(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 +} +impl Default for AmplitudeMeasureConf { + fn default() -> AmplitudeMeasureConf { + AmplitudeMeasureConf(0) } - pub fn set_rfo2(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; +} +impl From for AmplitudeMeasureConf { + fn from(val: u8) -> Self { + Self(val) } - pub const fn single(&self) -> bool { +} +impl From for u8 { + fn from(val: AmplitudeMeasureConf) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AmModDepthCtrl(pub u8); +impl AmModDepthCtrl { + pub const fn modd(&self) -> u8 { + let val = (self.0 >> 1_usize) & 6; + val as u8 + } + pub fn set_modd(&mut self, val: u8) { + self.0 = (self.0 & !(6 << 1_usize)) | ((val as u8) & 6) << 1_usize; + } + pub const fn am_s(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_single(&mut self, val: bool) { + pub fn set_am_s(&mut self, val: bool) { self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for IoConf1 { - fn default() -> IoConf1 { - IoConf1(8) +impl Default for AmModDepthCtrl { + fn default() -> AmModDepthCtrl { + AmModDepthCtrl(0) } } -impl From for IoConf1 { +impl From for AmModDepthCtrl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IoConf1) -> u8 { +impl From for u8 { + fn from(val: AmModDepthCtrl) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IoConf2(pub u8); -impl IoConf2 { - pub const fn slow_up(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub fn set_slow_up(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn io_18(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 +pub struct AntTuneCtrl(pub u8); +impl AntTuneCtrl { + pub const fn tre(&self) -> u8 { + let val = (self.0 >> 3_usize) & 4; + val as u8 } - pub fn set_io_18(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + pub fn set_tre(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; } - pub const fn miso_pd1(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; + pub const fn trim_s(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_miso_pd1(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; - } - pub const fn miso_pd2(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; - val != 0 + pub fn set_trim_s(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } - pub fn set_miso_pd2(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; +} +impl Default for AntTuneCtrl { + fn default() -> AntTuneCtrl { + AntTuneCtrl(0) } - pub const fn vspd_off(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 +} +impl From for AntTuneCtrl { + fn from(val: u8) -> Self { + Self(val) } - pub fn set_vspd_off(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; +} +impl From for u8 { + fn from(val: AntTuneCtrl) -> u8 { + val.0 } - pub const fn sup_3v(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AntTuneDisp(pub u8); +impl AntTuneDisp { + pub const fn tri_err(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_sup_3v(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + pub const fn tri(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } } -impl Default for IoConf2 { - fn default() -> IoConf2 { - IoConf2(0) +impl Default for AntTuneDisp { + fn default() -> AntTuneDisp { + AntTuneDisp(0) } } -impl From for IoConf2 { +impl From for AntTuneDisp { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IoConf2) -> u8 { +impl From for u8 { + fn from(val: AntTuneDisp) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct OpControl(pub u8); -impl OpControl { - pub const fn wu(&self) -> bool { +pub struct Aux(pub u8); +impl Aux { + pub const fn nfc_n(&self) -> u8 { + let val = (self.0 >> 0_usize) & 2; + val as u8 + } + pub fn set_nfc_n(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val as u8) & 2) << 0_usize; + } + pub const fn rx_tol(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_wu(&mut self, val: bool) { + pub fn set_rx_tol(&mut self, val: bool) { self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn tx_en(&self) -> bool { + pub const fn ook_hr(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_tx_en(&mut self, val: bool) { + pub fn set_ook_hr(&mut self, val: bool) { self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn rx_man(&self) -> bool { + pub const fn en_fd(&self) -> bool { let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_rx_man(&mut self, val: bool) { + pub fn set_en_fd(&mut self, val: bool) { self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn rx_chn(&self) -> bool { + pub const fn tr_am(&self) -> bool { let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_rx_chn(&mut self, val: bool) { + pub fn set_tr_am(&mut self, val: bool) { self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn rx_en(&self) -> bool { + pub const fn crc_2_fifo(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_rx_en(&mut self, val: bool) { + pub fn set_crc_2_fifo(&mut self, val: bool) { self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn en(&self) -> bool { + pub const fn no_crc_rx(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_en(&mut self, val: bool) { + pub fn set_no_crc_rx(&mut self, val: bool) { self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for OpControl { - fn default() -> OpControl { - OpControl(0) +impl Default for Aux { + fn default() -> Aux { + Aux(0) } } -impl From for OpControl { +impl From for Aux { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: OpControl) -> u8 { +impl From for u8 { + fn from(val: Aux) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Mode(pub u8); -impl Mode { - pub const fn nfc_ar(&self) -> bool { +pub struct AuxDisplay(pub u8); +impl AuxDisplay { + pub const fn en_ac(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_nfc_ar(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + pub const fn nfc_t(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } - pub const fn om(&self) -> ModeOm { - let val = (self.0 >> 3_usize) & 4; - ModeOm(val as u8) + pub const fn rx_act(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } - pub fn set_om(&mut self, val: ModeOm) { - self.0 = (self.0 & !(4 << 3_usize)) | ((val.0 as u8) & 4) << 3_usize; + pub const fn rx_on(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } - pub const fn targ(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; + pub const fn osc_ok(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_targ(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + pub const fn tx_on(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub const fn efd_o(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub const fn a_cha(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } } -impl Default for Mode { - fn default() -> Mode { - Mode(8) +impl Default for AuxDisplay { + fn default() -> AuxDisplay { + AuxDisplay(0) } } -impl From for Mode { +impl From for AuxDisplay { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Mode) -> u8 { +impl From for u8 { + fn from(val: AuxDisplay) -> u8 { val.0 } } @@ -565,703 +603,566 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443ANfc(pub u8); -impl Iso14443ANfc { - pub const fn antcl(&self) -> bool { +pub struct CapacitanceMeasureConf(pub u8); +impl CapacitanceMeasureConf { + pub const fn cm_ae(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_antcl(&mut self, val: bool) { + pub fn set_cm_ae(&mut self, val: bool) { self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn p_len(&self) -> u8 { - let val = (self.0 >> 1_usize) & 4; + pub const fn cm_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; val as u8 } - pub fn set_p_len(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 1_usize)) | ((val as u8) & 4) << 1_usize; - } - pub const fn nfc_f0(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 - } - pub fn set_nfc_f0(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + pub fn set_cm_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; } - pub const fn no_rx_par(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; + pub const fn cm_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_no_rx_par(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + pub fn set_cm_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn no_tx_par(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 + pub const fn cm_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub fn set_no_tx_par(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + pub fn set_cm_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for Iso14443ANfc { - fn default() -> Iso14443ANfc { - Iso14443ANfc(0) +impl Default for CapacitanceMeasureConf { + fn default() -> CapacitanceMeasureConf { + CapacitanceMeasureConf(0) } } -impl From for Iso14443ANfc { +impl From for CapacitanceMeasureConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443ANfc) -> u8 { +impl From for u8 { + fn from(val: CapacitanceMeasureConf) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443B1(pub u8); -impl Iso14443B1 { - pub const fn rx_st_om(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub fn set_rx_st_om(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn half(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; - val != 0 - } - pub fn set_half(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn eof(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 - } - pub fn set_eof(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn sof_1(&self) -> Iso14443B1Sof1 { - let val = (self.0 >> 3_usize) & 1; - Iso14443B1Sof1(val as u8) - } - pub fn set_sof_1(&mut self, val: Iso14443B1Sof1) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val.0 as u8) & 1) << 3_usize; - } - pub const fn sof_0(&self) -> Iso14443B1Sof0 { - let val = (self.0 >> 4_usize) & 1; - Iso14443B1Sof0(val as u8) +pub struct CapSensorControl(pub u8); +impl CapSensorControl { + pub const fn cs_g(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; + val as u8 } - pub fn set_sof_0(&mut self, val: Iso14443B1Sof0) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val.0 as u8) & 1) << 4_usize; + pub fn set_cs_g(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; } - pub const fn egt(&self) -> u8 { - let val = (self.0 >> 5_usize) & 3; + pub const fn cs_mcal(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; val as u8 } - pub fn set_egt(&mut self, val: u8) { - self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; + pub fn set_cs_mcal(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; } } -impl Default for Iso14443B1 { - fn default() -> Iso14443B1 { - Iso14443B1(0) +impl Default for CapSensorControl { + fn default() -> CapSensorControl { + CapSensorControl(0) } } -impl From for Iso14443B1 { +impl From for CapSensorControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443B1) -> u8 { +impl From for u8 { + fn from(val: CapSensorControl) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443B2(pub u8); -impl Iso14443B2 { - pub const fn f_p(&self) -> Iso14443B2FP { - let val = (self.0 >> 0_usize) & 2; - Iso14443B2FP(val as u8) - } - pub fn set_f_p(&mut self, val: Iso14443B2FP) { - self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; +pub struct CapSensorDisp(pub u8); +impl CapSensorDisp { + pub const fn cs_cal_err(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } - pub const fn phc_th(&self) -> bool { + pub const fn cs_cal_end(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_phc_th(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn eof_12(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 + pub const fn cs_cal_val(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; + val as u8 } - pub fn set_eof_12(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; +} +impl Default for CapSensorDisp { + fn default() -> CapSensorDisp { + CapSensorDisp(0) } - pub const fn no_eof(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; - val != 0 +} +impl From for CapSensorDisp { + fn from(val: u8) -> Self { + Self(val) } - pub fn set_no_eof(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; +} +impl From for u8 { + fn from(val: CapSensorDisp) -> u8 { + val.0 } - pub const fn no_sof(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CollisionStatus(pub u8); +impl CollisionStatus { + pub const fn c_pb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_no_sof(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn tr1(&self) -> Iso14443B2Tr1 { - let val = (self.0 >> 6_usize) & 2; - Iso14443B2Tr1(val as u8) + pub const fn c_bit(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 } - pub fn set_tr1(&mut self, val: Iso14443B2Tr1) { - self.0 = (self.0 & !(2 << 6_usize)) | ((val.0 as u8) & 2) << 6_usize; + pub const fn c_byte(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } } -impl Default for Iso14443B2 { - fn default() -> Iso14443B2 { - Iso14443B2(0) +impl Default for CollisionStatus { + fn default() -> CollisionStatus { + CollisionStatus(0) } } -impl From for Iso14443B2 { +impl From for CollisionStatus { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443B2) -> u8 { +impl From for u8 { + fn from(val: CollisionStatus) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct StreamMode(pub u8); -impl StreamMode { - pub const fn stx(&self) -> StreamModeStx { - let val = (self.0 >> 0_usize) & 3; - StreamModeStx(val as u8) - } - pub fn set_stx(&mut self, val: StreamModeStx) { - self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; - } - pub const fn scp(&self) -> StreamModeScp { - let val = (self.0 >> 3_usize) & 2; - StreamModeScp(val as u8) +pub struct ExtFieldDetThr(pub u8); +impl ExtFieldDetThr { + pub const fn rfe_t(&self) -> ThresholdDef2 { + let val = (self.0 >> 0_usize) & 4; + ThresholdDef2(val as u8) } - pub fn set_scp(&mut self, val: StreamModeScp) { - self.0 = (self.0 & !(2 << 3_usize)) | ((val.0 as u8) & 2) << 3_usize; + pub fn set_rfe_t(&mut self, val: ThresholdDef2) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; } - pub const fn scf(&self) -> StreamModeScf { - let val = (self.0 >> 5_usize) & 2; - StreamModeScf(val as u8) + pub const fn trg_l(&self) -> ThresholdDef1 { + let val = (self.0 >> 4_usize) & 3; + ThresholdDef1(val as u8) } - pub fn set_scf(&mut self, val: StreamModeScf) { - self.0 = (self.0 & !(2 << 5_usize)) | ((val.0 as u8) & 2) << 5_usize; + pub fn set_trg_l(&mut self, val: ThresholdDef1) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val.0 as u8) & 3) << 4_usize; } } -impl Default for StreamMode { - fn default() -> StreamMode { - StreamMode(0) +impl Default for ExtFieldDetThr { + fn default() -> ExtFieldDetThr { + ExtFieldDetThr(0) } } -impl From for StreamMode { +impl From for ExtFieldDetThr { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: StreamMode) -> u8 { +impl From for u8 { + fn from(val: ExtFieldDetThr) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Aux(pub u8); -impl Aux { - pub const fn nfc_n(&self) -> u8 { - let val = (self.0 >> 0_usize) & 2; - val as u8 - } - pub fn set_nfc_n(&mut self, val: u8) { - self.0 = (self.0 & !(2 << 0_usize)) | ((val as u8) & 2) << 0_usize; - } - pub const fn rx_tol(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 - } - pub fn set_rx_tol(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn ook_hr(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 - } - pub fn set_ook_hr(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; - } - pub const fn en_fd(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; +pub struct FifoStatus2(pub u8); +impl FifoStatus2 { + pub const fn np_lb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_en_fd(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + pub const fn fifo_lb(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 } - pub const fn tr_am(&self) -> bool { + pub const fn fifo_ovr(&self) -> bool { let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_tr_am(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn crc_2_fifo(&self) -> bool { + pub const fn fifo_unf(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_crc_2_fifo(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; +} +impl Default for FifoStatus2 { + fn default() -> FifoStatus2 { + FifoStatus2(0) } - pub const fn no_crc_rx(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 +} +impl From for FifoStatus2 { + fn from(val: u8) -> Self { + Self(val) } - pub fn set_no_crc_rx(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; +} +impl From for u8 { + fn from(val: FifoStatus2) -> u8 { + val.0 } } -impl Default for Aux { - fn default() -> Aux { - Aux(0) +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GainReduState(pub u8); +impl GainReduState { + pub const fn gs_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 + } + pub const fn gs_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } } -impl From for Aux { +impl Default for GainReduState { + fn default() -> GainReduState { + GainReduState(0) + } +} +impl From for GainReduState { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Aux) -> u8 { +impl From for u8 { + fn from(val: GainReduState) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf1(pub u8); -impl RxConf1 { - pub const fn z12k(&self) -> bool { +pub struct GptNrtCtrl(pub u8); +impl GptNrtCtrl { + pub const fn nrt_step(&self) -> TimerEmvControlNrtStep { let val = (self.0 >> 0_usize) & 1; - val != 0 + TimerEmvControlNrtStep(val as u8) } - pub fn set_z12k(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + pub fn set_nrt_step(&mut self, val: TimerEmvControlNrtStep) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val.0 as u8) & 1) << 0_usize; } - pub const fn h80(&self) -> bool { + pub const fn nrt_emv(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_h80(&mut self, val: bool) { + pub fn set_nrt_emv(&mut self, val: bool) { self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn h200(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 - } - pub fn set_h200(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + pub const fn gptc(&self) -> TimerEmvControlGptc { + let val = (self.0 >> 5_usize) & 3; + TimerEmvControlGptc(val as u8) } - pub const fn lp(&self) -> RxConf1Lp { - let val = (self.0 >> 3_usize) & 3; - RxConf1Lp(val as u8) + pub fn set_gptc(&mut self, val: TimerEmvControlGptc) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val.0 as u8) & 3) << 5_usize; } - pub fn set_lp(&mut self, val: RxConf1Lp) { - self.0 = (self.0 & !(3 << 3_usize)) | ((val.0 as u8) & 3) << 3_usize; +} +impl Default for GptNrtCtrl { + fn default() -> GptNrtCtrl { + GptNrtCtrl(0) } - pub const fn amd_sel(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 +} +impl From for GptNrtCtrl { + fn from(val: u8) -> Self { + Self(val) } - pub fn set_amd_sel(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; +} +impl From for u8 { + fn from(val: GptNrtCtrl) -> u8 { + val.0 } - pub const fn ch_sel(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IcIdentity(pub u8); +impl IcIdentity { + pub const fn ic_rev(&self) -> IcIdentityIcRev { + let val = (self.0 >> 0_usize) & 3; + IcIdentityIcRev(val as u8) } - pub fn set_ch_sel(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + pub const fn ic_type(&self) -> IcIdentityIcType { + let val = (self.0 >> 3_usize) & 5; + IcIdentityIcType(val as u8) } } -impl Default for RxConf1 { - fn default() -> RxConf1 { - RxConf1(0) +impl Default for IcIdentity { + fn default() -> IcIdentity { + IcIdentity(0) } } -impl From for RxConf1 { +impl From for IcIdentity { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf1) -> u8 { +impl From for u8 { + fn from(val: IcIdentity) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf2(pub u8); -impl RxConf2 { - pub const fn pmix_cl(&self) -> bool { +pub struct IoConf1(pub u8); +impl IoConf1 { + pub const fn lf_clk_off(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_pmix_cl(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn sqm_dyn(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; - val != 0 - } - pub fn set_sqm_dyn(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn agc_alg(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 - } - pub fn set_agc_alg(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + pub fn set_lf_clk_off(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn agc_m(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 + pub const fn out_cl(&self) -> IoConf1OutCl { + let val = (self.0 >> 1_usize) & 2; + IoConf1OutCl(val as u8) } - pub fn set_agc_m(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + pub fn set_out_cl(&mut self, val: IoConf1OutCl) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val.0 as u8) & 2) << 1_usize; } - pub const fn agc_en(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; + pub const fn osc(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_agc_en(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + pub fn set_osc(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn lf_en(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 + pub const fn fifo_lt(&self) -> u8 { + let val = (self.0 >> 4_usize) & 2; + val as u8 } - pub fn set_lf_en(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + pub fn set_fifo_lt(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 4_usize)) | ((val as u8) & 2) << 4_usize; } - pub const fn lf_op(&self) -> bool { + pub const fn rfo2(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_lf_op(&mut self, val: bool) { + pub fn set_rfo2(&mut self, val: bool) { self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn rx_lp(&self) -> bool { + pub const fn single(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_rx_lp(&mut self, val: bool) { + pub fn set_single(&mut self, val: bool) { self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RxConf2 { - fn default() -> RxConf2 { - RxConf2(0) +impl Default for IoConf1 { + fn default() -> IoConf1 { + IoConf1(0) } } -impl From for RxConf2 { +impl From for IoConf1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf2) -> u8 { +impl From for u8 { + fn from(val: IoConf1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf3(pub u8); -impl RxConf3 { - pub const fn rg_nfc(&self) -> bool { +pub struct IoConf2(pub u8); +impl IoConf2 { + pub const fn slow_up(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_rg_nfc(&mut self, val: bool) { + pub fn set_slow_up(&mut self, val: bool) { self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn lim(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; + pub const fn io_18(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_lim(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn rg1_pm(&self) -> u8 { - let val = (self.0 >> 2_usize) & 3; - val as u8 - } - pub fn set_rg1_pm(&mut self, val: u8) { - self.0 = (self.0 & !(3 << 2_usize)) | ((val as u8) & 3) << 2_usize; - } - pub const fn rg1_am(&self) -> u8 { - let val = (self.0 >> 5_usize) & 3; - val as u8 + pub fn set_io_18(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub fn set_rg1_am(&mut self, val: u8) { - self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; + pub const fn miso_pd1(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } -} -impl Default for RxConf3 { - fn default() -> RxConf3 { - RxConf3(0) + pub fn set_miso_pd1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } -} -impl From for RxConf3 { - fn from(val: u8) -> Self { - Self(val) + pub const fn miso_pd2(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: RxConf3) -> u8 { - val.0 + pub fn set_miso_pd2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf4(pub u8); -impl RxConf4 { - pub const fn rg2_pm(&self) -> u8 { - let val = (self.0 >> 0_usize) & 4; - val as u8 + pub const fn vspd_off(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 } - pub fn set_rg2_pm(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; + pub fn set_vspd_off(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn rg2_am(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; - val as u8 + pub const fn sup_3v(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub fn set_rg2_am(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + pub fn set_sup_3v(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RxConf4 { - fn default() -> RxConf4 { - RxConf4(0) +impl Default for IoConf2 { + fn default() -> IoConf2 { + IoConf2(0) } } -impl From for RxConf4 { +impl From for IoConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf4) -> u8 { +impl From for u8 { + fn from(val: IoConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MaskRxTimer(pub u8); -impl MaskRxTimer { - pub const fn mrt0(&self) -> bool { +pub struct IrqMain(pub u8); +impl IrqMain { + pub const fn err(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_mrt0(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn mrt1(&self) -> bool { + pub const fn tim(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_mrt1(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn mrt2(&self) -> bool { + pub const fn col(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_mrt2(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn mrt3(&self) -> bool { + pub const fn txe(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_mrt3(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; - } - pub const fn mrt4(&self) -> bool { + pub const fn rxe(&self) -> bool { let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_mrt4(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; - } - pub const fn mrt5(&self) -> bool { + pub const fn rxs(&self) -> bool { let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_mrt5(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn mrt6(&self) -> bool { + pub const fn wl(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_mrt6(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; - } - pub const fn mrt7(&self) -> bool { + pub const fn osc(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_mrt7(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; - } } -impl Default for MaskRxTimer { - fn default() -> MaskRxTimer { - MaskRxTimer(0) +impl Default for IrqMain { + fn default() -> IrqMain { + IrqMain(0) } } -impl From for MaskRxTimer { +impl From for IrqMain { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: MaskRxTimer) -> u8 { +impl From for u8 { + fn from(val: IrqMain) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct NoResponseTimer1(pub u8); -impl NoResponseTimer1 { - pub const fn nrt8(&self) -> bool { +pub struct IrqMaskErrorWup(pub u8); +impl IrqMaskErrorWup { + pub const fn m_ncap(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_nrt8(&mut self, val: bool) { + pub fn set_m_ncap(&mut self, val: bool) { self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn nrt9(&self) -> bool { + pub const fn m_wph(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_nrt9(&mut self, val: bool) { + pub fn set_m_wph(&mut self, val: bool) { self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn nrt10(&self) -> bool { + pub const fn m_wam(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_nrt10(&mut self, val: bool) { + pub fn set_m_wam(&mut self, val: bool) { self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn nrt11(&self) -> bool { + pub const fn m_wt(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_nrt11(&mut self, val: bool) { + pub fn set_m_wt(&mut self, val: bool) { self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn nrt12(&self) -> bool { + pub const fn m_err1(&self) -> bool { let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_nrt12(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; - } - pub const fn nrt13(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 - } - pub fn set_nrt13(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn nrt14(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 - } - pub fn set_nrt14(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; - } - pub const fn nrt15(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 - } - pub fn set_nrt15(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; - } -} -impl Default for NoResponseTimer1 { - fn default() -> NoResponseTimer1 { - NoResponseTimer1(0) - } -} -impl From for NoResponseTimer1 { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: NoResponseTimer1) -> u8 { - val.0 - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GptNrtCtrl(pub u8); -impl GptNrtCtrl { - pub const fn nrt_step(&self) -> TimerEmvControlNrtStep { - let val = (self.0 >> 0_usize) & 1; - TimerEmvControlNrtStep(val as u8) + pub fn set_m_err1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub fn set_nrt_step(&mut self, val: TimerEmvControlNrtStep) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val.0 as u8) & 1) << 0_usize; + pub const fn m_err2(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } - pub const fn nrt_emv(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; + pub fn set_m_err2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn m_par(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_nrt_emv(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + pub fn set_m_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn gptc(&self) -> TimerEmvControlGptc { - let val = (self.0 >> 5_usize) & 3; - TimerEmvControlGptc(val as u8) + pub const fn m_crc(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub fn set_gptc(&mut self, val: TimerEmvControlGptc) { - self.0 = (self.0 & !(3 << 5_usize)) | ((val.0 as u8) & 3) << 5_usize; + pub fn set_m_crc(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for GptNrtCtrl { - fn default() -> GptNrtCtrl { - GptNrtCtrl(0) +impl Default for IrqMaskErrorWup { + fn default() -> IrqMaskErrorWup { + IrqMaskErrorWup(0) } } -impl From for GptNrtCtrl { +impl From for IrqMaskErrorWup { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: GptNrtCtrl) -> u8 { +impl From for u8 { + fn from(val: IrqMaskErrorWup) -> u8 { val.0 } } @@ -1405,283 +1306,349 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqMaskErrorWup(pub u8); -impl IrqMaskErrorWup { - pub const fn m_ncap(&self) -> bool { +pub struct IrqTimerNfc(pub u8); +impl IrqTimerNfc { + pub const fn nfct(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_m_ncap(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn m_wph(&self) -> bool { + pub const fn cat(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_m_wph(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn m_wam(&self) -> bool { + pub const fn cac(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_m_wam(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn m_wt(&self) -> bool { + pub const fn eof(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_m_wt(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; - } - pub const fn m_err1(&self) -> bool { + pub const fn eon(&self) -> bool { let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_m_err1(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + pub const fn gpe(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } - pub const fn m_err2(&self) -> bool { + pub const fn nre(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub const fn dcd(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } +} +impl Default for IrqTimerNfc { + fn default() -> IrqTimerNfc { + IrqTimerNfc(0) + } +} +impl From for IrqTimerNfc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: IrqTimerNfc) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Iso14443ANfc(pub u8); +impl Iso14443ANfc { + pub const fn antcl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_antcl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn p_len(&self) -> u8 { + let val = (self.0 >> 1_usize) & 4; + val as u8 + } + pub fn set_p_len(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 1_usize)) | ((val as u8) & 4) << 1_usize; + } + pub const fn nfc_f0(&self) -> bool { let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_m_err2(&mut self, val: bool) { + pub fn set_nfc_f0(&mut self, val: bool) { self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn m_par(&self) -> bool { + pub const fn no_rx_par(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_m_par(&mut self, val: bool) { + pub fn set_no_rx_par(&mut self, val: bool) { self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn m_crc(&self) -> bool { + pub const fn no_tx_par(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_m_crc(&mut self, val: bool) { + pub fn set_no_tx_par(&mut self, val: bool) { self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for IrqMaskErrorWup { - fn default() -> IrqMaskErrorWup { - IrqMaskErrorWup(0) +impl Default for Iso14443ANfc { + fn default() -> Iso14443ANfc { + Iso14443ANfc(0) } } -impl From for IrqMaskErrorWup { +impl From for Iso14443ANfc { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IrqMaskErrorWup) -> u8 { +impl From for u8 { + fn from(val: Iso14443ANfc) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqMain(pub u8); -impl IrqMain { - pub const fn err(&self) -> bool { +pub struct Iso14443B1(pub u8); +impl Iso14443B1 { + pub const fn rx_st_om(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub const fn tim(&self) -> bool { + pub fn set_rx_st_om(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn half(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub const fn col(&self) -> bool { + pub fn set_half(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn eof(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub const fn txe(&self) -> bool { + pub fn set_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn sof_1(&self) -> Iso14443B1Sof1 { let val = (self.0 >> 3_usize) & 1; - val != 0 + Iso14443B1Sof1(val as u8) } - pub const fn rxe(&self) -> bool { + pub fn set_sof_1(&mut self, val: Iso14443B1Sof1) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val.0 as u8) & 1) << 3_usize; + } + pub const fn sof_0(&self) -> Iso14443B1Sof0 { let val = (self.0 >> 4_usize) & 1; - val != 0 + Iso14443B1Sof0(val as u8) } - pub const fn rxs(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 + pub fn set_sof_0(&mut self, val: Iso14443B1Sof0) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val.0 as u8) & 1) << 4_usize; } - pub const fn wl(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 + pub const fn egt(&self) -> u8 { + let val = (self.0 >> 5_usize) & 3; + val as u8 } - pub const fn osc(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 + pub fn set_egt(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; } } -impl Default for IrqMain { - fn default() -> IrqMain { - IrqMain(0) +impl Default for Iso14443B1 { + fn default() -> Iso14443B1 { + Iso14443B1(0) } } -impl From for IrqMain { +impl From for Iso14443B1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IrqMain) -> u8 { +impl From for u8 { + fn from(val: Iso14443B1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IrqTimerNfc(pub u8); -impl IrqTimerNfc { - pub const fn nfct(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 +pub struct Iso14443B2(pub u8); +impl Iso14443B2 { + pub const fn f_p(&self) -> Iso14443B2FP { + let val = (self.0 >> 0_usize) & 2; + Iso14443B2FP(val as u8) } - pub const fn cat(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; - val != 0 + pub fn set_f_p(&mut self, val: Iso14443B2FP) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; } - pub const fn cac(&self) -> bool { + pub const fn phc_th(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub const fn eof(&self) -> bool { + pub fn set_phc_th(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn eof_12(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub const fn eon(&self) -> bool { + pub fn set_eof_12(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn no_eof(&self) -> bool { let val = (self.0 >> 4_usize) & 1; val != 0 } - pub const fn gpe(&self) -> bool { + pub fn set_no_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn no_sof(&self) -> bool { let val = (self.0 >> 5_usize) & 1; val != 0 } - pub const fn nre(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 + pub fn set_no_sof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn dcd(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 + pub const fn tr1(&self) -> Iso14443B2Tr1 { + let val = (self.0 >> 6_usize) & 2; + Iso14443B2Tr1(val as u8) + } + pub fn set_tr1(&mut self, val: Iso14443B2Tr1) { + self.0 = (self.0 & !(2 << 6_usize)) | ((val.0 as u8) & 2) << 6_usize; } } -impl Default for IrqTimerNfc { - fn default() -> IrqTimerNfc { - IrqTimerNfc(0) +impl Default for Iso14443B2 { + fn default() -> Iso14443B2 { + Iso14443B2(0) } } -impl From for IrqTimerNfc { +impl From for Iso14443B2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IrqTimerNfc) -> u8 { +impl From for u8 { + fn from(val: Iso14443B2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct FifoStatus2(pub u8); -impl FifoStatus2 { - pub const fn np_lb(&self) -> bool { +pub struct MaskRxTimer(pub u8); +impl MaskRxTimer { + pub const fn mrt0(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub const fn fifo_lb(&self) -> u8 { - let val = (self.0 >> 1_usize) & 3; - val as u8 + pub fn set_mrt0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn fifo_ovr(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; + pub const fn mrt1(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub const fn fifo_unf(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; + pub fn set_mrt1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn mrt2(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } -} -impl Default for FifoStatus2 { - fn default() -> FifoStatus2 { - FifoStatus2(0) + pub fn set_mrt2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } -} -impl From for FifoStatus2 { - fn from(val: u8) -> Self { - Self(val) + pub const fn mrt3(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: FifoStatus2) -> u8 { - val.0 + pub fn set_mrt3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct CollisionStatus(pub u8); -impl CollisionStatus { - pub const fn c_pb(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; + pub const fn mrt4(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub const fn c_bit(&self) -> u8 { - let val = (self.0 >> 1_usize) & 3; - val as u8 + pub fn set_mrt4(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn c_byte(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; - val as u8 + pub const fn mrt5(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_mrt5(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn mrt6(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_mrt6(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn mrt7(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_mrt7(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for CollisionStatus { - fn default() -> CollisionStatus { - CollisionStatus(0) +impl Default for MaskRxTimer { + fn default() -> MaskRxTimer { + MaskRxTimer(0) } } -impl From for CollisionStatus { +impl From for MaskRxTimer { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CollisionStatus) -> u8 { +impl From for u8 { + fn from(val: MaskRxTimer) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct NumTxBytes2(pub u8); -impl NumTxBytes2 { - pub const fn nbtx(&self) -> u8 { - let val = (self.0 >> 0_usize) & 3; - val as u8 +pub struct Mode(pub u8); +impl Mode { + pub const fn nfc_ar(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub fn set_nbtx(&mut self, val: u8) { - self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; + pub fn set_nfc_ar(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn ntx(&self) -> u8 { - let val = (self.0 >> 3_usize) & 5; - val as u8 + pub const fn om(&self) -> ModeOm { + let val = (self.0 >> 3_usize) & 4; + ModeOm(val as u8) } - pub fn set_ntx(&mut self, val: u8) { - self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; + pub fn set_om(&mut self, val: ModeOm) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val.0 as u8) & 4) << 3_usize; + } + pub const fn targ(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_targ(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for NumTxBytes2 { - fn default() -> NumTxBytes2 { - NumTxBytes2(0) +impl Default for Mode { + fn default() -> Mode { + Mode(0) } } -impl From for NumTxBytes2 { +impl From for Mode { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: NumTxBytes2) -> u8 { +impl From for u8 { + fn from(val: Mode) -> u8 { val.0 } } @@ -1711,248 +1678,221 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AntTuneCtrl(pub u8); -impl AntTuneCtrl { - pub const fn tre(&self) -> u8 { - let val = (self.0 >> 3_usize) & 4; - val as u8 +pub struct NoResponseTimer1(pub u8); +impl NoResponseTimer1 { + pub const fn nrt8(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub fn set_tre(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; + pub fn set_nrt8(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn trim_s(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; + pub const fn nrt9(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_trim_s(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; - } -} -impl Default for AntTuneCtrl { - fn default() -> AntTuneCtrl { - AntTuneCtrl(0) + pub fn set_nrt9(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } -} -impl From for AntTuneCtrl { - fn from(val: u8) -> Self { - Self(val) + pub const fn nrt10(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: AntTuneCtrl) -> u8 { - val.0 + pub fn set_nrt10(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AntTuneDisp(pub u8); -impl AntTuneDisp { - pub const fn tri_err(&self) -> bool { + pub const fn nrt11(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub const fn tri(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; - val as u8 + pub fn set_nrt11(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn nrt12(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_nrt12(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn nrt13(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_nrt13(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn nrt14(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_nrt14(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn nrt15(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_nrt15(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for AntTuneDisp { - fn default() -> AntTuneDisp { - AntTuneDisp(0) +impl Default for NoResponseTimer1 { + fn default() -> NoResponseTimer1 { + NoResponseTimer1(0) } } -impl From for AntTuneDisp { +impl From for NoResponseTimer1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AntTuneDisp) -> u8 { +impl From for u8 { + fn from(val: NoResponseTimer1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AmModDepthCtrl(pub u8); -impl AmModDepthCtrl { - pub const fn modd(&self) -> u8 { - let val = (self.0 >> 1_usize) & 6; +pub struct NumTxBytes2(pub u8); +impl NumTxBytes2 { + pub const fn nbtx(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; val as u8 } - pub fn set_modd(&mut self, val: u8) { - self.0 = (self.0 & !(6 << 1_usize)) | ((val as u8) & 6) << 1_usize; + pub fn set_nbtx(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; } - pub const fn am_s(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 + pub const fn ntx(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; + val as u8 } - pub fn set_am_s(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + pub fn set_ntx(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; } } -impl Default for AmModDepthCtrl { - fn default() -> AmModDepthCtrl { - AmModDepthCtrl(0) +impl Default for NumTxBytes2 { + fn default() -> NumTxBytes2 { + NumTxBytes2(0) } } -impl From for AmModDepthCtrl { +impl From for NumTxBytes2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AmModDepthCtrl) -> u8 { +impl From for u8 { + fn from(val: NumTxBytes2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RfoAmLevelDef(pub u8); -impl RfoAmLevelDef { - pub const fn d0(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub fn set_d0(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn d1(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; - val != 0 - } - pub fn set_d1(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn d2(&self) -> bool { +pub struct OpControl(pub u8); +impl OpControl { + pub const fn wu(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_d2(&mut self, val: bool) { + pub fn set_wu(&mut self, val: bool) { self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn d3(&self) -> bool { + pub const fn tx_en(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_d3(&mut self, val: bool) { + pub fn set_tx_en(&mut self, val: bool) { self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn d4(&self) -> bool { + pub const fn rx_man(&self) -> bool { let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_d4(&mut self, val: bool) { + pub fn set_rx_man(&mut self, val: bool) { self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn d5(&self) -> bool { + pub const fn rx_chn(&self) -> bool { let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_d5(&mut self, val: bool) { + pub fn set_rx_chn(&mut self, val: bool) { self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn d6(&self) -> bool { + pub const fn rx_en(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_d6(&mut self, val: bool) { + pub fn set_rx_en(&mut self, val: bool) { self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn d7(&self) -> bool { + pub const fn en(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_d7(&mut self, val: bool) { + pub fn set_en(&mut self, val: bool) { self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RfoAmLevelDef { - fn default() -> RfoAmLevelDef { - RfoAmLevelDef(0) +impl Default for OpControl { + fn default() -> OpControl { + OpControl(0) } } -impl From for RfoAmLevelDef { +impl From for OpControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RfoAmLevelDef) -> u8 { +impl From for u8 { + fn from(val: OpControl) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct ExtFieldDetThr(pub u8); -impl ExtFieldDetThr { - pub const fn rfe_t(&self) -> ThresholdDef { - let val = (self.0 >> 0_usize) & 4; - ThresholdDef(val as u8) - } - pub fn set_rfe_t(&mut self, val: ThresholdDef) { - self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; - } - pub const fn trg_l(&self) -> ThresholdDef { - let val = (self.0 >> 4_usize) & 3; - ThresholdDef(val as u8) - } - pub fn set_trg_l(&mut self, val: ThresholdDef) { - self.0 = (self.0 & !(3 << 4_usize)) | ((val.0 as u8) & 3) << 4_usize; - } -} -impl Default for ExtFieldDetThr { - fn default() -> ExtFieldDetThr { - ExtFieldDetThr(51) - } -} -impl From for ExtFieldDetThr { - fn from(val: u8) -> Self { - Self(val) +pub struct PhaseMeasureConf(pub u8); +impl PhaseMeasureConf { + pub const fn pm_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: ExtFieldDetThr) -> u8 { - val.0 + pub fn set_pm_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct RegulatorVoltControl(pub u8); -impl RegulatorVoltControl { - pub const fn mpsv(&self) -> u8 { + pub const fn pm_aew(&self) -> u8 { let val = (self.0 >> 1_usize) & 2; val as u8 } - pub fn set_mpsv(&mut self, val: u8) { + pub fn set_pm_aew(&mut self, val: u8) { self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; } - pub const fn rege(&self) -> u8 { - let val = (self.0 >> 3_usize) & 4; - val as u8 + pub const fn pm_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } - pub fn set_rege(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; + pub fn set_pm_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn reg_s(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 + pub const fn pm_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub fn set_reg_s(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + pub fn set_pm_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for RegulatorVoltControl { - fn default() -> RegulatorVoltControl { - RegulatorVoltControl(0) +impl Default for PhaseMeasureConf { + fn default() -> PhaseMeasureConf { + PhaseMeasureConf(0) } } -impl From for RegulatorVoltControl { +impl From for PhaseMeasureConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RegulatorVoltControl) -> u8 { +impl From for u8 { + fn from(val: PhaseMeasureConf) -> u8 { val.0 } } @@ -1994,402 +1934,462 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RssiResult(pub u8); -impl RssiResult { - pub const fn rssi_pm(&self) -> u8 { - let val = (self.0 >> 0_usize) & 4; +pub struct RegulatorVoltControl(pub u8); +impl RegulatorVoltControl { + pub const fn mpsv(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; val as u8 } - pub const fn rssi_am(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; + pub fn set_mpsv(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + } + pub const fn rege(&self) -> u8 { + let val = (self.0 >> 3_usize) & 4; val as u8 } + pub fn set_rege(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; + } + pub const fn reg_s(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_reg_s(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } } -impl Default for RssiResult { - fn default() -> RssiResult { - RssiResult(0) +impl Default for RegulatorVoltControl { + fn default() -> RegulatorVoltControl { + RegulatorVoltControl(0) } } -impl From for RssiResult { +impl From for RegulatorVoltControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RssiResult) -> u8 { +impl From for u8 { + fn from(val: RegulatorVoltControl) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct GainReduState(pub u8); -impl GainReduState { - pub const fn gs_pm(&self) -> u8 { - let val = (self.0 >> 0_usize) & 4; - val as u8 +pub struct RfoAmLevelDef(pub u8); +impl RfoAmLevelDef { + pub const fn d0(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub const fn gs_am(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; - val as u8 + pub fn set_d0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } -} -impl Default for GainReduState { - fn default() -> GainReduState { - GainReduState(0) + pub const fn d1(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } -} -impl From for GainReduState { - fn from(val: u8) -> Self { - Self(val) + pub fn set_d1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } -} -impl From for u8 { - fn from(val: GainReduState) -> u8 { - val.0 + pub const fn d2(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct CapSensorControl(pub u8); -impl CapSensorControl { - pub const fn cs_g(&self) -> u8 { - let val = (self.0 >> 0_usize) & 3; - val as u8 + pub fn set_d2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub fn set_cs_g(&mut self, val: u8) { - self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; + pub const fn d3(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } - pub const fn cs_mcal(&self) -> u8 { - let val = (self.0 >> 3_usize) & 5; - val as u8 + pub fn set_d3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub fn set_cs_mcal(&mut self, val: u8) { - self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; + pub const fn d4(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 } -} -impl Default for CapSensorControl { - fn default() -> CapSensorControl { - CapSensorControl(0) + pub fn set_d4(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn d5(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_d5(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn d6(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_d6(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn d7(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_d7(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for RfoAmLevelDef { + fn default() -> RfoAmLevelDef { + RfoAmLevelDef(0) } } -impl From for CapSensorControl { +impl From for RfoAmLevelDef { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CapSensorControl) -> u8 { +impl From for u8 { + fn from(val: RfoAmLevelDef) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CapSensorDisp(pub u8); -impl CapSensorDisp { - pub const fn cs_cal_err(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; - val != 0 - } - pub const fn cs_cal_end(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 +pub struct RssiResult(pub u8); +impl RssiResult { + pub const fn rssi_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 } - pub const fn cs_cal_val(&self) -> u8 { - let val = (self.0 >> 3_usize) & 5; + pub const fn rssi_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; val as u8 } } -impl Default for CapSensorDisp { - fn default() -> CapSensorDisp { - CapSensorDisp(0) +impl Default for RssiResult { + fn default() -> RssiResult { + RssiResult(0) } } -impl From for CapSensorDisp { +impl From for RssiResult { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CapSensorDisp) -> u8 { +impl From for u8 { + fn from(val: RssiResult) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AuxDisplay(pub u8); -impl AuxDisplay { - pub const fn en_ac(&self) -> bool { +pub struct RxConf1(pub u8); +impl RxConf1 { + pub const fn z12k(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub const fn nfc_t(&self) -> bool { + pub fn set_z12k(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn h80(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub const fn rx_act(&self) -> bool { + pub fn set_h80(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn h200(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub const fn rx_on(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 + pub fn set_h200(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn osc_ok(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; - val != 0 + pub const fn lp(&self) -> RxConf1Lp { + let val = (self.0 >> 3_usize) & 3; + RxConf1Lp(val as u8) } - pub const fn tx_on(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 + pub fn set_lp(&mut self, val: RxConf1Lp) { + self.0 = (self.0 & !(3 << 3_usize)) | ((val.0 as u8) & 3) << 3_usize; } - pub const fn efd_o(&self) -> bool { + pub const fn amd_sel(&self) -> bool { let val = (self.0 >> 6_usize) & 1; val != 0 } - pub const fn a_cha(&self) -> bool { + pub fn set_amd_sel(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn ch_sel(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } + pub fn set_ch_sel(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } } -impl Default for AuxDisplay { - fn default() -> AuxDisplay { - AuxDisplay(0) +impl Default for RxConf1 { + fn default() -> RxConf1 { + RxConf1(0) } } -impl From for AuxDisplay { +impl From for RxConf1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AuxDisplay) -> u8 { +impl From for u8 { + fn from(val: RxConf1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct WupTimerControl(pub u8); -impl WupTimerControl { - pub const fn wph(&self) -> bool { +pub struct RxConf2(pub u8); +impl RxConf2 { + pub const fn pmix_cl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_pmix_cl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn sqm_dyn(&self) -> bool { let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_wph(&mut self, val: bool) { + pub fn set_sqm_dyn(&mut self, val: bool) { self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn wam(&self) -> bool { + pub const fn agc_alg(&self) -> bool { let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_wam(&mut self, val: bool) { + pub fn set_agc_alg(&mut self, val: bool) { self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn wto(&self) -> bool { + pub const fn agc_m(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_wto(&mut self, val: bool) { + pub fn set_agc_m(&mut self, val: bool) { self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn wut(&self) -> u8 { - let val = (self.0 >> 4_usize) & 3; - val as u8 + pub const fn agc_en(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 } - pub fn set_wut(&mut self, val: u8) { - self.0 = (self.0 & !(3 << 4_usize)) | ((val as u8) & 3) << 4_usize; + pub fn set_agc_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn wur(&self) -> bool { + pub const fn lf_en(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_lf_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn lf_op(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_lf_op(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn rx_lp(&self) -> bool { let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_wur(&mut self, val: bool) { + pub fn set_rx_lp(&mut self, val: bool) { self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for WupTimerControl { - fn default() -> WupTimerControl { - WupTimerControl(0) +impl Default for RxConf2 { + fn default() -> RxConf2 { + RxConf2(0) } } -impl From for WupTimerControl { +impl From for RxConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: WupTimerControl) -> u8 { +impl From for u8 { + fn from(val: RxConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AmplitudeMeasureConf(pub u8); -impl AmplitudeMeasureConf { - pub const fn am_ae(&self) -> bool { +pub struct RxConf3(pub u8); +impl RxConf3 { + pub const fn rg_nfc(&self) -> bool { let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_am_ae(&mut self, val: bool) { + pub fn set_rg_nfc(&mut self, val: bool) { self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn am_aew(&self) -> u8 { - let val = (self.0 >> 1_usize) & 2; - val as u8 + pub const fn lim(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } - pub fn set_am_aew(&mut self, val: u8) { - self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + pub fn set_lim(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn am_aam(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 + pub const fn rg1_pm(&self) -> u8 { + let val = (self.0 >> 2_usize) & 3; + val as u8 } - pub fn set_am_aam(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + pub fn set_rg1_pm(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 2_usize)) | ((val as u8) & 3) << 2_usize; } - pub const fn am_d(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; + pub const fn rg1_am(&self) -> u8 { + let val = (self.0 >> 5_usize) & 3; val as u8 } - pub fn set_am_d(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + pub fn set_rg1_am(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; } } -impl Default for AmplitudeMeasureConf { - fn default() -> AmplitudeMeasureConf { - AmplitudeMeasureConf(0) +impl Default for RxConf3 { + fn default() -> RxConf3 { + RxConf3(0) } } -impl From for AmplitudeMeasureConf { +impl From for RxConf3 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AmplitudeMeasureConf) -> u8 { +impl From for u8 { + fn from(val: RxConf3) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct PhaseMeasureConf(pub u8); -impl PhaseMeasureConf { - pub const fn pm_ae(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 +pub struct RxConf4(pub u8); +impl RxConf4 { + pub const fn rg2_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 } - pub fn set_pm_ae(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + pub fn set_rg2_pm(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub const fn pm_aew(&self) -> u8 { - let val = (self.0 >> 1_usize) & 2; + pub const fn rg2_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; val as u8 } - pub fn set_pm_aew(&mut self, val: u8) { - self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + pub fn set_rg2_am(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } - pub const fn pm_aam(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 +} +impl Default for RxConf4 { + fn default() -> RxConf4 { + RxConf4(0) + } +} +impl From for RxConf4 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf4) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct StreamMode(pub u8); +impl StreamMode { + pub const fn stx(&self) -> StreamModeStx { + let val = (self.0 >> 0_usize) & 3; + StreamModeStx(val as u8) + } + pub fn set_stx(&mut self, val: StreamModeStx) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; } - pub fn set_pm_aam(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + pub const fn scp(&self) -> StreamModeScp { + let val = (self.0 >> 3_usize) & 2; + StreamModeScp(val as u8) } - pub const fn pm_d(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; - val as u8 + pub fn set_scp(&mut self, val: StreamModeScp) { + self.0 = (self.0 & !(2 << 3_usize)) | ((val.0 as u8) & 2) << 3_usize; } - pub fn set_pm_d(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; + pub const fn scf(&self) -> StreamModeScf { + let val = (self.0 >> 5_usize) & 2; + StreamModeScf(val as u8) + } + pub fn set_scf(&mut self, val: StreamModeScf) { + self.0 = (self.0 & !(2 << 5_usize)) | ((val.0 as u8) & 2) << 5_usize; } } -impl Default for PhaseMeasureConf { - fn default() -> PhaseMeasureConf { - PhaseMeasureConf(0) +impl Default for StreamMode { + fn default() -> StreamMode { + StreamMode(0) } } -impl From for PhaseMeasureConf { +impl From for StreamMode { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: PhaseMeasureConf) -> u8 { +impl From for u8 { + fn from(val: StreamMode) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CapacitanceMeasureConf(pub u8); -impl CapacitanceMeasureConf { - pub const fn cm_ae(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; +pub struct WupTimerControl(pub u8); +impl WupTimerControl { + pub const fn wph(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_cm_ae(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + pub fn set_wph(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn cm_aew(&self) -> u8 { - let val = (self.0 >> 1_usize) & 2; - val as u8 + pub const fn wam(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } - pub fn set_cm_aew(&mut self, val: u8) { - self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + pub fn set_wam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn cm_aam(&self) -> bool { + pub const fn wto(&self) -> bool { let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_cm_aam(&mut self, val: bool) { + pub fn set_wto(&mut self, val: bool) { self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn cm_d(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; + pub const fn wut(&self) -> u8 { + let val = (self.0 >> 4_usize) & 3; val as u8 } - pub fn set_cm_d(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; - } -} -impl Default for CapacitanceMeasureConf { - fn default() -> CapacitanceMeasureConf { - CapacitanceMeasureConf(0) - } -} -impl From for CapacitanceMeasureConf { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: CapacitanceMeasureConf) -> u8 { - val.0 + pub fn set_wut(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val as u8) & 3) << 4_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IcIdentity(pub u8); -impl IcIdentity { - pub const fn ic_rev(&self) -> IcIdentityIcRev { - let val = (self.0 >> 0_usize) & 3; - IcIdentityIcRev(val as u8) + pub const fn wur(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub const fn ic_type(&self) -> IcIdentityIcType { - let val = (self.0 >> 3_usize) & 5; - IcIdentityIcType(val as u8) + pub fn set_wur(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for IcIdentity { - fn default() -> IcIdentity { - IcIdentity(0) +impl Default for WupTimerControl { + fn default() -> WupTimerControl { + WupTimerControl(0) } } -impl From for IcIdentity { +impl From for WupTimerControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IcIdentity) -> u8 { +impl From for u8 { + fn from(val: WupTimerControl) -> u8 { val.0 } } @@ -2416,62 +2416,6 @@ impl From for u8 { } } -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] -pub struct ThresholdDef(pub u8); -impl ThresholdDef { - pub const _75MV: Self = Self(0x00); - pub const _105MV: Self = Self(0x01); - pub const _150MV: Self = Self(0x02); - pub const _205MV: Self = Self(0x03); - pub const _290MV: Self = Self(0x04); - pub const _400MV: Self = Self(0x05); - pub const _560MV: Self = Self(0x06); - pub const _800MV: Self = Self(0x07); - pub const _25MV: Self = Self(0x08); - pub const _33MV: Self = Self(0x09); - pub const _47MV: Self = Self(0x0a); - pub const _64MV: Self = Self(0x0b); - pub const _90MV: Self = Self(0x0c); - pub const _125MV: Self = Self(0x0d); - pub const _175MV: Self = Self(0x0e); - pub const _250MV: Self = Self(0x0f); -} -impl From for ThresholdDef { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: ThresholdDef) -> u8 { - val.0 - } -} - -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] -pub struct WakeupTimesDef(pub u8); -impl WakeupTimesDef { - pub const _10: Self = Self(0x00); - pub const _20: Self = Self(0x01); - pub const _30: Self = Self(0x02); - pub const _40: Self = Self(0x03); - pub const _50: Self = Self(0x04); - pub const _60: Self = Self(0x05); - pub const _70: Self = Self(0x06); - pub const _80: Self = Self(0x07); -} -impl From for WakeupTimesDef { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: WakeupTimesDef) -> u8 { - val.0 - } -} - #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct IcIdentityIcRev(pub u8); @@ -2532,36 +2476,36 @@ impl From for u8 { #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] -pub struct Iso14443B1Sof1(pub u8); -impl Iso14443B1Sof1 { - pub const _2ETU: Self = Self(0x00); - pub const _3ETU: Self = Self(0x01); +pub struct Iso14443B1Sof0(pub u8); +impl Iso14443B1Sof0 { + pub const _10ETU: Self = Self(0x00); + pub const _11ETU: Self = Self(0x01); } -impl From for Iso14443B1Sof1 { +impl From for Iso14443B1Sof0 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443B1Sof1) -> u8 { +impl From for u8 { + fn from(val: Iso14443B1Sof0) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] -pub struct Iso14443B1Sof0(pub u8); -impl Iso14443B1Sof0 { - pub const _10ETU: Self = Self(0x00); - pub const _11ETU: Self = Self(0x01); +pub struct Iso14443B1Sof1(pub u8); +impl Iso14443B1Sof1 { + pub const _2ETU: Self = Self(0x00); + pub const _3ETU: Self = Self(0x01); } -impl From for Iso14443B1Sof0 { +impl From for Iso14443B1Sof1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443B1Sof0) -> u8 { +impl From for u8 { + fn from(val: Iso14443B1Sof1) -> u8 { val.0 } } @@ -2716,6 +2660,62 @@ impl From for u8 { } } +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct ThresholdDef1(pub u8); +impl ThresholdDef1 { + pub const _75MV: Self = Self(0x00); + pub const _105MV: Self = Self(0x01); + pub const _150MV: Self = Self(0x02); + pub const _205MV: Self = Self(0x03); + pub const _290MV: Self = Self(0x04); + pub const _400MV: Self = Self(0x05); + pub const _560MV: Self = Self(0x06); + pub const _800MV: Self = Self(0x07); +} +impl From for ThresholdDef1 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: ThresholdDef1) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct ThresholdDef2(pub u8); +impl ThresholdDef2 { + pub const _75MV: Self = Self(0x00); + pub const _105MV: Self = Self(0x01); + pub const _150MV: Self = Self(0x02); + pub const _205MV: Self = Self(0x03); + pub const _290MV: Self = Self(0x04); + pub const _400MV: Self = Self(0x05); + pub const _560MV: Self = Self(0x06); + pub const _800MV: Self = Self(0x07); + pub const _25MV: Self = Self(0x08); + pub const _33MV: Self = Self(0x09); + pub const _47MV: Self = Self(0x0a); + pub const _64MV: Self = Self(0x0b); + pub const _90MV: Self = Self(0x0c); + pub const _125MV: Self = Self(0x0d); + pub const _175MV: Self = Self(0x0e); + pub const _250MV: Self = Self(0x0f); +} +impl From for ThresholdDef2 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: ThresholdDef2) -> u8 { + val.0 + } +} + #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct TimerEmvControlGptc(pub u8); @@ -2753,3 +2753,28 @@ impl From for u8 { val.0 } } + +/// Typical wake-up time, values for wur=1; multiply by 10 for wur=0 +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct WakeupTimesDef(pub u8); +impl WakeupTimesDef { + pub const _10: Self = Self(0x00); + pub const _20: Self = Self(0x01); + pub const _30: Self = Self(0x02); + pub const _40: Self = Self(0x03); + pub const _50: Self = Self(0x04); + pub const _60: Self = Self(0x05); + pub const _70: Self = Self(0x06); + pub const _80: Self = Self(0x07); +} +impl From for WakeupTimesDef { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: WakeupTimesDef) -> u8 { + val.0 + } +} diff --git a/rnfc-st25r39/src/regs/regs_st25r3916.rs b/rnfc-st25r39/src/regs/regs_st25r3916.rs index 3efdb61..cb3f404 100644 --- a/rnfc-st25r39/src/regs/regs_st25r3916.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3916.rs @@ -43,11 +43,6 @@ impl<'a, I: Interface, T: Default + Copy + Into + From> Reg<'a, I, T> { Ok(res) } } - -// ========================================================== -// ========================================================== -// ========================================================== - pub struct Regs<'a, I: Interface> { iface: &'a mut I, } @@ -72,13 +67,13 @@ impl<'a, I: Interface> Regs<'a, I> { pub fn bit_rate(&mut self) -> Reg<'_, I, BitRate> { Reg::new(self.iface, 4) } - pub fn iso14443a_nfc(&mut self) -> Reg<'_, I, Iso14443aNfc> { + pub fn iso14443a_nfc(&mut self) -> Reg<'_, I, Iso14443ANfc> { Reg::new(self.iface, 5) } - pub fn iso14443b_1(&mut self) -> Reg<'_, I, Iso14443b1> { + pub fn iso14443b_1(&mut self) -> Reg<'_, I, Iso14443B1> { Reg::new(self.iface, 6) } - pub fn iso14443b_2(&mut self) -> Reg<'_, I, Iso14443b2> { + pub fn iso14443b_2(&mut self) -> Reg<'_, I, Iso14443B2> { Reg::new(self.iface, 7) } pub fn passive_target(&mut self) -> Reg<'_, I, PassiveTarget> { @@ -123,13 +118,29 @@ impl<'a, I: Interface> Regs<'a, I> { pub fn ppon2(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 21) } - pub fn irq_mask(&mut self, n: u8) -> Reg<'_, I, u8> { - assert!(n < 4); - Reg::new(self.iface, 22 + n) + pub fn irq_mask_main(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 22) + } + pub fn irq_mask_timer_nfc(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 23) + } + pub fn irq_mask_error_wup(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 24) + } + pub fn irq_mask_target(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 25) + } + pub fn irq_main(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 26) + } + pub fn irq_timer_nfc(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 27) + } + pub fn irq_error_wup(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 28) } - pub fn irq_main(&mut self, n: u8) -> Reg<'_, I, u8> { - assert!(n < 4); - Reg::new(self.iface, 26 + n) + pub fn irq_target(&mut self) -> Reg<'_, I, u8> { + Reg::new(self.iface, 29) } pub fn fifo_status1(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 30) @@ -239,7 +250,7 @@ impl<'a, I: Interface> Regs<'a, I> { pub fn subc_start_time(&mut self) -> Reg<'_, I, SubcStartTime> { Reg::new(self.iface, 70) } - pub fn p2p_rx_conf(&mut self) -> Reg<'_, I, P2pRxConf> { + pub fn p2p_rx_conf(&mut self) -> Reg<'_, I, P2PRxConf> { Reg::new(self.iface, 75) } pub fn corr_conf1(&mut self) -> Reg<'_, I, CorrConf1> { @@ -288,851 +299,736 @@ impl<'a, I: Interface> Regs<'a, I> { #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct TxDriver(pub u8); -impl TxDriver { - pub const fn d_res(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; +pub struct AmplitudeMeasureConf(pub u8); +impl AmplitudeMeasureConf { + pub const fn am_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_am_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn am_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; val as u8 } - pub fn set_d_res(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u8) & 0x0f) << 0usize); + pub fn set_am_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; } - pub const fn am_mod(&self) -> TxDriverAmMod { - let val = (self.0 >> 4usize) & 0x0f; - TxDriverAmMod(val as u8) + pub const fn am_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } - pub fn set_am_mod(&mut self, val: TxDriverAmMod) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val.0 as u8) & 0x0f) << 4usize); + pub fn set_am_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn am_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_am_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for TxDriver { - fn default() -> TxDriver { - TxDriver(0) +impl Default for AmplitudeMeasureConf { + fn default() -> AmplitudeMeasureConf { + AmplitudeMeasureConf(0) } } -impl From for TxDriver { +impl From for AmplitudeMeasureConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: TxDriver) -> u8 { +impl From for u8 { + fn from(val: AmplitudeMeasureConf) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AuxMod(pub u8); -impl AuxMod { - pub const fn rfu0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_rfu0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn rfu1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - pub fn set_rfu1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); - } - pub const fn rfu2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 +pub struct Aux(pub u8); +impl Aux { + pub const fn nfc_n(&self) -> u8 { + let val = (self.0 >> 0_usize) & 2; + val as u8 } - pub fn set_rfu2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_nfc_n(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val as u8) & 2) << 0_usize; } - pub const fn res_am(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn dis_corr(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_res_am(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_dis_corr(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn lm_dri(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn mfaz_cl90(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_lm_dri(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_mfaz_cl90(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn lm_ext(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 + pub const fn nfc_id(&self) -> AuxNfcId { + let val = (self.0 >> 4_usize) & 2; + AuxNfcId(val as u8) } - pub fn set_lm_ext(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_nfc_id(&mut self, val: AuxNfcId) { + self.0 = (self.0 & !(2 << 4_usize)) | ((val.0 as u8) & 2) << 4_usize; } - pub const fn lm_ext_pol(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_lm_ext_pol(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn dis_reg_am(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn no_crc_rx(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_dis_reg_am(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_no_crc_rx(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for AuxMod { - fn default() -> AuxMod { - AuxMod(0) +impl Default for Aux { + fn default() -> Aux { + Aux(0) } } -impl From for AuxMod { +impl From for Aux { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AuxMod) -> u8 { +impl From for u8 { + fn from(val: Aux) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf2(pub u8); -impl RxConf2 { - pub const fn agc6_3(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_agc6_3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn agc_alg(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; +pub struct AuxDisplay(pub u8); +impl AuxDisplay { + pub const fn en_ac(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_agc_alg(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_en_ac(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn agc_m(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn en_peer(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_agc_m(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_en_peer(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn agc_en(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn rx_act(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_agc_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_rx_act(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn pulz_61(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn rx_on(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_pulz_61(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_rx_on(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn sqm_dyn(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + pub const fn osc_ok(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_sqm_dyn(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_osc_ok(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn amd_sel(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn tx_on(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_amd_sel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_tx_on(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn amd_sel_mixer(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn efd_o(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_amd_sel_mixer(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_efd_o(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn demod_mode(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn a_cha(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_demod_mode(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_a_cha(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RxConf2 { - fn default() -> RxConf2 { - RxConf2(0) +impl Default for AuxDisplay { + fn default() -> AuxDisplay { + AuxDisplay(0) } } -impl From for RxConf2 { +impl From for AuxDisplay { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf2) -> u8 { +impl From for u8 { + fn from(val: AuxDisplay) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SubcStartTime(pub u8); -impl SubcStartTime { - pub const fn sst(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - pub fn set_sst(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u8) & 0x1f) << 0usize); - } +pub struct AuxMod(pub u8); +impl AuxMod { pub const fn rfu0(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + let val = (self.0 >> 0_usize) & 1; val != 0 } pub fn set_rfu0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } pub const fn rfu1(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + let val = (self.0 >> 1_usize) & 1; val != 0 } pub fn set_rfu1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } pub const fn rfu2(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + let val = (self.0 >> 2_usize) & 1; val != 0 } pub fn set_rfu2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } -} -impl Default for SubcStartTime { - fn default() -> SubcStartTime { - SubcStartTime(0) + pub const fn res_am(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } -} -impl From for SubcStartTime { - fn from(val: u8) -> Self { - Self(val) + pub fn set_res_am(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } -} -impl From for u8 { - fn from(val: SubcStartTime) -> u8 { - val.0 + pub const fn lm_dri(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct RegulatorControl(pub u8); -impl RegulatorControl { - pub const fn mpsv(&self) -> RegulatorControlMpsv { - let val = (self.0 >> 0usize) & 0x07; - RegulatorControlMpsv(val as u8) + pub fn set_lm_dri(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub fn set_mpsv(&mut self, val: RegulatorControlMpsv) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u8) & 0x07) << 0usize); + pub const fn lm_ext(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } - pub const fn rege(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x0f; - val as u8 + pub fn set_lm_ext(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub fn set_rege(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 3usize)) | (((val as u8) & 0x0f) << 3usize); + pub const fn lm_ext_pol(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 } - pub const fn reg_s(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub fn set_lm_ext_pol(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn dis_reg_am(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_reg_s(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_dis_reg_am(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RegulatorControl { - fn default() -> RegulatorControl { - RegulatorControl(0) +impl Default for AuxMod { + fn default() -> AuxMod { + AuxMod(0) } } -impl From for RegulatorControl { +impl From for AuxMod { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RegulatorControl) -> u8 { +impl From for u8 { + fn from(val: AuxMod) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct EmdSupConf(pub u8); -impl EmdSupConf { - pub const fn emd_thld(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - pub fn set_emd_thld(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u8) & 0x0f) << 0usize); - } - pub const fn rfu0(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - pub fn set_rfu0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); - } - pub const fn rfu1(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - pub fn set_rfu1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); - } - pub const fn rx_start_emv(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 +pub struct BitRate(pub u8); +impl BitRate { + pub const fn rxrate(&self) -> BitRateE { + let val = (self.0 >> 0_usize) & 2; + BitRateE(val as u8) } - pub fn set_rx_start_emv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rxrate(&mut self, val: BitRateE) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; } - pub const fn emd_emv(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn txrate(&self) -> BitRateE { + let val = (self.0 >> 4_usize) & 2; + BitRateE(val as u8) } - pub fn set_emd_emv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_txrate(&mut self, val: BitRateE) { + self.0 = (self.0 & !(2 << 4_usize)) | ((val.0 as u8) & 2) << 4_usize; } } -impl Default for EmdSupConf { - fn default() -> EmdSupConf { - EmdSupConf(0) +impl Default for BitRate { + fn default() -> BitRate { + BitRate(0) } } -impl From for EmdSupConf { +impl From for BitRate { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: EmdSupConf) -> u8 { +impl From for u8 { + fn from(val: BitRate) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RssiResult(pub u8); -impl RssiResult { - pub const fn rssi_pm(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; +pub struct CapacitanceMeasureConf(pub u8); +impl CapacitanceMeasureConf { + pub const fn cm_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_cm_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn cm_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; val as u8 } - pub fn set_rssi_pm(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u8) & 0x0f) << 0usize); + pub fn set_cm_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; } - pub const fn rssi_am(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; + pub const fn cm_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_cm_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn cm_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; val as u8 } - pub fn set_rssi_am(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_cm_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for RssiResult { - fn default() -> RssiResult { - RssiResult(0) +impl Default for CapacitanceMeasureConf { + fn default() -> CapacitanceMeasureConf { + CapacitanceMeasureConf(0) } } -impl From for RssiResult { +impl From for CapacitanceMeasureConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RssiResult) -> u8 { +impl From for u8 { + fn from(val: CapacitanceMeasureConf) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CollisionStatus(pub u8); -impl CollisionStatus { - pub const fn c_pb(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_c_pb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn c_bit(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x07; +pub struct CapSensorControl(pub u8); +impl CapSensorControl { + pub const fn cs_g(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; val as u8 } - pub fn set_c_bit(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 1usize)) | (((val as u8) & 0x07) << 1usize); + pub fn set_cs_g(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; } - pub const fn c_byte(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; + pub const fn cs_mcal(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; val as u8 } - pub fn set_c_byte(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_cs_mcal(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; } } -impl Default for CollisionStatus { - fn default() -> CollisionStatus { - CollisionStatus(0) +impl Default for CapSensorControl { + fn default() -> CapSensorControl { + CapSensorControl(0) } } -impl From for CollisionStatus { +impl From for CapSensorControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CollisionStatus) -> u8 { +impl From for u8 { + fn from(val: CapSensorControl) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct StreamMode(pub u8); -impl StreamMode { - pub const fn stx(&self) -> StreamModeStx { - let val = (self.0 >> 0usize) & 0x07; - StreamModeStx(val as u8) - } - pub fn set_stx(&mut self, val: StreamModeStx) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u8) & 0x07) << 0usize); - } - pub const fn scp(&self) -> StreamModeScp { - let val = (self.0 >> 3usize) & 0x03; - StreamModeScp(val as u8) +pub struct CapSensorResult(pub u8); +impl CapSensorResult { + pub const fn cs_cal_err(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } - pub fn set_scp(&mut self, val: StreamModeScp) { - self.0 = (self.0 & !(0x03 << 3usize)) | (((val.0 as u8) & 0x03) << 3usize); + pub fn set_cs_cal_err(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn scf(&self) -> StreamModeScf { - let val = (self.0 >> 5usize) & 0x03; - StreamModeScf(val as u8) + pub const fn cs_cal_end(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } - pub fn set_scf(&mut self, val: StreamModeScf) { - self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u8) & 0x03) << 5usize); + pub fn set_cs_cal_end(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn cs_cal_val(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; + val as u8 } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_cs_cal_val(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; } } -impl Default for StreamMode { - fn default() -> StreamMode { - StreamMode(0) +impl Default for CapSensorResult { + fn default() -> CapSensorResult { + CapSensorResult(0) } } -impl From for StreamMode { +impl From for CapSensorResult { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: StreamMode) -> u8 { +impl From for u8 { + fn from(val: CapSensorResult) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct BitRate(pub u8); -impl BitRate { - pub const fn rxrate(&self) -> BitRateE { - let val = (self.0 >> 0usize) & 0x03; - BitRateE(val as u8) +pub struct CollisionStatus(pub u8); +impl CollisionStatus { + pub const fn c_pb(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub fn set_rxrate(&mut self, val: BitRateE) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u8) & 0x03) << 0usize); + pub fn set_c_pb(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn txrate(&self) -> BitRateE { - let val = (self.0 >> 4usize) & 0x03; - BitRateE(val as u8) + pub const fn c_bit(&self) -> u8 { + let val = (self.0 >> 1_usize) & 3; + val as u8 } - pub fn set_txrate(&mut self, val: BitRateE) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.0 as u8) & 0x03) << 4usize); + pub fn set_c_bit(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 1_usize)) | ((val as u8) & 3) << 1_usize; + } + pub const fn c_byte(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_c_byte(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for BitRate { - fn default() -> BitRate { - BitRate(0) +impl Default for CollisionStatus { + fn default() -> CollisionStatus { + CollisionStatus(0) } } -impl From for BitRate { +impl From for CollisionStatus { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: BitRate) -> u8 { +impl From for u8 { + fn from(val: CollisionStatus) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf3(pub u8); -impl RxConf3 { - pub const fn lf_op(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct CorrConf1(pub u8); +impl CorrConf1 { + pub const fn corr_s0(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_lf_op(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_corr_s0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn lf_en(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn corr_s1(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_lf_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); - } - pub const fn rg1_pm(&self) -> u8 { - let val = (self.0 >> 2usize) & 0x07; - val as u8 - } - pub fn set_rg1_pm(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 2usize)) | (((val as u8) & 0x07) << 2usize); - } - pub const fn rg1_am(&self) -> u8 { - let val = (self.0 >> 5usize) & 0x07; - val as u8 - } - pub fn set_rg1_am(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u8) & 0x07) << 5usize); - } -} -impl Default for RxConf3 { - fn default() -> RxConf3 { - RxConf3(0) - } -} -impl From for RxConf3 { - fn from(val: u8) -> Self { - Self(val) + pub fn set_corr_s1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } -} -impl From for u8 { - fn from(val: RxConf3) -> u8 { - val.0 + pub const fn corr_s2(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct IcIdentity(pub u8); -impl IcIdentity { - pub const fn ic_rev(&self) -> IcIdentityIcRev { - let val = (self.0 >> 0usize) & 0x07; - IcIdentityIcRev(val as u8) + pub fn set_corr_s2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub fn set_ic_rev(&mut self, val: IcIdentityIcRev) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u8) & 0x07) << 0usize); + pub const fn corr_s3(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } - pub const fn ic_type(&self) -> IcIdentityIcType { - let val = (self.0 >> 3usize) & 0x1f; - IcIdentityIcType(val as u8) + pub fn set_corr_s3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub fn set_ic_type(&mut self, val: IcIdentityIcType) { - self.0 = (self.0 & !(0x1f << 3usize)) | (((val.0 as u8) & 0x1f) << 3usize); + pub const fn corr_s4(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 } -} -impl Default for IcIdentity { - fn default() -> IcIdentity { - IcIdentity(0) + pub fn set_corr_s4(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } -} -impl From for IcIdentity { - fn from(val: u8) -> Self { - Self(val) + pub const fn corr_s5(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: IcIdentity) -> u8 { - val.0 + pub fn set_corr_s5(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct PtMod(pub u8); -impl PtMod { - pub const fn pt_res(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub const fn corr_s6(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 } - pub fn set_pt_res(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u8) & 0x0f) << 0usize); + pub fn set_corr_s6(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn ptm_res(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub const fn corr_s7(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub fn set_ptm_res(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_corr_s7(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for PtMod { - fn default() -> PtMod { - PtMod(0) +impl Default for CorrConf1 { + fn default() -> CorrConf1 { + CorrConf1(0) } } -impl From for PtMod { +impl From for CorrConf1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: PtMod) -> u8 { +impl From for u8 { + fn from(val: CorrConf1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct WupTimerControl(pub u8); -impl WupTimerControl { - pub const fn wcap(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct CorrConf2(pub u8); +impl CorrConf2 { + pub const fn corr_s8(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_wcap(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_corr_s8(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn wph(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn corr_s9(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_wph(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_corr_s9(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn wam(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn rfu0(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_wam(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_rfu0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn wto(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn rfu1(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_wto(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); - } - pub const fn wut(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x07; - val as u8 - } - pub fn set_wut(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u8) & 0x07) << 4usize); + pub fn set_rfu1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn wur(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn rfu2(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_wur(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); - } -} -impl Default for WupTimerControl { - fn default() -> WupTimerControl { - WupTimerControl(0) + pub fn set_rfu2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } -} -impl From for WupTimerControl { - fn from(val: u8) -> Self { - Self(val) + pub const fn rfu3(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: WupTimerControl) -> u8 { - val.0 + pub fn set_rfu3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FieldThresholdDeactv(pub u8); -impl FieldThresholdDeactv { - pub const fn rfe(&self) -> FieldThresholdDeactvRfe { - let val = (self.0 >> 0usize) & 0x0f; - FieldThresholdDeactvRfe(val as u8) + pub const fn rfu4(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 } - pub fn set_rfe(&mut self, val: FieldThresholdDeactvRfe) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.0 as u8) & 0x0f) << 0usize); + pub fn set_rfu4(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn trg(&self) -> FieldThresholdDeactvTrg { - let val = (self.0 >> 4usize) & 0x07; - FieldThresholdDeactvTrg(val as u8) + pub const fn rfu5(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub fn set_trg(&mut self, val: FieldThresholdDeactvTrg) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u8) & 0x07) << 4usize); + pub fn set_rfu5(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for FieldThresholdDeactv { - fn default() -> FieldThresholdDeactv { - FieldThresholdDeactv(0) +impl Default for CorrConf2 { + fn default() -> CorrConf2 { + CorrConf2(0) } } -impl From for FieldThresholdDeactv { +impl From for CorrConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: FieldThresholdDeactv) -> u8 { +impl From for u8 { + fn from(val: CorrConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IoConf1(pub u8); -impl IoConf1 { - pub const fn lf_clk_off(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_lf_clk_off(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn out_cl(&self) -> IoConf1OutCl { - let val = (self.0 >> 1usize) & 0x03; - IoConf1OutCl(val as u8) +pub struct EmdSupConf(pub u8); +impl EmdSupConf { + pub const fn emd_thld(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 } - pub fn set_out_cl(&mut self, val: IoConf1OutCl) { - self.0 = (self.0 & !(0x03 << 1usize)) | (((val.0 as u8) & 0x03) << 1usize); + pub fn set_emd_thld(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn rfu0(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_rfu0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn i2c_thd(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x03; - val as u8 + pub const fn rfu1(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } - pub fn set_i2c_thd(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u8) & 0x03) << 4usize); + pub fn set_rfu1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn rfo2(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn rx_start_emv(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_rfo2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rx_start_emv(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn single(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn emd_emv(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_single(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_emd_emv(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for IoConf1 { - fn default() -> IoConf1 { - IoConf1(0) +impl Default for EmdSupConf { + fn default() -> EmdSupConf { + EmdSupConf(0) } } -impl From for IoConf1 { +impl From for EmdSupConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IoConf1) -> u8 { +impl From for u8 { + fn from(val: EmdSupConf) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RegulatorResult(pub u8); -impl RegulatorResult { - pub const fn i_lim(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 +pub struct FieldThresholdActv(pub u8); +impl FieldThresholdActv { + pub const fn rfe(&self) -> FieldThresholdActvRfe { + let val = (self.0 >> 0_usize) & 4; + FieldThresholdActvRfe(val as u8) } - pub fn set_i_lim(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_rfe(&mut self, val: FieldThresholdActvRfe) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; } - pub const fn reg(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub const fn trg(&self) -> FieldThresholdActvTrg { + let val = (self.0 >> 4_usize) & 3; + FieldThresholdActvTrg(val as u8) } - pub fn set_reg(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_trg(&mut self, val: FieldThresholdActvTrg) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val.0 as u8) & 3) << 4_usize; } } -impl Default for RegulatorResult { - fn default() -> RegulatorResult { - RegulatorResult(0) +impl Default for FieldThresholdActv { + fn default() -> FieldThresholdActv { + FieldThresholdActv(0) } } -impl From for RegulatorResult { +impl From for FieldThresholdActv { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RegulatorResult) -> u8 { +impl From for u8 { + fn from(val: FieldThresholdActv) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443b2(pub u8); -impl Iso14443b2 { - pub const fn f_p(&self) -> Iso14443b2FP { - let val = (self.0 >> 0usize) & 0x03; - Iso14443b2FP(val as u8) - } - pub fn set_f_p(&mut self, val: Iso14443b2FP) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u8) & 0x03) << 0usize); - } - pub const fn no_eof(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - pub fn set_no_eof(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); - } - pub const fn no_sof(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 +pub struct FieldThresholdDeactv(pub u8); +impl FieldThresholdDeactv { + pub const fn rfe(&self) -> FieldThresholdDeactvRfe { + let val = (self.0 >> 0_usize) & 4; + FieldThresholdDeactvRfe(val as u8) } - pub fn set_no_sof(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_rfe(&mut self, val: FieldThresholdDeactvRfe) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; } - pub const fn tr1(&self) -> Iso14443b2Tr1 { - let val = (self.0 >> 6usize) & 0x03; - Iso14443b2Tr1(val as u8) + pub const fn trg(&self) -> FieldThresholdDeactvTrg { + let val = (self.0 >> 4_usize) & 3; + FieldThresholdDeactvTrg(val as u8) } - pub fn set_tr1(&mut self, val: Iso14443b2Tr1) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u8) & 0x03) << 6usize); + pub fn set_trg(&mut self, val: FieldThresholdDeactvTrg) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val.0 as u8) & 3) << 4_usize; } } -impl Default for Iso14443b2 { - fn default() -> Iso14443b2 { - Iso14443b2(0) +impl Default for FieldThresholdDeactv { + fn default() -> FieldThresholdDeactv { + FieldThresholdDeactv(0) } } -impl From for Iso14443b2 { +impl From for FieldThresholdDeactv { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443b2) -> u8 { +impl From for u8 { + fn from(val: FieldThresholdDeactv) -> u8 { val.0 } } @@ -1141,39 +1037,39 @@ impl From for u8 { pub struct FifoStatus2(pub u8); impl FifoStatus2 { pub const fn np_lb(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + let val = (self.0 >> 0_usize) & 1; val != 0 } pub fn set_np_lb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } pub const fn fifo_lb(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x07; + let val = (self.0 >> 1_usize) & 3; val as u8 } pub fn set_fifo_lb(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 1usize)) | (((val as u8) & 0x07) << 1usize); + self.0 = (self.0 & !(3 << 1_usize)) | ((val as u8) & 3) << 1_usize; } pub const fn fifo_ovr(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + let val = (self.0 >> 4_usize) & 1; val != 0 } pub fn set_fifo_ovr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } pub const fn fifo_unf(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + let val = (self.0 >> 5_usize) & 1; val != 0 } pub fn set_fifo_unf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } pub const fn fifo_b(&self) -> u8 { - let val = (self.0 >> 6usize) & 0x03; + let val = (self.0 >> 6_usize) & 2; val as u8 } pub fn set_fifo_b(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u8) & 0x03) << 6usize); + self.0 = (self.0 & !(2 << 6_usize)) | ((val as u8) & 2) << 6_usize; } } impl Default for FifoStatus2 { @@ -1193,372 +1089,386 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct PassiveTargetStatus(pub u8); -impl PassiveTargetStatus { - pub const fn pta_state(&self) -> PassiveTargetStatusPtaState { - let val = (self.0 >> 0usize) & 0x0f; - PassiveTargetStatusPtaState(val as u8) +pub struct GainRedState(pub u8); +impl GainRedState { + pub const fn gs_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 } - pub fn set_pta_state(&mut self, val: PassiveTargetStatusPtaState) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.0 as u8) & 0x0f) << 0usize); + pub fn set_gs_pm(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub const fn rfu3(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 + pub const fn gs_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub fn set_rfu3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_gs_am(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } - pub const fn rfu2(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 +} +impl Default for GainRedState { + fn default() -> GainRedState { + GainRedState(0) } - pub fn set_rfu2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); +} +impl From for GainRedState { + fn from(val: u8) -> Self { + Self(val) } - pub const fn rfu1(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 +} +impl From for u8 { + fn from(val: GainRedState) -> u8 { + val.0 } - pub fn set_rfu1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct IcIdentity(pub u8); +impl IcIdentity { + pub const fn ic_rev(&self) -> IcIdentityIcRev { + let val = (self.0 >> 0_usize) & 3; + IcIdentityIcRev(val as u8) } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub fn set_ic_rev(&mut self, val: IcIdentityIcRev) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub const fn ic_type(&self) -> IcIdentityIcType { + let val = (self.0 >> 3_usize) & 5; + IcIdentityIcType(val as u8) + } + pub fn set_ic_type(&mut self, val: IcIdentityIcType) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val.0 as u8) & 5) << 3_usize; } } -impl Default for PassiveTargetStatus { - fn default() -> PassiveTargetStatus { - PassiveTargetStatus(0) +impl Default for IcIdentity { + fn default() -> IcIdentity { + IcIdentity(0) } } -impl From for PassiveTargetStatus { +impl From for IcIdentity { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: PassiveTargetStatus) -> u8 { +impl From for u8 { + fn from(val: IcIdentity) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CorrConf1(pub u8); -impl CorrConf1 { - pub const fn corr_s0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_corr_s0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn corr_s1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - pub fn set_corr_s1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); - } - pub const fn corr_s2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; +pub struct IoConf1(pub u8); +impl IoConf1 { + pub const fn lf_clk_off(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_corr_s2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_lf_clk_off(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn corr_s3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 + pub const fn out_cl(&self) -> IoConf1OutCl { + let val = (self.0 >> 1_usize) & 2; + IoConf1OutCl(val as u8) } - pub fn set_corr_s3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_out_cl(&mut self, val: IoConf1OutCl) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val.0 as u8) & 2) << 1_usize; } - pub const fn corr_s4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_corr_s4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn corr_s5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 + pub const fn i2c_thd(&self) -> u8 { + let val = (self.0 >> 4_usize) & 2; + val as u8 } - pub fn set_corr_s5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_i2c_thd(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 4_usize)) | ((val as u8) & 2) << 4_usize; } - pub const fn corr_s6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn rfo2(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_corr_s6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rfo2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn corr_s7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn single(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_corr_s7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_single(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for CorrConf1 { - fn default() -> CorrConf1 { - CorrConf1(0) +impl Default for IoConf1 { + fn default() -> IoConf1 { + IoConf1(0) } } -impl From for CorrConf1 { +impl From for IoConf1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CorrConf1) -> u8 { +impl From for u8 { + fn from(val: IoConf1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct TxDriverStatus(pub u8); -impl TxDriverStatus { - pub const fn d_tim(&self) -> TxDriverStatusDTim { - let val = (self.0 >> 0usize) & 0x07; - TxDriverStatusDTim(val as u8) +pub struct IoConf2(pub u8); +impl IoConf2 { + pub const fn slow_up(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub fn set_d_tim(&mut self, val: TxDriverStatusDTim) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u8) & 0x07) << 0usize); + pub fn set_slow_up(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn am_ref_rf(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); - } - pub const fn d_rat(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub fn set_am_ref_rf(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub fn set_d_rat(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub const fn io_drv_lvl(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 } -} -impl Default for TxDriverStatus { - fn default() -> TxDriverStatus { - TxDriverStatus(0) + pub fn set_io_drv_lvl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } -} -impl From for TxDriverStatus { - fn from(val: u8) -> Self { - Self(val) + pub const fn miso_pd1(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 } -} -impl From for u8 { - fn from(val: TxDriverStatus) -> u8 { - val.0 + pub fn set_miso_pd1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct PhaseMeasureConf(pub u8); -impl PhaseMeasureConf { - pub const fn pm_ae(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + pub const fn miso_pd2(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_pm_ae(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_miso_pd2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn pm_aew(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x03; - val as u8 + pub const fn aat_en(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } - pub fn set_pm_aew(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u8) & 0x03) << 1usize); + pub fn set_aat_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn pm_aam(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn vspd_off(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_pm_aam(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_vspd_off(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn pm_d(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub const fn sup_3v(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub fn set_pm_d(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_sup_3v(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for PhaseMeasureConf { - fn default() -> PhaseMeasureConf { - PhaseMeasureConf(0) +impl Default for IoConf2 { + fn default() -> IoConf2 { + IoConf2(0) } } -impl From for PhaseMeasureConf { +impl From for IoConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: PhaseMeasureConf) -> u8 { +impl From for u8 { + fn from(val: IoConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct OvershootConf2(pub u8); -impl OvershootConf2 { - pub const fn ov_pattern(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; +pub struct Iso14443ANfc(pub u8); +impl Iso14443ANfc { + pub const fn antcl(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 + } + pub fn set_antcl(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; + } + pub const fn p_len(&self) -> u8 { + let val = (self.0 >> 1_usize) & 4; val as u8 } - pub fn set_ov_pattern(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u8) & 0xff) << 0usize); + pub fn set_p_len(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 1_usize)) | ((val as u8) & 4) << 1_usize; + } + pub const fn nfc_f0(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_nfc_f0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn no_rx_par(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_no_rx_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn no_tx_par(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_no_tx_par(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for OvershootConf2 { - fn default() -> OvershootConf2 { - OvershootConf2(0) +impl Default for Iso14443ANfc { + fn default() -> Iso14443ANfc { + Iso14443ANfc(0) } } -impl From for OvershootConf2 { +impl From for Iso14443ANfc { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: OvershootConf2) -> u8 { +impl From for u8 { + fn from(val: Iso14443ANfc) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct PassiveTarget(pub u8); -impl PassiveTarget { - pub const fn d_106_ac_a(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct Iso14443B1(pub u8); +impl Iso14443B1 { + pub const fn rx_st_om(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_d_106_ac_a(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_rx_st_om(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn half(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_half(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn d_212_424_1r(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn eof(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_d_212_424_1r(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn d_ac_ap2p(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn eof_11etu(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_d_ac_ap2p(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_eof_11etu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn fdel(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; + pub const fn sof_1(&self) -> Iso14443B1Sof1 { + let val = (self.0 >> 3_usize) & 1; + Iso14443B1Sof1(val as u8) + } + pub fn set_sof_1(&mut self, val: Iso14443B1Sof1) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val.0 as u8) & 1) << 3_usize; + } + pub const fn sof_0_11etu(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_sof_0_11etu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn sof_0_mak(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_sof_0_mak(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn egt(&self) -> u8 { + let val = (self.0 >> 5_usize) & 3; val as u8 } - pub fn set_fdel(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_egt(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; } } -impl Default for PassiveTarget { - fn default() -> PassiveTarget { - PassiveTarget(0) +impl Default for Iso14443B1 { + fn default() -> Iso14443B1 { + Iso14443B1(0) } } -impl From for PassiveTarget { +impl From for Iso14443B1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: PassiveTarget) -> u8 { +impl From for u8 { + fn from(val: Iso14443B1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct OpControl(pub u8); -impl OpControl { - pub const fn en_fd(&self) -> OpControlEnFd { - let val = (self.0 >> 0usize) & 0x03; - OpControlEnFd(val as u8) - } - pub fn set_en_fd(&mut self, val: OpControlEnFd) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u8) & 0x03) << 0usize); - } - pub const fn wu(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - pub fn set_wu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); - } - pub const fn tx_en(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - pub fn set_tx_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); - } - pub const fn rx_man(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 +pub struct Iso14443B2(pub u8); +impl Iso14443B2 { + pub const fn f_p(&self) -> Iso14443B2FP { + let val = (self.0 >> 0_usize) & 2; + Iso14443B2FP(val as u8) } - pub fn set_rx_man(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_f_p(&mut self, val: Iso14443B2FP) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; } - pub const fn rx_chn(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + pub const fn no_eof(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_rx_chn(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_no_eof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn rx_en(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn no_sof(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_rx_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_no_sof(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn en(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn tr1(&self) -> Iso14443B2Tr1 { + let val = (self.0 >> 6_usize) & 2; + Iso14443B2Tr1(val as u8) } - pub fn set_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_tr1(&mut self, val: Iso14443B2Tr1) { + self.0 = (self.0 & !(2 << 6_usize)) | ((val.0 as u8) & 2) << 6_usize; } } -impl Default for OpControl { - fn default() -> OpControl { - OpControl(0) +impl Default for Iso14443B2 { + fn default() -> Iso14443B2 { + Iso14443B2(0) } } -impl From for OpControl { +impl From for Iso14443B2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: OpControl) -> u8 { +impl From for u8 { + fn from(val: Iso14443B2) -> u8 { val.0 } } @@ -1567,39 +1477,39 @@ impl From for u8 { pub struct Mode(pub u8); impl Mode { pub const fn nfc_ar(&self) -> ModeNfcAr { - let val = (self.0 >> 0usize) & 0x03; + let val = (self.0 >> 0_usize) & 2; ModeNfcAr(val as u8) } pub fn set_nfc_ar(&mut self, val: ModeNfcAr) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u8) & 0x03) << 0usize); + self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; } pub const fn tr_am(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + let val = (self.0 >> 2_usize) & 1; val != 0 } pub fn set_tr_am(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } pub const fn om(&self) -> ModeOm { - let val = (self.0 >> 3usize) & 0x0f; + let val = (self.0 >> 3_usize) & 4; ModeOm(val as u8) } pub fn set_om(&mut self, val: ModeOm) { - self.0 = (self.0 & !(0x0f << 3usize)) | (((val.0 as u8) & 0x0f) << 3usize); + self.0 = (self.0 & !(4 << 3_usize)) | ((val.0 as u8) & 4) << 3_usize; } pub const fn targ(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + let val = (self.0 >> 7_usize) & 1; val != 0 } pub fn set_targ(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } pub const fn targ_targ(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + let val = (self.0 >> 7_usize) & 1; val != 0 } pub fn set_targ_targ(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } impl Default for Mode { @@ -1619,818 +1529,982 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct FieldThresholdActv(pub u8); -impl FieldThresholdActv { - pub const fn rfe(&self) -> FieldThresholdActvRfe { - let val = (self.0 >> 0usize) & 0x0f; - FieldThresholdActvRfe(val as u8) +pub struct Nfcip1BitRate(pub u8); +impl Nfcip1BitRate { + pub const fn mrt_on(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub fn set_rfe(&mut self, val: FieldThresholdActvRfe) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.0 as u8) & 0x0f) << 0usize); + pub fn set_mrt_on(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn trg(&self) -> FieldThresholdActvTrg { - let val = (self.0 >> 4usize) & 0x07; - FieldThresholdActvTrg(val as u8) + pub const fn nrt_on(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } - pub fn set_trg(&mut self, val: FieldThresholdActvTrg) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u8) & 0x07) << 4usize); + pub fn set_nrt_on(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn gpt_on(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_gpt_on(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn ppt2_on(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_ppt2_on(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn nfc_rate(&self) -> u8 { + let val = (self.0 >> 4_usize) & 2; + val as u8 + } + pub fn set_nfc_rate(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 4_usize)) | ((val as u8) & 2) << 4_usize; + } + pub const fn nfc_rfu0(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_nfc_rfu0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn nfc_rfu1(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_nfc_rfu1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for FieldThresholdActv { - fn default() -> FieldThresholdActv { - FieldThresholdActv(0) +impl Default for Nfcip1BitRate { + fn default() -> Nfcip1BitRate { + Nfcip1BitRate(0) } } -impl From for FieldThresholdActv { +impl From for Nfcip1BitRate { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: FieldThresholdActv) -> u8 { +impl From for u8 { + fn from(val: Nfcip1BitRate) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AmplitudeMeasureConf(pub u8); -impl AmplitudeMeasureConf { - pub const fn am_ae(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_am_ae(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn am_aew(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x03; +pub struct NumTxBytes2(pub u8); +impl NumTxBytes2 { + pub const fn nbtx(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; val as u8 } - pub fn set_am_aew(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u8) & 0x03) << 1usize); - } - pub const fn am_aam(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - pub fn set_am_aam(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_nbtx(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; } - pub const fn am_d(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; + pub const fn ntx(&self) -> u8 { + let val = (self.0 >> 3_usize) & 5; val as u8 } - pub fn set_am_d(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_ntx(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 3_usize)) | ((val as u8) & 5) << 3_usize; } } -impl Default for AmplitudeMeasureConf { - fn default() -> AmplitudeMeasureConf { - AmplitudeMeasureConf(0) +impl Default for NumTxBytes2 { + fn default() -> NumTxBytes2 { + NumTxBytes2(0) } } -impl From for AmplitudeMeasureConf { +impl From for NumTxBytes2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AmplitudeMeasureConf) -> u8 { +impl From for u8 { + fn from(val: NumTxBytes2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf1(pub u8); -impl RxConf1 { - pub const fn hz(&self) -> RxConf1Hz { - let val = (self.0 >> 0usize) & 0x0f; - RxConf1Hz(val as u8) +pub struct OpControl(pub u8); +impl OpControl { + pub const fn en_fd(&self) -> OpControlEnFd { + let val = (self.0 >> 0_usize) & 2; + OpControlEnFd(val as u8) } - pub fn set_hz(&mut self, val: RxConf1Hz) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.0 as u8) & 0x0f) << 0usize); + pub fn set_en_fd(&mut self, val: OpControlEnFd) { + self.0 = (self.0 & !(2 << 0_usize)) | ((val.0 as u8) & 2) << 0_usize; } - pub const fn z12k(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + pub const fn wu(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_z12k(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_wu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn h80(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn tx_en(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_h80(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_tx_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn h200(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn rx_man(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; + val != 0 + } + pub fn set_rx_man(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; + } + pub const fn rx_chn(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 + } + pub fn set_rx_chn(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn rx_en(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_rx_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn en(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_h200(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; + } +} +impl Default for OpControl { + fn default() -> OpControl { + OpControl(0) + } +} +impl From for OpControl { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: OpControl) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct OvershootConf1(pub u8); +impl OvershootConf1 { + pub const fn ov_pattern(&self) -> u8 { + let val = (self.0 >> 0_usize) & 6; + val as u8 + } + pub fn set_ov_pattern(&mut self, val: u8) { + self.0 = (self.0 & !(6 << 0_usize)) | ((val as u8) & 6) << 0_usize; } - pub const fn z600k(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn ov_tx_mode0(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_z600k(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); - } - pub const fn lp(&self) -> RxConf1Lp { - let val = (self.0 >> 4usize) & 0x07; - RxConf1Lp(val as u8) - } - pub fn set_lp(&mut self, val: RxConf1Lp) { - self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u8) & 0x07) << 4usize); + pub fn set_ov_tx_mode0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn ch_sel(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn ov_tx_mode1(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_ch_sel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_ov_tx_mode1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RxConf1 { - fn default() -> RxConf1 { - RxConf1(0) +impl Default for OvershootConf1 { + fn default() -> OvershootConf1 { + OvershootConf1(0) } } -impl From for RxConf1 { +impl From for OvershootConf1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf1) -> u8 { +impl From for u8 { + fn from(val: OvershootConf1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CapSensorResult(pub u8); -impl CapSensorResult { - pub const fn cs_cal_err(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - pub fn set_cs_cal_err(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); - } - pub const fn cs_cal_end(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - pub fn set_cs_cal_end(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); - } - pub const fn cs_cal_val(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x1f; +pub struct OvershootConf2(pub u8); +impl OvershootConf2 { + pub const fn ov_pattern(&self) -> u8 { + let val = (self.0 >> 0_usize) & 8; val as u8 } - pub fn set_cs_cal_val(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 3usize)) | (((val as u8) & 0x1f) << 3usize); + pub fn set_ov_pattern(&mut self, val: u8) { + self.0 = (self.0 & !(8 << 0_usize)) | ((val as u8) & 8) << 0_usize; } } -impl Default for CapSensorResult { - fn default() -> CapSensorResult { - CapSensorResult(0) +impl Default for OvershootConf2 { + fn default() -> OvershootConf2 { + OvershootConf2(0) } } -impl From for CapSensorResult { +impl From for OvershootConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CapSensorResult) -> u8 { +impl From for u8 { + fn from(val: OvershootConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CorrConf2(pub u8); -impl CorrConf2 { - pub const fn corr_s8(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct P2PRxConf(pub u8); +impl P2PRxConf { + pub const fn ask_thd(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_corr_s8(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_ask_thd(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn corr_s9(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn ask_rc0(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_corr_s9(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_ask_rc0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn rfu0(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn ask_rc1(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_rfu0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_ask_rc1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn rfu1(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn ook_thd0(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_rfu1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_ook_thd0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn rfu2(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn ook_thd1(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_rfu2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_ook_thd1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn rfu3(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + pub const fn ook_rc0(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_rfu3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_ook_rc0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn rfu4(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn ook_rc1(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_rfu4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_ook_rc1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn rfu5(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn ook_fd(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_rfu5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_ook_fd(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for CorrConf2 { - fn default() -> CorrConf2 { - CorrConf2(0) +impl Default for P2PRxConf { + fn default() -> P2PRxConf { + P2PRxConf(0) } } -impl From for CorrConf2 { +impl From for P2PRxConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CorrConf2) -> u8 { +impl From for u8 { + fn from(val: P2PRxConf) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct UndershootConf1(pub u8); -impl UndershootConf1 { - pub const fn un_pattern(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 +pub struct PassiveTarget(pub u8); +impl PassiveTarget { + pub const fn d_106_ac_a(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; + val != 0 } - pub fn set_un_pattern(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u8) & 0x3f) << 0usize); + pub fn set_d_106_ac_a(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn un_tx_mode0(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_un_tx_mode0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn un_tx_mode1(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn d_212_424_1r(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_un_tx_mode1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_d_212_424_1r(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn d_ac_ap2p(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_d_ac_ap2p(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn fdel(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_fdel(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for UndershootConf1 { - fn default() -> UndershootConf1 { - UndershootConf1(0) +impl Default for PassiveTarget { + fn default() -> PassiveTarget { + PassiveTarget(0) } } -impl From for UndershootConf1 { +impl From for PassiveTarget { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: UndershootConf1) -> u8 { +impl From for u8 { + fn from(val: PassiveTarget) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443b1(pub u8); -impl Iso14443b1 { - pub const fn rx_st_om(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct PassiveTargetStatus(pub u8); +impl PassiveTargetStatus { + pub const fn pta_state(&self) -> PassiveTargetStatusPtaState { + let val = (self.0 >> 0_usize) & 4; + PassiveTargetStatusPtaState(val as u8) + } + pub fn set_pta_state(&mut self, val: PassiveTargetStatusPtaState) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; + } + pub const fn rfu3(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_rx_st_om(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_rfu3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn half(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn rfu2(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_half(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_rfu2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn eof(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn rfu1(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_eof(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_rfu1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn eof_11etu(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_eof_11etu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } - pub const fn sof_1(&self) -> Iso14443b1Sof1 { - let val = (self.0 >> 3usize) & 0x01; - Iso14443b1Sof1(val as u8) +} +impl Default for PassiveTargetStatus { + fn default() -> PassiveTargetStatus { + PassiveTargetStatus(0) } - pub fn set_sof_1(&mut self, val: Iso14443b1Sof1) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u8) & 0x01) << 3usize); +} +impl From for PassiveTargetStatus { + fn from(val: u8) -> Self { + Self(val) } - pub const fn sof_0_11etu(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; +} +impl From for u8 { + fn from(val: PassiveTargetStatus) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct PhaseMeasureConf(pub u8); +impl PhaseMeasureConf { + pub const fn pm_ae(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_sof_0_11etu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_pm_ae(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn sof_0_mak(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn pm_aew(&self) -> u8 { + let val = (self.0 >> 1_usize) & 2; + val as u8 + } + pub fn set_pm_aew(&mut self, val: u8) { + self.0 = (self.0 & !(2 << 1_usize)) | ((val as u8) & 2) << 1_usize; + } + pub const fn pm_aam(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_sof_0_mak(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_pm_aam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn egt(&self) -> u8 { - let val = (self.0 >> 5usize) & 0x07; + pub const fn pm_d(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; val as u8 } - pub fn set_egt(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u8) & 0x07) << 5usize); + pub fn set_pm_d(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for Iso14443b1 { - fn default() -> Iso14443b1 { - Iso14443b1(0) +impl Default for PhaseMeasureConf { + fn default() -> PhaseMeasureConf { + PhaseMeasureConf(0) } } -impl From for Iso14443b1 { +impl From for PhaseMeasureConf { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443b1) -> u8 { +impl From for u8 { + fn from(val: PhaseMeasureConf) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct IoConf2(pub u8); -impl IoConf2 { - pub const fn slow_up(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_slow_up(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn am_ref_rf(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - pub fn set_am_ref_rf(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); +pub struct PtMod(pub u8); +impl PtMod { + pub const fn pt_res(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 } - pub const fn io_drv_lvl(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub fn set_pt_res(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub fn set_io_drv_lvl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub const fn ptm_res(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub const fn miso_pd1(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 + pub fn set_ptm_res(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } - pub fn set_miso_pd1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); +} +impl Default for PtMod { + fn default() -> PtMod { + PtMod(0) } - pub const fn miso_pd2(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 +} +impl From for PtMod { + fn from(val: u8) -> Self { + Self(val) } - pub fn set_miso_pd2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); +} +impl From for u8 { + fn from(val: PtMod) -> u8 { + val.0 } - pub const fn aat_en(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RegulatorControl(pub u8); +impl RegulatorControl { + pub const fn mpsv(&self) -> RegulatorControlMpsv { + let val = (self.0 >> 0_usize) & 3; + RegulatorControlMpsv(val as u8) } - pub fn set_aat_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_mpsv(&mut self, val: RegulatorControlMpsv) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; } - pub const fn sup_3v(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn rege(&self) -> u8 { + let val = (self.0 >> 3_usize) & 4; + val as u8 } - pub fn set_sup_3v(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_rege(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 3_usize)) | ((val as u8) & 4) << 3_usize; } - pub const fn vspd_off(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn reg_s(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_vspd_off(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_reg_s(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for IoConf2 { - fn default() -> IoConf2 { - IoConf2(0) +impl Default for RegulatorControl { + fn default() -> RegulatorControl { + RegulatorControl(0) } } -impl From for IoConf2 { +impl From for RegulatorControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IoConf2) -> u8 { +impl From for u8 { + fn from(val: RegulatorControl) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CapacitanceMeasureConf(pub u8); -impl CapacitanceMeasureConf { - pub const fn cm_ae(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_cm_ae(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn cm_aew(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x03; - val as u8 - } - pub fn set_cm_aew(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u8) & 0x03) << 1usize); - } - pub const fn cm_aam(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; +pub struct RegulatorResult(pub u8); +impl RegulatorResult { + pub const fn i_lim(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_cm_aam(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_i_lim(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn cm_d(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; + pub const fn reg(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; val as u8 } - pub fn set_cm_d(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_reg(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for CapacitanceMeasureConf { - fn default() -> CapacitanceMeasureConf { - CapacitanceMeasureConf(0) +impl Default for RegulatorResult { + fn default() -> RegulatorResult { + RegulatorResult(0) } } -impl From for CapacitanceMeasureConf { +impl From for RegulatorResult { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CapacitanceMeasureConf) -> u8 { +impl From for u8 { + fn from(val: RegulatorResult) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf4(pub u8); -impl RxConf4 { - pub const fn rg2_pm(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; +pub struct ResAmMod(pub u8); +impl ResAmMod { + pub const fn md_res(&self) -> u8 { + let val = (self.0 >> 0_usize) & 7; val as u8 } - pub fn set_rg2_pm(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u8) & 0x0f) << 0usize); + pub fn set_md_res(&mut self, val: u8) { + self.0 = (self.0 & !(7 << 0_usize)) | ((val as u8) & 7) << 0_usize; } - pub const fn rg2_am(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub const fn fa3_f(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 } - pub fn set_rg2_am(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_fa3_f(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for RxConf4 { - fn default() -> RxConf4 { - RxConf4(0) +impl Default for ResAmMod { + fn default() -> ResAmMod { + ResAmMod(0) } } -impl From for RxConf4 { +impl From for ResAmMod { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf4) -> u8 { +impl From for u8 { + fn from(val: ResAmMod) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct OvershootConf1(pub u8); -impl OvershootConf1 { - pub const fn ov_pattern(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; +pub struct RssiResult(pub u8); +impl RssiResult { + pub const fn rssi_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; val as u8 } - pub fn set_ov_pattern(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u8) & 0x3f) << 0usize); - } - pub const fn ov_tx_mode0(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - pub fn set_ov_tx_mode0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rssi_pm(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub const fn ov_tx_mode1(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn rssi_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub fn set_ov_tx_mode1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_rssi_am(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for OvershootConf1 { - fn default() -> OvershootConf1 { - OvershootConf1(0) +impl Default for RssiResult { + fn default() -> RssiResult { + RssiResult(0) } } -impl From for OvershootConf1 { +impl From for RssiResult { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: OvershootConf1) -> u8 { +impl From for u8 { + fn from(val: RssiResult) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct TxDriverTiming(pub u8); -impl TxDriverTiming { - pub const fn d_tim_m(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 +pub struct RxConf1(pub u8); +impl RxConf1 { + pub const fn hz(&self) -> RxConf1Hz { + let val = (self.0 >> 0_usize) & 4; + RxConf1Hz(val as u8) } - pub fn set_d_tim_m(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u8) & 0x07) << 0usize); + pub fn set_hz(&mut self, val: RxConf1Hz) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val.0 as u8) & 4) << 0_usize; } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn z12k(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_z12k(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn d_rat(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub const fn h80(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 } - pub fn set_d_rat(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_h80(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn h200(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; + val != 0 + } + pub fn set_h200(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; + } + pub const fn z600k(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; + val != 0 + } + pub fn set_z600k(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn lp(&self) -> RxConf1Lp { + let val = (self.0 >> 4_usize) & 3; + RxConf1Lp(val as u8) + } + pub fn set_lp(&mut self, val: RxConf1Lp) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val.0 as u8) & 3) << 4_usize; + } + pub const fn ch_sel(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_ch_sel(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for TxDriverTiming { - fn default() -> TxDriverTiming { - TxDriverTiming(0) +impl Default for RxConf1 { + fn default() -> RxConf1 { + RxConf1(0) } } -impl From for TxDriverTiming { +impl From for RxConf1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: TxDriverTiming) -> u8 { +impl From for u8 { + fn from(val: RxConf1) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct P2pRxConf(pub u8); -impl P2pRxConf { - pub const fn ask_thd(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct RxConf2(pub u8); +impl RxConf2 { + pub const fn agc6_3(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_ask_thd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_agc6_3(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn ask_rc0(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn agc_alg(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_ask_rc0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_agc_alg(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn ask_rc1(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn agc_m(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_ask_rc1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_agc_m(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn ook_thd0(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn agc_en(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_ook_thd0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_agc_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn ook_thd1(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn pulz_61(&self) -> bool { + let val = (self.0 >> 4_usize) & 1; val != 0 } - pub fn set_ook_thd1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + pub fn set_pulz_61(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } - pub const fn ook_rc0(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; + pub const fn sqm_dyn(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; val != 0 } - pub fn set_ook_rc0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_sqm_dyn(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; } - pub const fn ook_rc1(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn amd_sel(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_ook_rc1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_amd_sel(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn ook_fd(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn amd_sel_mixer(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_ook_fd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_amd_sel_mixer(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn demod_mode(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_demod_mode(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for P2pRxConf { - fn default() -> P2pRxConf { - P2pRxConf(0) +impl Default for RxConf2 { + fn default() -> RxConf2 { + RxConf2(0) } } -impl From for P2pRxConf { +impl From for RxConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: P2pRxConf) -> u8 { +impl From for u8 { + fn from(val: RxConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443aNfc(pub u8); -impl Iso14443aNfc { - pub const fn antcl(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct RxConf3(pub u8); +impl RxConf3 { + pub const fn lf_op(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_antcl(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_lf_op(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn p_len(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x0f; + pub const fn lf_en(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; + val != 0 + } + pub fn set_lf_en(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; + } + pub const fn rg1_pm(&self) -> u8 { + let val = (self.0 >> 2_usize) & 3; val as u8 } - pub fn set_p_len(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 1usize)) | (((val as u8) & 0x0f) << 1usize); + pub fn set_rg1_pm(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 2_usize)) | ((val as u8) & 3) << 2_usize; } - pub const fn nfc_f0(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 + pub const fn rg1_am(&self) -> u8 { + let val = (self.0 >> 5_usize) & 3; + val as u8 } - pub fn set_nfc_f0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_rg1_am(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 5_usize)) | ((val as u8) & 3) << 5_usize; } - pub const fn no_rx_par(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 +} +impl Default for RxConf3 { + fn default() -> RxConf3 { + RxConf3(0) + } +} +impl From for RxConf3 { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: RxConf3) -> u8 { + val.0 + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RxConf4(pub u8); +impl RxConf4 { + pub const fn rg2_pm(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; + val as u8 } - pub fn set_no_rx_par(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rg2_pm(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub const fn no_tx_par(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn rg2_am(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub fn set_no_tx_par(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_rg2_am(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for Iso14443aNfc { - fn default() -> Iso14443aNfc { - Iso14443aNfc(0) +impl Default for RxConf4 { + fn default() -> RxConf4 { + RxConf4(0) } } -impl From for Iso14443aNfc { +impl From for RxConf4 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443aNfc) -> u8 { +impl From for u8 { + fn from(val: RxConf4) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct UndershootConf2(pub u8); -impl UndershootConf2 { - pub const fn un_pattern(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 +pub struct StreamMode(pub u8); +impl StreamMode { + pub const fn stx(&self) -> StreamModeStx { + let val = (self.0 >> 0_usize) & 3; + StreamModeStx(val as u8) } - pub fn set_un_pattern(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u8) & 0xff) << 0usize); + pub fn set_stx(&mut self, val: StreamModeStx) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; + } + pub const fn scp(&self) -> StreamModeScp { + let val = (self.0 >> 3_usize) & 2; + StreamModeScp(val as u8) + } + pub fn set_scp(&mut self, val: StreamModeScp) { + self.0 = (self.0 & !(2 << 3_usize)) | ((val.0 as u8) & 2) << 3_usize; + } + pub const fn scf(&self) -> StreamModeScf { + let val = (self.0 >> 5_usize) & 2; + StreamModeScf(val as u8) + } + pub fn set_scf(&mut self, val: StreamModeScf) { + self.0 = (self.0 & !(2 << 5_usize)) | ((val.0 as u8) & 2) << 5_usize; + } + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for UndershootConf2 { - fn default() -> UndershootConf2 { - UndershootConf2(0) +impl Default for StreamMode { + fn default() -> StreamMode { + StreamMode(0) } } -impl From for UndershootConf2 { +impl From for StreamMode { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: UndershootConf2) -> u8 { +impl From for u8 { + fn from(val: StreamMode) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CapSensorControl(pub u8); -impl CapSensorControl { - pub const fn cs_g(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; +pub struct SubcStartTime(pub u8); +impl SubcStartTime { + pub const fn sst(&self) -> u8 { + let val = (self.0 >> 0_usize) & 5; val as u8 } - pub fn set_cs_g(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u8) & 0x07) << 0usize); + pub fn set_sst(&mut self, val: u8) { + self.0 = (self.0 & !(5 << 0_usize)) | ((val as u8) & 5) << 0_usize; } - pub const fn cs_mcal(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x1f; - val as u8 + pub const fn rfu0(&self) -> bool { + let val = (self.0 >> 5_usize) & 1; + val != 0 } - pub fn set_cs_mcal(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 3usize)) | (((val as u8) & 0x1f) << 3usize); + pub fn set_rfu0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; + } + pub const fn rfu1(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; + val != 0 + } + pub fn set_rfu1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; + } + pub const fn rfu2(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; + val != 0 + } + pub fn set_rfu2(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl Default for CapSensorControl { - fn default() -> CapSensorControl { - CapSensorControl(0) +impl Default for SubcStartTime { + fn default() -> SubcStartTime { + SubcStartTime(0) } } -impl From for CapSensorControl { +impl From for SubcStartTime { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: CapSensorControl) -> u8 { +impl From for u8 { + fn from(val: SubcStartTime) -> u8 { val.0 } } @@ -2439,11 +2513,11 @@ impl From for u8 { pub struct TestUnk(pub u8); impl TestUnk { pub const fn dis_overheat_prot(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + let val = (self.0 >> 4_usize) & 1; val != 0 } pub fn set_dis_overheat_prot(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } } impl Default for TestUnk { @@ -2463,83 +2537,49 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct NumTxBytes2(pub u8); -impl NumTxBytes2 { - pub const fn nbtx(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x07; - val as u8 - } - pub fn set_nbtx(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u8) & 0x07) << 0usize); - } - pub const fn ntx(&self) -> u8 { - let val = (self.0 >> 3usize) & 0x1f; - val as u8 - } - pub fn set_ntx(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 3usize)) | (((val as u8) & 0x1f) << 3usize); - } -} -impl Default for NumTxBytes2 { - fn default() -> NumTxBytes2 { - NumTxBytes2(0) - } -} -impl From for NumTxBytes2 { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: NumTxBytes2) -> u8 { - val.0 - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] pub struct TimerEmvControl(pub u8); impl TimerEmvControl { pub const fn nrt_step(&self) -> TimerEmvControlNrtStep { - let val = (self.0 >> 0usize) & 0x01; + let val = (self.0 >> 0_usize) & 1; TimerEmvControlNrtStep(val as u8) } pub fn set_nrt_step(&mut self, val: TimerEmvControlNrtStep) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u8) & 0x01) << 0usize); + self.0 = (self.0 & !(1 << 0_usize)) | ((val.0 as u8) & 1) << 0_usize; } pub const fn nrt_emv(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + let val = (self.0 >> 1_usize) & 1; val != 0 } pub fn set_nrt_emv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } pub const fn nrt_nfc(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + let val = (self.0 >> 2_usize) & 1; val != 0 } pub fn set_nrt_nfc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } pub const fn mrt_step(&self) -> TimerEmvControlMrtStep { - let val = (self.0 >> 3usize) & 0x01; + let val = (self.0 >> 3_usize) & 1; TimerEmvControlMrtStep(val as u8) } pub fn set_mrt_step(&mut self, val: TimerEmvControlMrtStep) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u8) & 0x01) << 3usize); + self.0 = (self.0 & !(1 << 3_usize)) | ((val.0 as u8) & 1) << 3_usize; } pub const fn rfu(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + let val = (self.0 >> 4_usize) & 1; val != 0 } pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); + self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; } pub const fn gptc(&self) -> TimerEmvControlGptc { - let val = (self.0 >> 5usize) & 0x07; + let val = (self.0 >> 5_usize) & 3; TimerEmvControlGptc(val as u8) } pub fn set_gptc(&mut self, val: TimerEmvControlGptc) { - self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u8) & 0x07) << 5usize); + self.0 = (self.0 & !(3 << 5_usize)) | ((val.0 as u8) & 3) << 5_usize; } } impl Default for TimerEmvControl { @@ -2559,339 +2599,293 @@ impl From for u8 { } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct GainRedState(pub u8); -impl GainRedState { - pub const fn gs_pm(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; +pub struct TxDriver(pub u8); +impl TxDriver { + pub const fn d_res(&self) -> u8 { + let val = (self.0 >> 0_usize) & 4; val as u8 } - pub fn set_gs_pm(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u8) & 0x0f) << 0usize); + pub fn set_d_res(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 0_usize)) | ((val as u8) & 4) << 0_usize; } - pub const fn gs_am(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x0f; - val as u8 + pub const fn am_mod(&self) -> TxDriverAmMod { + let val = (self.0 >> 4_usize) & 4; + TxDriverAmMod(val as u8) } - pub fn set_gs_am(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u8) & 0x0f) << 4usize); + pub fn set_am_mod(&mut self, val: TxDriverAmMod) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val.0 as u8) & 4) << 4_usize; } } -impl Default for GainRedState { - fn default() -> GainRedState { - GainRedState(0) +impl Default for TxDriver { + fn default() -> TxDriver { + TxDriver(0) } } -impl From for GainRedState { +impl From for TxDriver { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: GainRedState) -> u8 { +impl From for u8 { + fn from(val: TxDriver) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AuxDisplay(pub u8); -impl AuxDisplay { - pub const fn en_ac(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - pub fn set_en_ac(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); - } - pub const fn en_peer(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - pub fn set_en_peer(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); - } - pub const fn rx_act(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - pub fn set_rx_act(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); - } - pub const fn rx_on(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - pub fn set_rx_on(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); - } - pub const fn osc_ok(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - pub fn set_osc_ok(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u8) & 0x01) << 4usize); - } - pub const fn tx_on(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 +pub struct TxDriverStatus(pub u8); +impl TxDriverStatus { + pub const fn d_tim(&self) -> TxDriverStatusDTim { + let val = (self.0 >> 0_usize) & 3; + TxDriverStatusDTim(val as u8) } - pub fn set_tx_on(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u8) & 0x01) << 5usize); + pub fn set_d_tim(&mut self, val: TxDriverStatusDTim) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val.0 as u8) & 3) << 0_usize; } - pub const fn efd_o(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_efd_o(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn a_cha(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn d_rat(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 } - pub fn set_a_cha(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_d_rat(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for AuxDisplay { - fn default() -> AuxDisplay { - AuxDisplay(0) +impl Default for TxDriverStatus { + fn default() -> TxDriverStatus { + TxDriverStatus(0) } } -impl From for AuxDisplay { +impl From for TxDriverStatus { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AuxDisplay) -> u8 { +impl From for u8 { + fn from(val: TxDriverStatus) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct ResAmMod(pub u8); -impl ResAmMod { - pub const fn md_res(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x7f; +pub struct TxDriverTiming(pub u8); +impl TxDriverTiming { + pub const fn d_tim_m(&self) -> u8 { + let val = (self.0 >> 0_usize) & 3; val as u8 } - pub fn set_md_res(&mut self, val: u8) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u8) & 0x7f) << 0usize); + pub fn set_d_tim_m(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 0_usize)) | ((val as u8) & 3) << 0_usize; } - pub const fn fa3_f(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn rfu(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_fa3_f(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_rfu(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; + } + pub const fn d_rat(&self) -> u8 { + let val = (self.0 >> 4_usize) & 4; + val as u8 + } + pub fn set_d_rat(&mut self, val: u8) { + self.0 = (self.0 & !(4 << 4_usize)) | ((val as u8) & 4) << 4_usize; } } -impl Default for ResAmMod { - fn default() -> ResAmMod { - ResAmMod(0) +impl Default for TxDriverTiming { + fn default() -> TxDriverTiming { + TxDriverTiming(0) } } -impl From for ResAmMod { +impl From for TxDriverTiming { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: ResAmMod) -> u8 { +impl From for u8 { + fn from(val: TxDriverTiming) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Aux(pub u8); -impl Aux { - pub const fn nfc_n(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x03; +pub struct UndershootConf1(pub u8); +impl UndershootConf1 { + pub const fn un_pattern(&self) -> u8 { + let val = (self.0 >> 0_usize) & 6; val as u8 } - pub fn set_nfc_n(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u8) & 0x03) << 0usize); + pub fn set_un_pattern(&mut self, val: u8) { + self.0 = (self.0 & !(6 << 0_usize)) | ((val as u8) & 6) << 0_usize; } - pub const fn dis_corr(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn un_tx_mode0(&self) -> bool { + let val = (self.0 >> 6_usize) & 1; val != 0 } - pub fn set_dis_corr(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_un_tx_mode0(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; } - pub const fn mfaz_cl90(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn un_tx_mode1(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_mfaz_cl90(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); - } - pub const fn nfc_id(&self) -> AuxNfcId { - let val = (self.0 >> 4usize) & 0x03; - AuxNfcId(val as u8) + pub fn set_un_tx_mode1(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } - pub fn set_nfc_id(&mut self, val: AuxNfcId) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.0 as u8) & 0x03) << 4usize); +} +impl Default for UndershootConf1 { + fn default() -> UndershootConf1 { + UndershootConf1(0) } - pub const fn rfu(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 +} +impl From for UndershootConf1 { + fn from(val: u8) -> Self { + Self(val) } - pub fn set_rfu(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); +} +impl From for u8 { + fn from(val: UndershootConf1) -> u8 { + val.0 } - pub const fn no_crc_rx(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct UndershootConf2(pub u8); +impl UndershootConf2 { + pub const fn un_pattern(&self) -> u8 { + let val = (self.0 >> 0_usize) & 8; + val as u8 } - pub fn set_no_crc_rx(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); + pub fn set_un_pattern(&mut self, val: u8) { + self.0 = (self.0 & !(8 << 0_usize)) | ((val as u8) & 8) << 0_usize; } } -impl Default for Aux { - fn default() -> Aux { - Aux(0) +impl Default for UndershootConf2 { + fn default() -> UndershootConf2 { + UndershootConf2(0) } } -impl From for Aux { +impl From for UndershootConf2 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Aux) -> u8 { +impl From for u8 { + fn from(val: UndershootConf2) -> u8 { val.0 } } #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Nfcip1BitRate(pub u8); -impl Nfcip1BitRate { - pub const fn mrt_on(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; +pub struct WupTimerControl(pub u8); +impl WupTimerControl { + pub const fn wcap(&self) -> bool { + let val = (self.0 >> 0_usize) & 1; val != 0 } - pub fn set_mrt_on(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u8) & 0x01) << 0usize); + pub fn set_wcap(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; } - pub const fn nrt_on(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; + pub const fn wph(&self) -> bool { + let val = (self.0 >> 1_usize) & 1; val != 0 } - pub fn set_nrt_on(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u8) & 0x01) << 1usize); + pub fn set_wph(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; } - pub const fn gpt_on(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; + pub const fn wam(&self) -> bool { + let val = (self.0 >> 2_usize) & 1; val != 0 } - pub fn set_gpt_on(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u8) & 0x01) << 2usize); + pub fn set_wam(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; } - pub const fn ppt2_on(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn wto(&self) -> bool { + let val = (self.0 >> 3_usize) & 1; val != 0 } - pub fn set_ppt2_on(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u8) & 0x01) << 3usize); + pub fn set_wto(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; } - pub const fn nfc_rate(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x03; + pub const fn wut(&self) -> u8 { + let val = (self.0 >> 4_usize) & 3; val as u8 } - pub fn set_nfc_rate(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u8) & 0x03) << 4usize); - } - pub const fn nfc_rfu0(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - pub fn set_nfc_rfu0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u8) & 0x01) << 6usize); + pub fn set_wut(&mut self, val: u8) { + self.0 = (self.0 & !(3 << 4_usize)) | ((val as u8) & 3) << 4_usize; } - pub const fn nfc_rfu1(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; + pub const fn wur(&self) -> bool { + let val = (self.0 >> 7_usize) & 1; val != 0 } - pub fn set_nfc_rfu1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u8) & 0x01) << 7usize); - } -} -impl Default for Nfcip1BitRate { - fn default() -> Nfcip1BitRate { - Nfcip1BitRate(0) - } -} -impl From for Nfcip1BitRate { - fn from(val: u8) -> Self { - Self(val) + pub fn set_wur(&mut self, val: bool) { + self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; } } -impl From for u8 { - fn from(val: Nfcip1BitRate) -> u8 { - val.0 +impl Default for WupTimerControl { + fn default() -> WupTimerControl { + WupTimerControl(0) } } -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct Iso14443b2FP(pub u8); -impl Iso14443b2FP { - pub const _48: Self = Self(0); - pub const _64: Self = Self(0x01); - pub const _80: Self = Self(0x02); - pub const _96: Self = Self(0x03); -} -impl From for Iso14443b2FP { +impl From for WupTimerControl { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443b2FP) -> u8 { +impl From for u8 { + fn from(val: WupTimerControl) -> u8 { val.0 } } #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct TimerEmvControlNrtStep(pub u8); -impl TimerEmvControlNrtStep { - pub const _64FC: Self = Self(0); - pub const _4096_FC: Self = Self(0x01); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct AuxNfcId(pub u8); +impl AuxNfcId { + pub const _4BYTES: Self = Self(0x00); + pub const _7BYTES: Self = Self(0x01); } -impl From for TimerEmvControlNrtStep { +impl From for AuxNfcId { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: TimerEmvControlNrtStep) -> u8 { +impl From for u8 { + fn from(val: AuxNfcId) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct StreamModeStx(pub u8); -impl StreamModeStx { - pub const _106: Self = Self(0); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct BitRateE(pub u8); +impl BitRateE { + pub const _106: Self = Self(0x00); pub const _212: Self = Self(0x01); pub const _424: Self = Self(0x02); pub const _848: Self = Self(0x03); } -impl From for StreamModeStx { +impl From for BitRateE { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: StreamModeStx) -> u8 { +impl From for u8 { + fn from(val: BitRateE) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct FieldThresholdDeactvRfe(pub u8); -impl FieldThresholdDeactvRfe { - pub const _75MV: Self = Self(0); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct FieldThresholdActvRfe(pub u8); +impl FieldThresholdActvRfe { + pub const _75MV: Self = Self(0x00); pub const _105MV: Self = Self(0x01); pub const _150MV: Self = Self(0x02); pub const _205MV: Self = Self(0x03); @@ -2908,66 +2902,78 @@ impl FieldThresholdDeactvRfe { pub const _175MV: Self = Self(0x0e); pub const _250MV: Self = Self(0x0f); } -impl From for FieldThresholdDeactvRfe { +impl From for FieldThresholdActvRfe { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: FieldThresholdDeactvRfe) -> u8 { +impl From for u8 { + fn from(val: FieldThresholdActvRfe) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct IcIdentityIcType(pub u8); -impl IcIdentityIcType { - pub const ST25R3916: Self = Self(0x05); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct FieldThresholdActvTrg(pub u8); +impl FieldThresholdActvTrg { + pub const _75MV: Self = Self(0x00); + pub const _105MV: Self = Self(0x01); + pub const _150MV: Self = Self(0x02); + pub const _205MV: Self = Self(0x03); + pub const _290MV: Self = Self(0x04); + pub const _400MV: Self = Self(0x05); + pub const _560MV: Self = Self(0x06); + pub const _800MV: Self = Self(0x07); } -impl From for IcIdentityIcType { +impl From for FieldThresholdActvTrg { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: IcIdentityIcType) -> u8 { +impl From for u8 { + fn from(val: FieldThresholdActvTrg) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct PassiveTargetStatusPtaState(pub u8); -impl PassiveTargetStatusPtaState { - pub const POWER_OFF: Self = Self(0); - pub const IDLE: Self = Self(0x01); - pub const READY_L1: Self = Self(0x02); - pub const READY_L2: Self = Self(0x03); - pub const RFU4: Self = Self(0x04); - pub const ACTIVE: Self = Self(0x05); - pub const RFU6: Self = Self(0x06); - pub const RFU7: Self = Self(0x07); - pub const RFU8: Self = Self(0x08); - pub const HALT: Self = Self(0x09); - pub const READY_L1_X: Self = Self(0x0a); - pub const READY_L2_X: Self = Self(0x0b); - pub const RFU12: Self = Self(0x0c); - pub const ACTIVE_X: Self = Self(0x0d); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct FieldThresholdDeactvRfe(pub u8); +impl FieldThresholdDeactvRfe { + pub const _75MV: Self = Self(0x00); + pub const _105MV: Self = Self(0x01); + pub const _150MV: Self = Self(0x02); + pub const _205MV: Self = Self(0x03); + pub const _290MV: Self = Self(0x04); + pub const _400MV: Self = Self(0x05); + pub const _560MV: Self = Self(0x06); + pub const _800MV: Self = Self(0x07); + pub const _25MV: Self = Self(0x08); + pub const _33MV: Self = Self(0x09); + pub const _47MV: Self = Self(0x0a); + pub const _64MV: Self = Self(0x0b); + pub const _90MV: Self = Self(0x0c); + pub const _125MV: Self = Self(0x0d); + pub const _175MV: Self = Self(0x0e); + pub const _250MV: Self = Self(0x0f); } -impl From for PassiveTargetStatusPtaState { +impl From for FieldThresholdDeactvRfe { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: PassiveTargetStatusPtaState) -> u8 { +impl From for u8 { + fn from(val: FieldThresholdDeactvRfe) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct FieldThresholdActvRfe(pub u8); -impl FieldThresholdActvRfe { - pub const _75MV: Self = Self(0); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct FieldThresholdDeactvTrg(pub u8); +impl FieldThresholdDeactvTrg { + pub const _75MV: Self = Self(0x00); pub const _105MV: Self = Self(0x01); pub const _150MV: Self = Self(0x02); pub const _205MV: Self = Self(0x03); @@ -2975,30 +2981,23 @@ impl FieldThresholdActvRfe { pub const _400MV: Self = Self(0x05); pub const _560MV: Self = Self(0x06); pub const _800MV: Self = Self(0x07); - pub const _25MV: Self = Self(0x08); - pub const _33MV: Self = Self(0x09); - pub const _47MV: Self = Self(0x0a); - pub const _64MV: Self = Self(0x0b); - pub const _90MV: Self = Self(0x0c); - pub const _125MV: Self = Self(0x0d); - pub const _175MV: Self = Self(0x0e); - pub const _250MV: Self = Self(0x0f); } -impl From for FieldThresholdActvRfe { +impl From for FieldThresholdDeactvTrg { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: FieldThresholdActvRfe) -> u8 { +impl From for u8 { + fn from(val: FieldThresholdDeactvTrg) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct IcIdentityIcRev(pub u8); impl IcIdentityIcRev { - pub const V0: Self = Self(0); + pub const V0: Self = Self(0x00); } impl From for IcIdentityIcRev { fn from(val: u8) -> Self { @@ -3010,30 +3009,29 @@ impl From for u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct OpControlEnFd(pub u8); -impl OpControlEnFd { - pub const EFD_OFF: Self = Self(0); - pub const MANUAL_EFD_CA: Self = Self(0x01); - pub const MANUAL_EFD_PDT: Self = Self(0x02); - pub const AUTO_EFD: Self = Self(0x03); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct IcIdentityIcType(pub u8); +impl IcIdentityIcType { + pub const ST25R3916: Self = Self(0x05); } -impl From for OpControlEnFd { +impl From for IcIdentityIcType { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: OpControlEnFd) -> u8 { +impl From for u8 { + fn from(val: IcIdentityIcType) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct IoConf1OutCl(pub u8); impl IoConf1OutCl { - pub const _3_39_MHZ: Self = Self(0); + pub const _3_39_MHZ: Self = Self(0x00); pub const _6_78_MHZ: Self = Self(0x01); pub const _13_86_MHZ: Self = Self(0x02); pub const DISABLED: Self = Self(0x03); @@ -3048,127 +3046,165 @@ impl From for u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct Iso14443b1Sof1(pub u8); -impl Iso14443b1Sof1 { - pub const _2ETU: Self = Self(0); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B1Sof1(pub u8); +impl Iso14443B1Sof1 { + pub const _2ETU: Self = Self(0x00); pub const _3ETU: Self = Self(0x01); } -impl From for Iso14443b1Sof1 { +impl From for Iso14443B1Sof1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443b1Sof1) -> u8 { +impl From for u8 { + fn from(val: Iso14443B1Sof1) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct RxConf1Hz(pub u8); -impl RxConf1Hz { - pub const _60_400KHZ: Self = Self(0); - pub const _12_200KHZ: Self = Self(0x01); - pub const _40_80KHZ: Self = Self(0x02); - pub const _12_80KHZ: Self = Self(0x03); - pub const _60_200KHZ: Self = Self(0x04); - pub const _12_200KHZ_ALT: Self = Self(0x05); - pub const _600_400KHZ: Self = Self(0x08); - pub const _600_200KHZ: Self = Self(0x0c); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B2FP(pub u8); +impl Iso14443B2FP { + pub const _48: Self = Self(0x00); + pub const _64: Self = Self(0x01); + pub const _80: Self = Self(0x02); + pub const _96: Self = Self(0x03); } -impl From for RxConf1Hz { +impl From for Iso14443B2FP { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: RxConf1Hz) -> u8 { +impl From for u8 { + fn from(val: Iso14443B2FP) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct StreamModeScp(pub u8); -impl StreamModeScp { - pub const _1PULSE: Self = Self(0); - pub const _2PULSES: Self = Self(0x01); - pub const _4PULSES: Self = Self(0x02); - pub const _8PULSES: Self = Self(0x03); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct Iso14443B2Tr1(pub u8); +impl Iso14443B2Tr1 { + pub const _80FS80FS: Self = Self(0x00); + pub const _64FS32FS: Self = Self(0x01); } -impl From for StreamModeScp { +impl From for Iso14443B2Tr1 { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: StreamModeScp) -> u8 { +impl From for u8 { + fn from(val: Iso14443B2Tr1) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct ModeNfcAr(pub u8); impl ModeNfcAr { - pub const OFF: Self = Self(0); + pub const FALSE: Self = Self(0x00); pub const AUTO_RX: Self = Self(0x01); pub const EOF: Self = Self(0x02); pub const RFU: Self = Self(0x03); } -impl From for ModeNfcAr { +impl From for ModeNfcAr { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: ModeNfcAr) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct ModeOm(pub u8); +impl ModeOm { + pub const INI_NFC: Self = Self(0x00); + pub const INI_ISO14443A: Self = Self(0x01); + pub const TARG_NFCA: Self = Self(0x01); + pub const INI_ISO14443B: Self = Self(0x02); + pub const TARG_NFCB: Self = Self(0x02); + pub const INI_FELICA: Self = Self(0x03); + pub const INI_TOPAZ: Self = Self(0x04); + pub const TARG_NFCF: Self = Self(0x04); + pub const TARG_NFCIP: Self = Self(0x07); + pub const INI_SUBCARRIER_STREAM: Self = Self(0x0e); + pub const INI_BPSK_STREAM: Self = Self(0x0f); +} +impl From for ModeOm { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: ModeNfcAr) -> u8 { +impl From for u8 { + fn from(val: ModeOm) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct TimerEmvControlGptc(pub u8); -impl TimerEmvControlGptc { - pub const NO_TRIGGER: Self = Self(0); - pub const ERX: Self = Self(0x01); - pub const SRX: Self = Self(0x02); - pub const ETX_NFC: Self = Self(0x03); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct OpControlEnFd(pub u8); +impl OpControlEnFd { + pub const EFD_OFF: Self = Self(0x00); + pub const MANUAL_EFD_CA: Self = Self(0x01); + pub const MANUAL_EFD_PDT: Self = Self(0x02); + pub const AUTO_EFD: Self = Self(0x03); } -impl From for TimerEmvControlGptc { +impl From for OpControlEnFd { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: TimerEmvControlGptc) -> u8 { +impl From for u8 { + fn from(val: OpControlEnFd) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct BitRateE(pub u8); -impl BitRateE { - pub const _106: Self = Self(0); - pub const _212: Self = Self(0x01); - pub const _424: Self = Self(0x02); - pub const _848: Self = Self(0x03); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct PassiveTargetStatusPtaState(pub u8); +impl PassiveTargetStatusPtaState { + pub const POWER_OFF: Self = Self(0x00); + pub const IDLE: Self = Self(0x01); + pub const READY_L1: Self = Self(0x02); + pub const READY_L2: Self = Self(0x03); + pub const RFU4: Self = Self(0x04); + pub const ACTIVE: Self = Self(0x05); + pub const RFU6: Self = Self(0x06); + pub const RFU7: Self = Self(0x07); + pub const RFU8: Self = Self(0x08); + pub const HALT: Self = Self(0x09); + pub const READY_L1_X: Self = Self(0x0a); + pub const READY_L2_X: Self = Self(0x0b); + pub const RFU12: Self = Self(0x0c); + pub const ACTIVE_X: Self = Self(0x0d); } -impl From for BitRateE { +impl From for PassiveTargetStatusPtaState { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: BitRateE) -> u8 { +impl From for u8 { + fn from(val: PassiveTargetStatusPtaState) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct RegulatorControlMpsv(pub u8); impl RegulatorControlMpsv { - pub const VDD: Self = Self(0); + pub const VDD: Self = Self(0x00); pub const VDD_A: Self = Self(0x01); pub const VDD_D: Self = Self(0x02); pub const VDD_RF: Self = Self(0x03); @@ -3187,103 +3223,58 @@ impl From for u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct RxConf1Lp(pub u8); -impl RxConf1Lp { - pub const _1200KHZ: Self = Self(0); - pub const _600KHZ: Self = Self(0x01); - pub const _300KHZ: Self = Self(0x02); - pub const _2000KHZ: Self = Self(0x04); - pub const _7000KHZ: Self = Self(0x05); -} -impl From for RxConf1Lp { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: RxConf1Lp) -> u8 { - val.0 - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct TxDriverAmMod(pub u8); -impl TxDriverAmMod { - pub const _5PERCENT: Self = Self(0); - pub const _6PERCENT: Self = Self(0x01); - pub const _7PERCENT: Self = Self(0x02); - pub const _8PERCENT: Self = Self(0x03); - pub const _9PERCENT: Self = Self(0x04); - pub const _10PERCENT: Self = Self(0x05); - pub const _11PERCENT: Self = Self(0x06); - pub const _12PERCENT: Self = Self(0x07); - pub const _13PERCENT: Self = Self(0x08); - pub const _14PERCENT: Self = Self(0x09); - pub const _15PERCENT: Self = Self(0x0a); - pub const _17PERCENT: Self = Self(0x0b); - pub const _19PERCENT: Self = Self(0x0c); - pub const _22PERCENT: Self = Self(0x0d); - pub const _26PERCENT: Self = Self(0x0e); - pub const _40PERCENT: Self = Self(0x0f); -} -impl From for TxDriverAmMod { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: TxDriverAmMod) -> u8 { - val.0 - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct AuxNfcId(pub u8); -impl AuxNfcId { - pub const _4BYTES: Self = Self(0); - pub const _7BYTES: Self = Self(0x01); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct RxConf1Hz(pub u8); +impl RxConf1Hz { + pub const _60_400KHZ: Self = Self(0x00); + pub const _12_200KHZ: Self = Self(0x01); + pub const _40_80KHZ: Self = Self(0x02); + pub const _12_80KHZ: Self = Self(0x03); + pub const _60_200KHZ: Self = Self(0x04); + pub const _12_200KHZ_ALT: Self = Self(0x05); + pub const _600_400KHZ: Self = Self(0x08); + pub const _600_200KHZ: Self = Self(0x0c); } -impl From for AuxNfcId { +impl From for RxConf1Hz { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: AuxNfcId) -> u8 { +impl From for u8 { + fn from(val: RxConf1Hz) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct FieldThresholdDeactvTrg(pub u8); -impl FieldThresholdDeactvTrg { - pub const _75MV: Self = Self(0); - pub const _105MV: Self = Self(0x01); - pub const _150MV: Self = Self(0x02); - pub const _205MV: Self = Self(0x03); - pub const _290MV: Self = Self(0x04); - pub const _400MV: Self = Self(0x05); - pub const _560MV: Self = Self(0x06); - pub const _800MV: Self = Self(0x07); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct RxConf1Lp(pub u8); +impl RxConf1Lp { + pub const _1200KHZ: Self = Self(0x00); + pub const _600KHZ: Self = Self(0x01); + pub const _300KHZ: Self = Self(0x02); + pub const _2000KHZ: Self = Self(0x04); + pub const _7000KHZ: Self = Self(0x05); } -impl From for FieldThresholdDeactvTrg { +impl From for RxConf1Lp { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: FieldThresholdDeactvTrg) -> u8 { +impl From for u8 { + fn from(val: RxConf1Lp) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct StreamModeScf(pub u8); impl StreamModeScf { - pub const BPSK848: Self = Self(0); - pub const SC212: Self = Self(0); + pub const BPSK848: Self = Self(0x00); + pub const SC212: Self = Self(0x00); pub const BPSK1695: Self = Self(0x01); pub const SC424: Self = Self(0x01); pub const BPSK3390: Self = Self(0x02); @@ -3301,60 +3292,72 @@ impl From for u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct ModeOm(pub u8); -impl ModeOm { - pub const INI_NFC: Self = Self(0); - pub const INI_ISO14443A: Self = Self(0x01); - pub const TARG_NFCA: Self = Self(0x01); - pub const INI_ISO14443B: Self = Self(0x02); - pub const TARG_NFCB: Self = Self(0x02); - pub const INI_FELICA: Self = Self(0x03); - pub const INI_TOPAZ: Self = Self(0x04); - pub const TARG_NFCF: Self = Self(0x04); - pub const TARG_NFCIP: Self = Self(0x07); - pub const INI_SUBCARRIER_STREAM: Self = Self(0x0e); - pub const INI_BPSK_STREAM: Self = Self(0x0f); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct StreamModeScp(pub u8); +impl StreamModeScp { + pub const _1PULSE: Self = Self(0x00); + pub const _2PULSES: Self = Self(0x01); + pub const _4PULSES: Self = Self(0x02); + pub const _8PULSES: Self = Self(0x03); } -impl From for ModeOm { +impl From for StreamModeScp { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: ModeOm) -> u8 { +impl From for u8 { + fn from(val: StreamModeScp) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct FieldThresholdActvTrg(pub u8); -impl FieldThresholdActvTrg { - pub const _75MV: Self = Self(0); - pub const _105MV: Self = Self(0x01); - pub const _150MV: Self = Self(0x02); - pub const _205MV: Self = Self(0x03); - pub const _290MV: Self = Self(0x04); - pub const _400MV: Self = Self(0x05); - pub const _560MV: Self = Self(0x06); - pub const _800MV: Self = Self(0x07); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct StreamModeStx(pub u8); +impl StreamModeStx { + pub const _106: Self = Self(0x00); + pub const _212: Self = Self(0x01); + pub const _424: Self = Self(0x02); + pub const _848: Self = Self(0x03); } -impl From for FieldThresholdActvTrg { +impl From for StreamModeStx { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: FieldThresholdActvTrg) -> u8 { +impl From for u8 { + fn from(val: StreamModeStx) -> u8 { + val.0 + } +} + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct TimerEmvControlGptc(pub u8); +impl TimerEmvControlGptc { + pub const NO_TRIGGER: Self = Self(0x00); + pub const ERX: Self = Self(0x01); + pub const SRX: Self = Self(0x02); + pub const ETX_NFC: Self = Self(0x03); +} +impl From for TimerEmvControlGptc { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: TimerEmvControlGptc) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct TimerEmvControlMrtStep(pub u8); impl TimerEmvControlMrtStep { - pub const _64: Self = Self(0); + pub const _64: Self = Self(0x00); pub const _512: Self = Self(0x01); } impl From for TimerEmvControlMrtStep { @@ -3367,28 +3370,30 @@ impl From for u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct Iso14443b2Tr1(pub u8); -impl Iso14443b2Tr1 { - pub const _80FS80FS: Self = Self(0); - pub const _64FS32FS: Self = Self(0x01); +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct TimerEmvControlNrtStep(pub u8); +impl TimerEmvControlNrtStep { + pub const _64FC: Self = Self(0x00); + pub const _4096_FC: Self = Self(0x01); } -impl From for Iso14443b2Tr1 { +impl From for TimerEmvControlNrtStep { fn from(val: u8) -> Self { Self(val) } } -impl From for u8 { - fn from(val: Iso14443b2Tr1) -> u8 { +impl From for u8 { + fn from(val: TimerEmvControlNrtStep) -> u8 { val.0 } } + #[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] pub struct TxDriverStatusDTim(pub u8); impl TxDriverStatusDTim { - pub const SLOW: Self = Self(0); + pub const SLOW: Self = Self(0x00); pub const MEDIUM_SLOW: Self = Self(0x01); pub const NOMINAL: Self = Self(0x02); pub const MEDIUM_FAST: Self = Self(0x03); @@ -3404,3 +3409,35 @@ impl From for u8 { val.0 } } + +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug)] +pub struct TxDriverAmMod(pub u8); +impl TxDriverAmMod { + pub const _5PERCENT: Self = Self(0x00); + pub const _6PERCENT: Self = Self(0x01); + pub const _7PERCENT: Self = Self(0x02); + pub const _8PERCENT: Self = Self(0x03); + pub const _9PERCENT: Self = Self(0x04); + pub const _10PERCENT: Self = Self(0x05); + pub const _11PERCENT: Self = Self(0x06); + pub const _12PERCENT: Self = Self(0x07); + pub const _13PERCENT: Self = Self(0x08); + pub const _14PERCENT: Self = Self(0x09); + pub const _15PERCENT: Self = Self(0x0a); + pub const _17PERCENT: Self = Self(0x0b); + pub const _19PERCENT: Self = Self(0x0c); + pub const _22PERCENT: Self = Self(0x0d); + pub const _26PERCENT: Self = Self(0x0e); + pub const _40PERCENT: Self = Self(0x0f); +} +impl From for TxDriverAmMod { + fn from(val: u8) -> Self { + Self(val) + } +} +impl From for u8 { + fn from(val: TxDriverAmMod) -> u8 { + val.0 + } +} diff --git a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml index 6bc8d8c..8c6d1e7 100644 --- a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml +++ b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3911b.yaml @@ -1,442 +1,416 @@ block/REGS: items: - name: IO_CONF1 + description: IO configuration register 1 byte_offset: 0 bit_size: 8 - access: ReadWrite - description: IO configuration register 1 fieldset: IO_CONF1 - name: IO_CONF2 + description: IO configuration register 2 byte_offset: 1 bit_size: 8 - access: ReadWrite - description: IO configuration register 2 fieldset: IO_CONF2 - name: OP_CONTROL + description: Operation control register byte_offset: 2 bit_size: 8 - access: ReadWrite - description: Operation control register fieldset: OP_CONTROL - name: MODE + description: Mode definition register byte_offset: 3 bit_size: 8 - access: ReadWrite - description: Mode definition register fieldset: MODE - name: BIT_RATE + description: Bit rate definition register byte_offset: 4 bit_size: 8 - access: ReadWrite - description: Bit rate definition register fieldset: BIT_RATE - name: ISO14443A_NFC + description: ISO14443A and NFC 106kb/s settings register byte_offset: 5 bit_size: 8 - access: ReadWrite - description: ISO14443A and NFC 106kb/s settings register fieldset: ISO14443A_NFC - name: ISO14443B_1 + description: ISO14443B settings register 1 byte_offset: 6 bit_size: 8 - access: ReadWrite - description: ISO14443B settings register 1 fieldset: ISO14443B_1 - name: ISO14443B_2 + description: ISO14443B and FeliCa settings register byte_offset: 7 bit_size: 8 - access: ReadWrite - description: ISO14443B and FeliCa settings register fieldset: ISO14443B_2 - name: STREAM_MODE + description: Stream mode definition register byte_offset: 8 bit_size: 8 - access: ReadWrite - description: Stream mode definition register fieldset: STREAM_MODE - name: AUX + description: Auxiliary definition register byte_offset: 9 bit_size: 8 - access: ReadWrite - description: Auxiliary definition register fieldset: AUX - name: RX_CONF1 + description: Receiver configuration register 1 byte_offset: 10 bit_size: 8 - access: ReadWrite - description: Receiver configuration register 1 fieldset: RX_CONF1 - name: RX_CONF2 + description: Receiver configuration register 2 byte_offset: 11 bit_size: 8 - access: ReadWrite - description: Receiver configuration register 2 fieldset: RX_CONF2 - name: RX_CONF3 + description: Receiver configuration register 3 byte_offset: 12 bit_size: 8 - access: ReadWrite - description: Receiver configuration register 3 fieldset: RX_CONF3 - name: RX_CONF4 + description: Receiver configuration register 4 byte_offset: 13 bit_size: 8 - access: ReadWrite - description: Receiver configuration register 4 fieldset: RX_CONF4 - name: MASK_RX_TIMER + description: Mask receive timer register byte_offset: 14 bit_size: 8 - access: ReadWrite - description: Mask receive timer register fieldset: MASK_RX_TIMER - name: NO_RESPONSE_TIMER1 + description: No-response timer register 1 byte_offset: 15 bit_size: 8 - access: ReadWrite - description: No-response timer register 1 fieldset: NO_RESPONSE_TIMER1 - name: NO_RESPONSE_TIMER2 + description: No-response timer register 2 byte_offset: 16 bit_size: 8 - access: ReadWrite - description: No-response timer register 2 - name: GPT_NRT_CTRL + description: General purpose and no-response timer control register byte_offset: 17 bit_size: 8 - access: ReadWrite - description: General purpose and no-response timer control register fieldset: GPT_NRT_CTRL - name: GPT1 + description: General purpose timer register 1 byte_offset: 18 bit_size: 8 - access: ReadWrite - description: General purpose timer register 1 - name: GPT2 + description: General purpose timer register 2 byte_offset: 19 bit_size: 8 - access: ReadWrite - description: General purpose timer register 2 - name: IRQ_MASK_MAIN + description: Main interrupt register byte_offset: 20 bit_size: 8 - access: ReadWrite - description: Main interrupt register fieldset: IRQ_MASK_MAIN - name: IRQ_MASK_TIMER_NFC + description: Mask timer and NFC interrupt register byte_offset: 21 bit_size: 8 - access: ReadWrite - description: Mask timer and NFC interrupt register fieldset: IRQ_MASK_TIMER_NFC - name: IRQ_MASK_ERROR_WUP + description: Mask error and wake-up interrupt register byte_offset: 22 bit_size: 8 - access: ReadWrite - description: Mask error and wake-up interrupt register fieldset: IRQ_MASK_ERROR_WUP - name: IRQ_MAIN + description: Main interrupt register byte_offset: 23 - bit_size: 8 access: Read - description: Main interrupt register + bit_size: 8 fieldset: IRQ_MAIN - name: IRQ_TIMER_NFC + description: Mask timer and NFC interrupt register byte_offset: 24 - bit_size: 8 access: Read - description: Mask timer and NFC interrupt register + bit_size: 8 fieldset: IRQ_TIMER_NFC - name: IRQ_ERROR_WUP + description: Error and wake-up interrupt register byte_offset: 25 - bit_size: 8 access: Read - description: Error and wake-up interrupt register + bit_size: 8 - name: FIFO_STATUS1 + description: FIFO status register 1 byte_offset: 26 - bit_size: 8 access: Read - description: FIFO status register 1 + bit_size: 8 - name: FIFO_STATUS2 + description: FIFO status register 2 byte_offset: 27 - bit_size: 8 access: Read - description: FIFO status register 2 + bit_size: 8 fieldset: FIFO_STATUS2 - name: COLLISION_STATUS + description: Collision display register byte_offset: 28 - bit_size: 8 access: Read - description: Collision display register + bit_size: 8 fieldset: COLLISION_STATUS - name: NUM_TX_BYTES1 + description: Number of transmitted bytes register 1 byte_offset: 29 bit_size: 8 - access: ReadWrite - description: Number of transmitted bytes register 1 - name: NUM_TX_BYTES2 + description: Number of transmitted bytes register 2 byte_offset: 30 bit_size: 8 - access: ReadWrite - description: Number of transmitted bytes register 2 fieldset: NUM_TX_BYTES2 - name: NFCIP1_BIT_RATE_DISP + description: NFCIP bit rate detection display register byte_offset: 31 - bit_size: 8 access: Read - description: NFCIP bit rate detection display register + bit_size: 8 fieldset: NFCIP1_BIT_RATE_DISP - name: AD_CONV_RESULT + description: A/D converter output register byte_offset: 32 - bit_size: 8 access: Read - description: A/D converter output register + bit_size: 8 - name: ANT_TUNE_CTRL + description: Antenna calibration control register byte_offset: 33 bit_size: 8 - access: ReadWrite - description: Antenna calibration control register fieldset: ANT_TUNE_CTRL - name: ANT_TUNE_TARGET + description: Antenna calibration target register byte_offset: 34 bit_size: 8 - access: ReadWrite - description: Antenna calibration target register - name: ANT_TUNE_DISP + description: Antenna calibration display register byte_offset: 35 - bit_size: 8 access: Read - description: Antenna calibration display register + bit_size: 8 fieldset: ANT_TUNE_DISP - name: AM_MOD_DEPTH_CTRL + description: AM modulation depth control register byte_offset: 36 bit_size: 8 - access: ReadWrite - description: AM modulation depth control register fieldset: AM_MOD_DEPTH_CTRL - name: AM_MOD_DEPTH_DISP + description: AM modulation depth display register byte_offset: 37 - bit_size: 8 access: Read - description: AM modulation depth display register + bit_size: 8 - name: RFO_AM_MOD_LEVEL_DEF + description: RFO AM modulated level definition register byte_offset: 38 bit_size: 8 - access: ReadWrite - description: RFO AM modulated level definition register fieldset: RFO_AM_LEVEL_DEF - name: RFO_NORMAL_LEVEL_DEF + description: RFO normal level definition register byte_offset: 39 bit_size: 8 - access: ReadWrite - description: RFO normal level definition register fieldset: RFO_AM_LEVEL_DEF - name: EXT_FIELD_DET_THR + description: External field detector threshold register byte_offset: 41 bit_size: 8 - access: ReadWrite - description: External field detector threshold register fieldset: EXT_FIELD_DET_THR - name: REGULATOR_VOLT_CONTROL + description: Regulator voltage control register byte_offset: 42 bit_size: 8 - access: ReadWrite - description: Regulator voltage control register fieldset: REGULATOR_VOLT_CONTROL - name: REGULATOR_AND_TIM_DISP + description: Regulator and timer display register byte_offset: 43 - bit_size: 8 access: Read - description: Regulator and timer display register + bit_size: 8 fieldset: REGULATOR_AND_TIM_DISP - name: RSSI_RESULT + description: RSSI display register byte_offset: 44 - bit_size: 8 access: Read - description: RSSI display register + bit_size: 8 fieldset: RSSI_RESULT - name: GAIN_REDU_STATE + description: Gain reduction state register byte_offset: 45 - bit_size: 8 access: Read - description: Gain reduction state register + bit_size: 8 fieldset: GAIN_REDU_STATE - name: CAP_SENSOR_CONTROL + description: Capacitive sensor control register byte_offset: 46 bit_size: 8 - access: ReadWrite - description: Capacitive sensor control register fieldset: CAP_SENSOR_CONTROL - name: CAP_SENSOR_DISP + description: Capacitive sensor display register byte_offset: 47 - bit_size: 8 access: Read - description: Capacitive sensor display register + bit_size: 8 fieldset: CAP_SENSOR_DISP - name: AUX_DISPLAY + description: Auxiliary display register byte_offset: 48 - bit_size: 8 access: Read - description: Auxiliary display register + bit_size: 8 fieldset: AUX_DISPLAY - name: WUP_TIMER_CONTROL + description: Wake-up timer control register byte_offset: 49 bit_size: 8 - access: ReadWrite - description: Wake-up timer control register fieldset: WUP_TIMER_CONTROL - name: AMPLITUDE_MEASURE_CONF + description: Amplitude measurement configuration register byte_offset: 50 bit_size: 8 - access: ReadWrite - description: Amplitude measurement configuration register fieldset: AMPLITUDE_MEASURE_CONF - name: AMPLITUDE_MEASURE_REF + description: Amplitude measurement reference register byte_offset: 51 bit_size: 8 - access: ReadWrite - description: Amplitude measurement reference register - name: AMPLITUDE_MEASURE_AUTO_AVG_DISP + description: Amplitude measurement auto-averaging display byte_offset: 52 - bit_size: 8 access: Read - description: Amplitude measurement auto-averaging display + bit_size: 8 - name: AMPLITUDE_MEASURE_DISP + description: Amplitude measurement display byte_offset: 53 - bit_size: 8 access: Read - description: Amplitude measurement display + bit_size: 8 - name: PHASE_MEASURE_CONF + description: Phase measurement configuration byte_offset: 54 bit_size: 8 - access: ReadWrite - description: Phase measurement configuration fieldset: PHASE_MEASURE_CONF - name: PHASE_MEASURE_REF + description: Phase measurement reference byte_offset: 55 bit_size: 8 - access: ReadWrite - description: Phase measurement reference - name: PHASE_MEASURE_AUTO_AVG_DISP + description: Phase measurement auto-averaging display byte_offset: 56 - bit_size: 8 access: Read - description: Phase measurement auto-averaging display + bit_size: 8 - name: PHASE_MEASURE_DISP + description: Phase measurement display byte_offset: 57 - bit_size: 8 access: Read - description: Phase measurement display + bit_size: 8 - name: CAPACITANCE_MEASURE_CONF + description: Capacitance measurement configuration byte_offset: 58 bit_size: 8 - access: ReadWrite - description: Capacitance measurement configuration fieldset: CAPACITANCE_MEASURE_CONF - name: CAPACITANCE_MEASURE_REF + description: Capacitance measurement reference byte_offset: 59 bit_size: 8 - access: ReadWrite - description: Capacitance measurement reference - name: CAPACITANCE_MEASURE_AUTO_AVG_DISP + description: Capacitance measurement auto-averaging display byte_offset: 60 - bit_size: 8 access: Read - description: Capacitance measurement auto-averaging display + bit_size: 8 - name: CAPACITANCE_MEASURE_DISP + description: Capacitance measurement display byte_offset: 61 - bit_size: 8 access: Read - description: Capacitance measurement display + bit_size: 8 - name: IC_IDENTITY + description: IC identity register byte_offset: 63 - bit_size: 8 access: Read - description: IC identity register + bit_size: 8 fieldset: IC_IDENTITY -fieldset/IO_CONF1: +fieldset/AMPLITUDE_MEASURE_CONF: bit_size: 8 fields: - - name: lf_clk_off + - name: am_ae bit_offset: 0 bit_size: 1 - - name: out_cl + - name: am_aew bit_offset: 1 bit_size: 2 - enum: IO_CONF1_out_cl - - name: osc + - name: am_aam bit_offset: 3 bit_size: 1 - default: 1 - - name: fifo_lt + - name: am_d bit_offset: 4 - bit_size: 2 - - name: rfo2 - bit_offset: 6 + bit_size: 4 +fieldset/AM_MOD_DEPTH_CTRL: + bit_size: 8 + fields: + - name: modd + bit_offset: 1 + bit_size: 6 + - name: am_s + bit_offset: 7 bit_size: 1 - - name: single +fieldset/ANT_TUNE_CTRL: + bit_size: 8 + fields: + - name: tre + bit_offset: 3 + bit_size: 4 + - name: trim_s bit_offset: 7 bit_size: 1 -fieldset/IO_CONF2: +fieldset/ANT_TUNE_DISP: bit_size: 8 fields: - - name: slow_up - bit_offset: 0 + - name: tri_err + bit_offset: 3 bit_size: 1 - - name: io_18 + - name: tri + bit_offset: 4 + bit_size: 4 +fieldset/AUX: + bit_size: 8 + fields: + - name: nfc_n + bit_offset: 0 + bit_size: 2 + - name: rx_tol bit_offset: 2 bit_size: 1 - - name: miso_pd1 + - name: ook_hr bit_offset: 3 bit_size: 1 - - name: miso_pd2 + - name: en_fd bit_offset: 4 bit_size: 1 - - name: vspd_off + - name: tr_am + bit_offset: 5 + bit_size: 1 + - name: crc_2_fifo bit_offset: 6 bit_size: 1 - - name: sup_3v + - name: no_crc_rx bit_offset: 7 bit_size: 1 -fieldset/OP_CONTROL: +fieldset/AUX_DISPLAY: bit_size: 8 fields: - - name: wu + - name: en_ac + bit_offset: 0 + bit_size: 1 + - name: nfc_t + bit_offset: 1 + bit_size: 1 + - name: rx_act bit_offset: 2 bit_size: 1 - - name: tx_en + - name: rx_on bit_offset: 3 bit_size: 1 - - name: rx_man + - name: osc_ok bit_offset: 4 bit_size: 1 - - name: rx_chn + - name: tx_on bit_offset: 5 bit_size: 1 - - name: rx_en + - name: efd_o bit_offset: 6 bit_size: 1 - - name: en + - name: a_cha bit_offset: 7 bit_size: 1 -fieldset/MODE: +fieldset/BIT_RATE: bit_size: 8 fields: - - name: nfc_ar - bit_offset: 0 - bit_size: 1 - - name: om - bit_offset: 3 - bit_size: 4 - enum: MODE_om - default: 1 - - name: targ - bit_offset: 7 - bit_size: 1 -fieldset/BIT_RATE: - bit_size: 8 - fields: - - name: rxrate + - name: rxrate bit_offset: 0 bit_size: 4 enum: BIT_RATE_E @@ -444,462 +418,493 @@ fieldset/BIT_RATE: bit_offset: 4 bit_size: 4 enum: BIT_RATE_E -fieldset/ISO14443A_NFC: +fieldset/CAPACITANCE_MEASURE_CONF: bit_size: 8 fields: - - name: antcl + - name: cm_ae bit_offset: 0 bit_size: 1 - - name: p_len + - name: cm_aew bit_offset: 1 - bit_size: 4 - - name: nfc_f0 - bit_offset: 5 - bit_size: 1 - - name: no_rx_par - bit_offset: 6 - bit_size: 1 - - name: no_tx_par - bit_offset: 7 + bit_size: 2 + - name: cm_aam + bit_offset: 3 bit_size: 1 -fieldset/ISO14443B_1: + - name: cm_d + bit_offset: 4 + bit_size: 4 +fieldset/CAP_SENSOR_CONTROL: bit_size: 8 fields: - - name: rx_st_om + - name: cs_g bit_offset: 0 - bit_size: 1 - - name: half + bit_size: 3 + - name: cs_mcal + bit_offset: 3 + bit_size: 5 +fieldset/CAP_SENSOR_DISP: + bit_size: 8 + fields: + - name: cs_cal_err bit_offset: 1 bit_size: 1 - - name: eof + - name: cs_cal_end bit_offset: 2 bit_size: 1 - - name: sof_1 + - name: cs_cal_val bit_offset: 3 + bit_size: 5 +fieldset/COLLISION_STATUS: + bit_size: 8 + fields: + - name: c_pb + bit_offset: 0 bit_size: 1 - enum: ISO14443B_1_sof_1 - - name: sof_0 - bit_offset: 4 - bit_size: 1 - enum: ISO14443B_1_sof_0 - - name: egt - bit_offset: 5 + - name: c_bit + bit_offset: 1 bit_size: 3 -fieldset/ISO14443B_2: + - name: c_byte + bit_offset: 4 + bit_size: 4 +fieldset/EXT_FIELD_DET_THR: bit_size: 8 fields: - - name: f_p + - name: rfe_t bit_offset: 0 - bit_size: 2 - enum: ISO14443B_2_f_p - - name: phc_th - bit_offset: 2 - bit_size: 1 - - name: eof_12 - bit_offset: 3 - bit_size: 1 - - name: no_eof + bit_size: 4 + enum: THRESHOLD_DEF_2 + - name: trg_l bit_offset: 4 + bit_size: 3 + enum: THRESHOLD_DEF_1 +fieldset/FIFO_STATUS2: + bit_size: 8 + fields: + - name: np_lb + bit_offset: 0 bit_size: 1 - - name: no_sof + - name: fifo_lb + bit_offset: 1 + bit_size: 3 + - name: fifo_ovr bit_offset: 5 bit_size: 1 - - name: tr1 + - name: fifo_unf bit_offset: 6 - bit_size: 2 - enum: ISO14443B_2_tr1 -fieldset/STREAM_MODE: + bit_size: 1 +fieldset/GAIN_REDU_STATE: bit_size: 8 fields: - - name: stx + - name: gs_pm bit_offset: 0 + bit_size: 4 + - name: gs_am + bit_offset: 4 + bit_size: 4 +fieldset/GPT_NRT_CTRL: + bit_size: 8 + fields: + - name: nrt_step + bit_offset: 0 + bit_size: 1 + enum: TIMER_EMV_CONTROL_nrt_step + - name: nrt_emv + bit_offset: 1 + bit_size: 1 + - name: gptc + bit_offset: 5 bit_size: 3 - enum: STREAM_MODE_stx - - name: scp + enum: TIMER_EMV_CONTROL_gptc +fieldset/IC_IDENTITY: + bit_size: 8 + fields: + - name: ic_rev + bit_offset: 0 + bit_size: 3 + enum: IC_IDENTITY_ic_rev + - name: ic_type bit_offset: 3 - bit_size: 2 - enum: STREAM_MODE_scp - - name: scf - bit_offset: 5 - bit_size: 2 - enum: STREAM_MODE_scf -fieldset/AUX: + bit_size: 5 + enum: IC_IDENTITY_ic_type +fieldset/IO_CONF1: bit_size: 8 fields: - - name: nfc_n + - name: lf_clk_off bit_offset: 0 - bit_size: 2 - - name: rx_tol - bit_offset: 2 bit_size: 1 - - name: ook_hr + - name: out_cl + bit_offset: 1 + bit_size: 2 + enum: IO_CONF1_out_cl + - name: osc bit_offset: 3 bit_size: 1 - - name: en_fd + - name: fifo_lt bit_offset: 4 - bit_size: 1 - - name: tr_am - bit_offset: 5 - bit_size: 1 - - name: crc_2_fifo + bit_size: 2 + - name: rfo2 bit_offset: 6 bit_size: 1 - - name: no_crc_rx + - name: single bit_offset: 7 bit_size: 1 -fieldset/RX_CONF1: +fieldset/IO_CONF2: bit_size: 8 fields: - - name: z12k + - name: slow_up bit_offset: 0 bit_size: 1 - - name: h80 - bit_offset: 1 - bit_size: 1 - - name: h200 + - name: io_18 bit_offset: 2 bit_size: 1 - - name: lp + - name: miso_pd1 bit_offset: 3 - bit_size: 3 - enum: RX_CONF1_lp - - name: amd_sel + bit_size: 1 + - name: miso_pd2 + bit_offset: 4 + bit_size: 1 + - name: vspd_off bit_offset: 6 bit_size: 1 - - name: ch_sel + - name: sup_3v bit_offset: 7 bit_size: 1 -fieldset/RX_CONF2: +fieldset/IRQ_MAIN: bit_size: 8 fields: - - name: pmix_cl + - name: err bit_offset: 0 bit_size: 1 - - name: sqm_dyn + - name: tim bit_offset: 1 bit_size: 1 - - name: agc_alg + - name: col bit_offset: 2 bit_size: 1 - - name: agc_m + - name: txe bit_offset: 3 bit_size: 1 - - name: agc_en + - name: rxe bit_offset: 4 bit_size: 1 - - name: lf_en + - name: rxs bit_offset: 5 bit_size: 1 - - name: lf_op + - name: wl bit_offset: 6 bit_size: 1 - - name: rx_lp + - name: osc bit_offset: 7 bit_size: 1 -fieldset/RX_CONF3: +fieldset/IRQ_MASK_ERROR_WUP: bit_size: 8 fields: - - name: rg_nfc + - name: m_ncap bit_offset: 0 bit_size: 1 - - name: lim + - name: m_wph bit_offset: 1 bit_size: 1 - - name: rg1_pm + - name: m_wam bit_offset: 2 - bit_size: 3 - - name: rg1_am - bit_offset: 5 - bit_size: 3 -fieldset/RX_CONF4: - bit_size: 8 - fields: - - name: rg2_pm - bit_offset: 0 - bit_size: 4 - - name: rg2_am + bit_size: 1 + - name: m_wt + bit_offset: 3 + bit_size: 1 + - name: m_err1 bit_offset: 4 - bit_size: 4 -fieldset/MASK_RX_TIMER: - bit_size: 8 - fields: - - name: mrt0 - bit_offset: 0 bit_size: 1 - default: 0 - - name: mrt1 - bit_offset: 1 + - name: m_err2 + bit_offset: 5 bit_size: 1 - default: 0 - - name: mrt2 + - name: m_par + bit_offset: 6 + bit_size: 1 + - name: m_crc + bit_offset: 7 + bit_size: 1 +fieldset/IRQ_MASK_MAIN: + bit_size: 8 + fields: + - name: m_col bit_offset: 2 bit_size: 1 - default: 0 - - name: mrt3 + - name: m_txe bit_offset: 3 bit_size: 1 - default: 0 - - name: mrt4 + - name: m_rxe bit_offset: 4 bit_size: 1 - default: 0 - - name: mrt5 + - name: m_rxs bit_offset: 5 bit_size: 1 - default: 0 - - name: mrt6 + - name: m_wl bit_offset: 6 bit_size: 1 - default: 0 - - name: mrt7 + - name: m_osc bit_offset: 7 bit_size: 1 - default: 0 -fieldset/NO_RESPONSE_TIMER1: +fieldset/IRQ_MASK_TIMER_NFC: bit_size: 8 fields: - - name: nrt8 + - name: m_nfct bit_offset: 0 bit_size: 1 - default: 0 - - name: nrt9 + - name: m_cat bit_offset: 1 bit_size: 1 - default: 0 - - name: nrt10 + - name: m_cac bit_offset: 2 bit_size: 1 - default: 0 - - name: nrt11 + - name: m_eof bit_offset: 3 bit_size: 1 - default: 0 - - name: nrt12 + - name: m_eon bit_offset: 4 bit_size: 1 - default: 0 - - name: nrt13 + - name: m_gpe bit_offset: 5 bit_size: 1 - default: 0 - - name: nrt14 + - name: m_nre bit_offset: 6 bit_size: 1 - default: 0 - - name: nrt15 + - name: m_dcd bit_offset: 7 bit_size: 1 - default: 0 -fieldset/GPT_NRT_CTRL: +fieldset/IRQ_TIMER_NFC: bit_size: 8 fields: - - name: nrt_step + - name: nfct bit_offset: 0 bit_size: 1 - enum: TIMER_EMV_CONTROL_nrt_step - - name: nrt_emv + - name: cat bit_offset: 1 bit_size: 1 - - name: gptc - bit_offset: 5 - bit_size: 3 - enum: TIMER_EMV_CONTROL_gptc -fieldset/IRQ_MASK_MAIN: - bit_size: 8 - fields: - - name: m_col + - name: cac bit_offset: 2 bit_size: 1 - - name: m_txe + - name: eof bit_offset: 3 bit_size: 1 - - name: m_rxe + - name: eon bit_offset: 4 bit_size: 1 - - name: m_rxs + - name: gpe bit_offset: 5 bit_size: 1 - - name: m_wl + - name: nre bit_offset: 6 bit_size: 1 - - name: m_osc + - name: dcd bit_offset: 7 bit_size: 1 -fieldset/IRQ_MASK_TIMER_NFC: +fieldset/ISO14443A_NFC: bit_size: 8 fields: - - name: m_nfct + - name: antcl bit_offset: 0 bit_size: 1 - - name: m_cat + - name: p_len bit_offset: 1 + bit_size: 4 + - name: nfc_f0 + bit_offset: 5 bit_size: 1 - - name: m_cac + - name: no_rx_par + bit_offset: 6 + bit_size: 1 + - name: no_tx_par + bit_offset: 7 + bit_size: 1 +fieldset/ISO14443B_1: + bit_size: 8 + fields: + - name: rx_st_om + bit_offset: 0 + bit_size: 1 + - name: half + bit_offset: 1 + bit_size: 1 + - name: eof + bit_offset: 2 + bit_size: 1 + - name: sof_1 + bit_offset: 3 + bit_size: 1 + enum: ISO14443B_1_sof_1 + - name: sof_0 + bit_offset: 4 + bit_size: 1 + enum: ISO14443B_1_sof_0 + - name: egt + bit_offset: 5 + bit_size: 3 +fieldset/ISO14443B_2: + bit_size: 8 + fields: + - name: f_p + bit_offset: 0 + bit_size: 2 + enum: ISO14443B_2_f_p + - name: phc_th bit_offset: 2 bit_size: 1 - - name: m_eof + - name: eof_12 bit_offset: 3 bit_size: 1 - - name: m_eon + - name: no_eof bit_offset: 4 bit_size: 1 - - name: m_gpe + - name: no_sof bit_offset: 5 bit_size: 1 - - name: m_nre + - name: tr1 bit_offset: 6 - bit_size: 1 - - name: m_dcd - bit_offset: 7 - bit_size: 1 -fieldset/IRQ_MASK_ERROR_WUP: + bit_size: 2 + enum: ISO14443B_2_tr1 +fieldset/MASK_RX_TIMER: bit_size: 8 fields: - - name: m_ncap + - name: mrt0 bit_offset: 0 bit_size: 1 - - name: m_wph + - name: mrt1 bit_offset: 1 bit_size: 1 - - name: m_wam + - name: mrt2 bit_offset: 2 bit_size: 1 - - name: m_wt + - name: mrt3 bit_offset: 3 bit_size: 1 - - name: m_err1 + - name: mrt4 bit_offset: 4 bit_size: 1 - - name: m_err2 + - name: mrt5 bit_offset: 5 bit_size: 1 - - name: m_par + - name: mrt6 bit_offset: 6 bit_size: 1 - - name: m_crc + - name: mrt7 bit_offset: 7 bit_size: 1 -fieldset/IRQ_MAIN: +fieldset/MODE: bit_size: 8 fields: - - name: err + - name: nfc_ar bit_offset: 0 bit_size: 1 - - name: tim + - name: om + bit_offset: 3 + bit_size: 4 + enum: MODE_om + - name: targ + bit_offset: 7 + bit_size: 1 +fieldset/NFCIP1_BIT_RATE_DISP: + bit_size: 8 + fields: + - name: nfc_rate + bit_offset: 4 + bit_size: 4 +fieldset/NO_RESPONSE_TIMER1: + bit_size: 8 + fields: + - name: nrt8 + bit_offset: 0 + bit_size: 1 + - name: nrt9 bit_offset: 1 bit_size: 1 - - name: col + - name: nrt10 bit_offset: 2 bit_size: 1 - - name: txe + - name: nrt11 bit_offset: 3 bit_size: 1 - - name: rxe + - name: nrt12 bit_offset: 4 bit_size: 1 - - name: rxs + - name: nrt13 bit_offset: 5 bit_size: 1 - - name: wl + - name: nrt14 bit_offset: 6 bit_size: 1 - - name: osc + - name: nrt15 bit_offset: 7 bit_size: 1 -fieldset/IRQ_TIMER_NFC: +fieldset/NUM_TX_BYTES2: bit_size: 8 fields: - - name: nfct + - name: nbtx bit_offset: 0 - bit_size: 1 - - name: cat - bit_offset: 1 - bit_size: 1 - - name: cac + bit_size: 3 + - name: ntx + bit_offset: 3 + bit_size: 5 +fieldset/OP_CONTROL: + bit_size: 8 + fields: + - name: wu bit_offset: 2 bit_size: 1 - - name: eof + - name: tx_en bit_offset: 3 bit_size: 1 - - name: eon + - name: rx_man bit_offset: 4 bit_size: 1 - - name: gpe + - name: rx_chn bit_offset: 5 bit_size: 1 - - name: nre + - name: rx_en bit_offset: 6 bit_size: 1 - - name: dcd + - name: en bit_offset: 7 bit_size: 1 -fieldset/FIFO_STATUS2: +fieldset/PHASE_MEASURE_CONF: bit_size: 8 fields: - - name: np_lb + - name: pm_ae bit_offset: 0 bit_size: 1 - - name: fifo_lb + - name: pm_aew bit_offset: 1 - bit_size: 3 - - name: fifo_ovr - bit_offset: 5 - bit_size: 1 - - name: fifo_unf - bit_offset: 6 - bit_size: 1 -fieldset/COLLISION_STATUS: - bit_size: 8 - fields: - - name: c_pb - bit_offset: 0 + bit_size: 2 + - name: pm_aam + bit_offset: 3 bit_size: 1 - - name: c_bit - bit_offset: 1 - bit_size: 3 - - name: c_byte + - name: pm_d bit_offset: 4 bit_size: 4 -fieldset/NUM_TX_BYTES2: +fieldset/REGULATOR_AND_TIM_DISP: bit_size: 8 fields: - - name: nbtx + - name: mrt_on bit_offset: 0 - bit_size: 3 - - name: ntx - bit_offset: 3 - bit_size: 5 -fieldset/NFCIP1_BIT_RATE_DISP: - bit_size: 8 - fields: - - name: nfc_rate - bit_offset: 4 - bit_size: 4 -fieldset/ANT_TUNE_CTRL: - bit_size: 8 - fields: - - name: tre - bit_offset: 3 - bit_size: 4 - - name: trim_s - bit_offset: 7 bit_size: 1 -fieldset/ANT_TUNE_DISP: - bit_size: 8 - fields: - - name: tri_err - bit_offset: 3 + - name: nrt_on + bit_offset: 1 bit_size: 1 - - name: tri + - name: gpt_on + bit_offset: 2 + bit_size: 1 + - name: reg bit_offset: 4 bit_size: 4 -fieldset/AM_MOD_DEPTH_CTRL: +fieldset/REGULATOR_VOLT_CONTROL: bit_size: 8 fields: - - name: modd + - name: mpsv bit_offset: 1 - bit_size: 6 - - name: am_s + bit_size: 2 + - name: rege + bit_offset: 3 + bit_size: 4 + - name: reg_s bit_offset: 7 bit_size: 1 fieldset/RFO_AM_LEVEL_DEF: @@ -908,75 +913,27 @@ fieldset/RFO_AM_LEVEL_DEF: - name: d0 bit_offset: 0 bit_size: 1 - default: 0 - name: d1 bit_offset: 1 bit_size: 1 - default: 0 - name: d2 bit_offset: 2 bit_size: 1 - default: 0 - name: d3 bit_offset: 3 bit_size: 1 - default: 0 - name: d4 bit_offset: 4 bit_size: 1 - default: 0 - name: d5 bit_offset: 5 bit_size: 1 - default: 0 - name: d6 bit_offset: 6 bit_size: 1 - default: 0 - name: d7 bit_offset: 7 bit_size: 1 - default: 0 -fieldset/EXT_FIELD_DET_THR: - bit_size: 8 - fields: - - name: rfe_t - bit_offset: 0 - bit_size: 4 - default: 3 - enum: THRESHOLD_DEF_2 - - name: trg_l - bit_offset: 4 - bit_size: 3 - default: 3 - enum: THRESHOLD_DEF_1 -fieldset/REGULATOR_VOLT_CONTROL: - bit_size: 8 - fields: - - name: mpsv - bit_offset: 1 - bit_size: 2 - - name: rege - bit_offset: 3 - bit_size: 4 - - name: reg_s - bit_offset: 7 - bit_size: 1 -fieldset/REGULATOR_AND_TIM_DISP: - bit_size: 8 - fields: - - name: mrt_on - bit_offset: 0 - bit_size: 1 - - name: nrt_on - bit_offset: 1 - bit_size: 1 - - name: gpt_on - bit_offset: 2 - bit_size: 1 - - name: reg - bit_offset: 4 - bit_size: 4 fieldset/RSSI_RESULT: bit_size: 8 fields: @@ -986,137 +943,112 @@ fieldset/RSSI_RESULT: - name: rssi_am bit_offset: 4 bit_size: 4 -fieldset/GAIN_REDU_STATE: - bit_size: 8 - fields: - - name: gs_pm - bit_offset: 0 - bit_size: 4 - - name: gs_am - bit_offset: 4 - bit_size: 4 -fieldset/CAP_SENSOR_CONTROL: +fieldset/RX_CONF1: bit_size: 8 fields: - - name: cs_g + - name: z12k bit_offset: 0 - bit_size: 3 - - name: cs_mcal - bit_offset: 3 - bit_size: 5 -fieldset/CAP_SENSOR_DISP: - bit_size: 8 - fields: - - name: cs_cal_err + bit_size: 1 + - name: h80 bit_offset: 1 bit_size: 1 - - name: cs_cal_end + - name: h200 bit_offset: 2 bit_size: 1 - - name: cs_cal_val + - name: lp bit_offset: 3 - bit_size: 5 -fieldset/AUX_DISPLAY: + bit_size: 3 + enum: RX_CONF1_lp + - name: amd_sel + bit_offset: 6 + bit_size: 1 + - name: ch_sel + bit_offset: 7 + bit_size: 1 +fieldset/RX_CONF2: bit_size: 8 fields: - - name: en_ac + - name: pmix_cl bit_offset: 0 bit_size: 1 - - name: nfc_t + - name: sqm_dyn bit_offset: 1 bit_size: 1 - - name: rx_act + - name: agc_alg bit_offset: 2 bit_size: 1 - - name: rx_on + - name: agc_m bit_offset: 3 bit_size: 1 - - name: osc_ok + - name: agc_en bit_offset: 4 bit_size: 1 - - name: tx_on + - name: lf_en bit_offset: 5 bit_size: 1 - - name: efd_o + - name: lf_op bit_offset: 6 bit_size: 1 - - name: a_cha + - name: rx_lp bit_offset: 7 bit_size: 1 -fieldset/WUP_TIMER_CONTROL: +fieldset/RX_CONF3: bit_size: 8 fields: - - name: wph + - name: rg_nfc + bit_offset: 0 + bit_size: 1 + - name: lim bit_offset: 1 bit_size: 1 - - name: wam + - name: rg1_pm bit_offset: 2 - bit_size: 1 - - name: wto - bit_offset: 3 - bit_size: 1 - - name: wut - bit_offset: 4 bit_size: 3 - - name: wur - bit_offset: 7 - bit_size: 1 -fieldset/AMPLITUDE_MEASURE_CONF: + - name: rg1_am + bit_offset: 5 + bit_size: 3 +fieldset/RX_CONF4: bit_size: 8 fields: - - name: am_ae + - name: rg2_pm bit_offset: 0 - bit_size: 1 - - name: am_aew - bit_offset: 1 - bit_size: 2 - - name: am_aam - bit_offset: 3 - bit_size: 1 - - name: am_d + bit_size: 4 + - name: rg2_am bit_offset: 4 bit_size: 4 -fieldset/PHASE_MEASURE_CONF: +fieldset/STREAM_MODE: bit_size: 8 fields: - - name: pm_ae + - name: stx bit_offset: 0 - bit_size: 1 - - name: pm_aew - bit_offset: 1 - bit_size: 2 - - name: pm_aam + bit_size: 3 + enum: STREAM_MODE_stx + - name: scp bit_offset: 3 - bit_size: 1 - - name: pm_d - bit_offset: 4 - bit_size: 4 -fieldset/CAPACITANCE_MEASURE_CONF: + bit_size: 2 + enum: STREAM_MODE_scp + - name: scf + bit_offset: 5 + bit_size: 2 + enum: STREAM_MODE_scf +fieldset/WUP_TIMER_CONTROL: bit_size: 8 fields: - - name: cm_ae - bit_offset: 0 - bit_size: 1 - - name: cm_aew + - name: wph bit_offset: 1 - bit_size: 2 - - name: cm_aam + bit_size: 1 + - name: wam + bit_offset: 2 + bit_size: 1 + - name: wto bit_offset: 3 bit_size: 1 - - name: cm_d + - name: wut bit_offset: 4 - bit_size: 4 -fieldset/IC_IDENTITY: - bit_size: 8 - fields: - - name: ic_rev - bit_offset: 0 bit_size: 3 - enum: IC_IDENTITY_ic_rev - - name: ic_type - bit_offset: 3 - bit_size: 5 - enum: IC_IDENTITY_ic_type + - name: wur + bit_offset: 7 + bit_size: 1 enum/BIT_RATE_E: bit_size: 4 variants: @@ -1134,80 +1066,6 @@ enum/BIT_RATE_E: value: 5 - name: '6780' value: 6 -enum/THRESHOLD_DEF_1: - bit_size: 3 - variants: - - name: 75mv - value: 0 - - name: 105mv - value: 1 - - name: 150mv - value: 2 - - name: 205mv - value: 3 - - name: 290mv - value: 4 - - name: 400mv - value: 5 - - name: 560mv - value: 6 - - name: 800mv - value: 7 -enum/THRESHOLD_DEF_2: - bit_size: 4 - variants: - - name: 75mv - value: 0 - - name: 105mv - value: 1 - - name: 150mv - value: 2 - - name: 205mv - value: 3 - - name: 290mv - value: 4 - - name: 400mv - value: 5 - - name: 560mv - value: 6 - - name: 800mv - value: 7 - - name: 25mv - value: 8 - - name: 33mv - value: 9 - - name: 47mv - value: 10 - - name: 64mv - value: 11 - - name: 90mv - value: 12 - - name: 125mv - value: 13 - - name: 175mv - value: 14 - - name: 250mv - value: 15 -enum/WAKEUP_TIMES_DEF: - bit_size: 3 - description: Typical wake-up time, values for wur=1; multiply by 10 for wur=0 - variants: - - name: '10' - value: 0 - - name: '20' - value: 1 - - name: '30' - value: 2 - - name: '40' - value: 3 - - name: '50' - value: 4 - - name: '60' - value: 5 - - name: '70' - value: 6 - - name: '80' - value: 7 enum/IC_IDENTITY_ic_rev: bit_size: 3 variants: @@ -1237,19 +1095,19 @@ enum/IO_CONF1_out_cl: value: 2 - name: disabled value: 3 -enum/ISO14443B_1_sof_1: +enum/ISO14443B_1_sof_0: bit_size: 1 variants: - - name: 2etu + - name: 10etu value: 0 - - name: 3etu + - name: 11etu value: 1 -enum/ISO14443B_1_sof_0: +enum/ISO14443B_1_sof_1: bit_size: 1 variants: - - name: 10etu + - name: 2etu value: 0 - - name: 11etu + - name: 3etu value: 1 enum/ISO14443B_2_f_p: bit_size: 2 @@ -1348,6 +1206,60 @@ enum/STREAM_MODE_stx: value: 2 - name: '848' value: 3 +enum/THRESHOLD_DEF_1: + bit_size: 3 + variants: + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 +enum/THRESHOLD_DEF_2: + bit_size: 4 + variants: + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 + - name: 25mv + value: 8 + - name: 33mv + value: 9 + - name: 47mv + value: 10 + - name: 64mv + value: 11 + - name: 90mv + value: 12 + - name: 125mv + value: 13 + - name: 175mv + value: 14 + - name: 250mv + value: 15 enum/TIMER_EMV_CONTROL_gptc: bit_size: 3 variants: @@ -1366,3 +1278,23 @@ enum/TIMER_EMV_CONTROL_nrt_step: value: 0 - name: 4096_fc value: 1 +enum/WAKEUP_TIMES_DEF: + description: Typical wake-up time, values for wur=1; multiply by 10 for wur=0 + bit_size: 3 + variants: + - name: '10' + value: 0 + - name: '20' + value: 1 + - name: '30' + value: 2 + - name: '40' + value: 3 + - name: '50' + value: 4 + - name: '60' + value: 5 + - name: '70' + value: 6 + - name: '80' + value: 7 diff --git a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml index cc39f51..049000e 100644 --- a/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml +++ b/rnfc-st25r39/src/yaml-regmaps/regs-st25r3916.yaml @@ -1,1547 +1,1546 @@ ---- block/REGS: items: - - name: IO_CONF1 - byte_offset: 0 - bit_size: 8 - fieldset: IO_CONF1 - - name: IO_CONF2 - byte_offset: 1 - bit_size: 8 - fieldset: IO_CONF2 - - name: OP_CONTROL - byte_offset: 2 - bit_size: 8 - fieldset: OP_CONTROL - - name: MODE - byte_offset: 3 - bit_size: 8 - fieldset: MODE - - name: BIT_RATE - byte_offset: 4 - bit_size: 8 - fieldset: BIT_RATE - - name: ISO14443A_NFC - byte_offset: 5 - bit_size: 8 - fieldset: ISO14443A_NFC - - name: ISO14443B_1 - byte_offset: 6 - bit_size: 8 - fieldset: ISO14443B_1 - - name: ISO14443B_2 - byte_offset: 7 - bit_size: 8 - fieldset: ISO14443B_2 - - name: PASSIVE_TARGET - byte_offset: 8 - bit_size: 8 - fieldset: PASSIVE_TARGET - - name: STREAM_MODE - byte_offset: 9 - bit_size: 8 - fieldset: STREAM_MODE - - name: AUX - byte_offset: 10 - bit_size: 8 - fieldset: AUX - - name: RX_CONF1 - byte_offset: 11 - bit_size: 8 - fieldset: RX_CONF1 - - name: RX_CONF2 - byte_offset: 12 - bit_size: 8 - fieldset: RX_CONF2 - - name: RX_CONF3 - byte_offset: 13 - bit_size: 8 - fieldset: RX_CONF3 - - name: RX_CONF4 - byte_offset: 14 - bit_size: 8 - fieldset: RX_CONF4 - - name: MASK_RX_TIMER - byte_offset: 15 - bit_size: 8 - - name: NO_RESPONSE_TIMER1 - byte_offset: 16 - bit_size: 8 - - name: NO_RESPONSE_TIMER2 - byte_offset: 17 - bit_size: 8 - - name: TIMER_EMV_CONTROL - byte_offset: 18 - bit_size: 8 - fieldset: TIMER_EMV_CONTROL - - name: GPT1 - byte_offset: 19 - bit_size: 8 - - name: GPT2 - byte_offset: 20 - bit_size: 8 - - name: PPON2 - byte_offset: 21 - bit_size: 8 - - name: IRQ_MASK_MAIN - byte_offset: 22 - bit_size: 8 - - name: IRQ_MASK_TIMER_NFC - byte_offset: 23 - bit_size: 8 - - name: IRQ_MASK_ERROR_WUP - byte_offset: 24 - bit_size: 8 - - name: IRQ_MASK_TARGET - byte_offset: 25 - bit_size: 8 - - name: IRQ_MAIN - byte_offset: 26 - bit_size: 8 - - name: IRQ_TIMER_NFC - byte_offset: 27 - bit_size: 8 - - name: IRQ_ERROR_WUP - byte_offset: 28 - bit_size: 8 - - name: IRQ_TARGET - byte_offset: 29 - bit_size: 8 - - name: FIFO_STATUS1 - byte_offset: 30 - bit_size: 8 - - name: FIFO_STATUS2 - byte_offset: 31 - bit_size: 8 - fieldset: FIFO_STATUS2 - - name: COLLISION_STATUS - byte_offset: 32 - bit_size: 8 - fieldset: COLLISION_STATUS - - name: PASSIVE_TARGET_STATUS - byte_offset: 33 - bit_size: 8 - fieldset: PASSIVE_TARGET_STATUS - - name: NUM_TX_BYTES1 - byte_offset: 34 - bit_size: 8 - - name: NUM_TX_BYTES2 - byte_offset: 35 - bit_size: 8 - fieldset: NUM_TX_BYTES2 - - name: NFCIP1_BIT_RATE - byte_offset: 36 - bit_size: 8 - fieldset: NFCIP1_BIT_RATE - - name: AD_RESULT - byte_offset: 37 - bit_size: 8 - - name: ANT_TUNE_A - byte_offset: 38 - bit_size: 8 - - name: ANT_TUNE_B - byte_offset: 39 - bit_size: 8 - - name: TX_DRIVER - byte_offset: 40 - bit_size: 8 - fieldset: TX_DRIVER - - name: PT_MOD - byte_offset: 41 - bit_size: 8 - fieldset: PT_MOD - - name: FIELD_THRESHOLD_ACTV - byte_offset: 42 - bit_size: 8 - fieldset: FIELD_THRESHOLD_ACTV - - name: FIELD_THRESHOLD_DEACTV - byte_offset: 43 - bit_size: 8 - fieldset: FIELD_THRESHOLD_DEACTV - - name: REGULATOR_CONTROL - byte_offset: 44 - bit_size: 8 - fieldset: REGULATOR_CONTROL - - name: RSSI_RESULT - byte_offset: 45 - bit_size: 8 - fieldset: RSSI_RESULT - - name: GAIN_RED_STATE - byte_offset: 46 - bit_size: 8 - fieldset: GAIN_RED_STATE - - name: CAP_SENSOR_CONTROL - byte_offset: 47 - bit_size: 8 - fieldset: CAP_SENSOR_CONTROL - - name: CAP_SENSOR_RESULT - byte_offset: 48 - bit_size: 8 - fieldset: CAP_SENSOR_RESULT - - name: AUX_DISPLAY - byte_offset: 49 - bit_size: 8 - fieldset: AUX_DISPLAY - - name: WUP_TIMER_CONTROL - byte_offset: 50 - bit_size: 8 - fieldset: WUP_TIMER_CONTROL - - name: AMPLITUDE_MEASURE_CONF - byte_offset: 51 - bit_size: 8 - fieldset: AMPLITUDE_MEASURE_CONF - - name: AMPLITUDE_MEASURE_REF - byte_offset: 52 - bit_size: 8 - - name: AMPLITUDE_MEASURE_AA_RESULT - byte_offset: 53 - bit_size: 8 - - name: AMPLITUDE_MEASURE_RESULT - byte_offset: 54 - bit_size: 8 - - name: PHASE_MEASURE_CONF - byte_offset: 55 - bit_size: 8 - fieldset: PHASE_MEASURE_CONF - - name: PHASE_MEASURE_REF - byte_offset: 56 - bit_size: 8 - - name: PHASE_MEASURE_AA_RESULT - byte_offset: 57 - bit_size: 8 - - name: PHASE_MEASURE_RESULT - byte_offset: 58 - bit_size: 8 - - name: CAPACITANCE_MEASURE_CONF - byte_offset: 59 - bit_size: 8 - fieldset: CAPACITANCE_MEASURE_CONF - - name: CAPACITANCE_MEASURE_REF - byte_offset: 60 - bit_size: 8 - - name: CAPACITANCE_MEASURE_AA_RESULT - byte_offset: 61 - bit_size: 8 - - name: CAPACITANCE_MEASURE_RESULT - byte_offset: 62 - bit_size: 8 - - name: IC_IDENTITY - byte_offset: 63 - bit_size: 8 - fieldset: IC_IDENTITY - - name: EMD_SUP_CONF - byte_offset: 69 - bit_size: 8 - fieldset: EMD_SUP_CONF - - name: SUBC_START_TIME - byte_offset: 70 - bit_size: 8 - fieldset: SUBC_START_TIME - - name: P2P_RX_CONF - byte_offset: 75 - bit_size: 8 - fieldset: P2P_RX_CONF - - name: CORR_CONF1 - byte_offset: 76 - bit_size: 8 - fieldset: CORR_CONF1 - - name: CORR_CONF2 - byte_offset: 77 - bit_size: 8 - fieldset: CORR_CONF2 - - name: SQUELCH_TIMER - byte_offset: 79 - bit_size: 8 - - name: FIELD_ON_GT - byte_offset: 85 - bit_size: 8 - - name: AUX_MOD - byte_offset: 104 - bit_size: 8 - fieldset: AUX_MOD - - name: TX_DRIVER_TIMING - byte_offset: 105 - bit_size: 8 - fieldset: TX_DRIVER_TIMING - - name: RES_AM_MOD - byte_offset: 106 - bit_size: 8 - fieldset: RES_AM_MOD - - name: TX_DRIVER_STATUS - byte_offset: 107 - bit_size: 8 - fieldset: TX_DRIVER_STATUS - - name: REGULATOR_RESULT - byte_offset: 108 - bit_size: 8 - fieldset: REGULATOR_RESULT - - name: OVERSHOOT_CONF1 - byte_offset: 112 - bit_size: 8 - fieldset: OVERSHOOT_CONF1 - - name: OVERSHOOT_CONF2 - byte_offset: 113 - bit_size: 8 - fieldset: OVERSHOOT_CONF2 - - name: UNDERSHOOT_CONF1 - byte_offset: 114 - bit_size: 8 - fieldset: UNDERSHOOT_CONF1 - - name: UNDERSHOOT_CONF2 - byte_offset: 115 - bit_size: 8 - fieldset: UNDERSHOOT_CONF2 - - name: TEST_UNK - byte_offset: 0x84 - bit_size: 8 - fieldset: TEST_UNK -fieldset/TEST_UNK: - bit_size: 8 - fields: - - name: dis_overheat_prot - bit_offset: 4 - bit_size: 1 + - name: IO_CONF1 + byte_offset: 0 + bit_size: 8 + fieldset: IO_CONF1 + - name: IO_CONF2 + byte_offset: 1 + bit_size: 8 + fieldset: IO_CONF2 + - name: OP_CONTROL + byte_offset: 2 + bit_size: 8 + fieldset: OP_CONTROL + - name: MODE + byte_offset: 3 + bit_size: 8 + fieldset: MODE + - name: BIT_RATE + byte_offset: 4 + bit_size: 8 + fieldset: BIT_RATE + - name: ISO14443A_NFC + byte_offset: 5 + bit_size: 8 + fieldset: ISO14443A_NFC + - name: ISO14443B_1 + byte_offset: 6 + bit_size: 8 + fieldset: ISO14443B_1 + - name: ISO14443B_2 + byte_offset: 7 + bit_size: 8 + fieldset: ISO14443B_2 + - name: PASSIVE_TARGET + byte_offset: 8 + bit_size: 8 + fieldset: PASSIVE_TARGET + - name: STREAM_MODE + byte_offset: 9 + bit_size: 8 + fieldset: STREAM_MODE + - name: AUX + byte_offset: 10 + bit_size: 8 + fieldset: AUX + - name: RX_CONF1 + byte_offset: 11 + bit_size: 8 + fieldset: RX_CONF1 + - name: RX_CONF2 + byte_offset: 12 + bit_size: 8 + fieldset: RX_CONF2 + - name: RX_CONF3 + byte_offset: 13 + bit_size: 8 + fieldset: RX_CONF3 + - name: RX_CONF4 + byte_offset: 14 + bit_size: 8 + fieldset: RX_CONF4 + - name: MASK_RX_TIMER + byte_offset: 15 + bit_size: 8 + - name: NO_RESPONSE_TIMER1 + byte_offset: 16 + bit_size: 8 + - name: NO_RESPONSE_TIMER2 + byte_offset: 17 + bit_size: 8 + - name: TIMER_EMV_CONTROL + byte_offset: 18 + bit_size: 8 + fieldset: TIMER_EMV_CONTROL + - name: GPT1 + byte_offset: 19 + bit_size: 8 + - name: GPT2 + byte_offset: 20 + bit_size: 8 + - name: PPON2 + byte_offset: 21 + bit_size: 8 + - name: IRQ_MASK_MAIN + byte_offset: 22 + bit_size: 8 + - name: IRQ_MASK_TIMER_NFC + byte_offset: 23 + bit_size: 8 + - name: IRQ_MASK_ERROR_WUP + byte_offset: 24 + bit_size: 8 + - name: IRQ_MASK_TARGET + byte_offset: 25 + bit_size: 8 + - name: IRQ_MAIN + byte_offset: 26 + bit_size: 8 + - name: IRQ_TIMER_NFC + byte_offset: 27 + bit_size: 8 + - name: IRQ_ERROR_WUP + byte_offset: 28 + bit_size: 8 + - name: IRQ_TARGET + byte_offset: 29 + bit_size: 8 + - name: FIFO_STATUS1 + byte_offset: 30 + bit_size: 8 + - name: FIFO_STATUS2 + byte_offset: 31 + bit_size: 8 + fieldset: FIFO_STATUS2 + - name: COLLISION_STATUS + byte_offset: 32 + bit_size: 8 + fieldset: COLLISION_STATUS + - name: PASSIVE_TARGET_STATUS + byte_offset: 33 + bit_size: 8 + fieldset: PASSIVE_TARGET_STATUS + - name: NUM_TX_BYTES1 + byte_offset: 34 + bit_size: 8 + - name: NUM_TX_BYTES2 + byte_offset: 35 + bit_size: 8 + fieldset: NUM_TX_BYTES2 + - name: NFCIP1_BIT_RATE + byte_offset: 36 + bit_size: 8 + fieldset: NFCIP1_BIT_RATE + - name: AD_RESULT + byte_offset: 37 + bit_size: 8 + - name: ANT_TUNE_A + byte_offset: 38 + bit_size: 8 + - name: ANT_TUNE_B + byte_offset: 39 + bit_size: 8 + - name: TX_DRIVER + byte_offset: 40 + bit_size: 8 + fieldset: TX_DRIVER + - name: PT_MOD + byte_offset: 41 + bit_size: 8 + fieldset: PT_MOD + - name: FIELD_THRESHOLD_ACTV + byte_offset: 42 + bit_size: 8 + fieldset: FIELD_THRESHOLD_ACTV + - name: FIELD_THRESHOLD_DEACTV + byte_offset: 43 + bit_size: 8 + fieldset: FIELD_THRESHOLD_DEACTV + - name: REGULATOR_CONTROL + byte_offset: 44 + bit_size: 8 + fieldset: REGULATOR_CONTROL + - name: RSSI_RESULT + byte_offset: 45 + bit_size: 8 + fieldset: RSSI_RESULT + - name: GAIN_RED_STATE + byte_offset: 46 + bit_size: 8 + fieldset: GAIN_RED_STATE + - name: CAP_SENSOR_CONTROL + byte_offset: 47 + bit_size: 8 + fieldset: CAP_SENSOR_CONTROL + - name: CAP_SENSOR_RESULT + byte_offset: 48 + bit_size: 8 + fieldset: CAP_SENSOR_RESULT + - name: AUX_DISPLAY + byte_offset: 49 + bit_size: 8 + fieldset: AUX_DISPLAY + - name: WUP_TIMER_CONTROL + byte_offset: 50 + bit_size: 8 + fieldset: WUP_TIMER_CONTROL + - name: AMPLITUDE_MEASURE_CONF + byte_offset: 51 + bit_size: 8 + fieldset: AMPLITUDE_MEASURE_CONF + - name: AMPLITUDE_MEASURE_REF + byte_offset: 52 + bit_size: 8 + - name: AMPLITUDE_MEASURE_AA_RESULT + byte_offset: 53 + bit_size: 8 + - name: AMPLITUDE_MEASURE_RESULT + byte_offset: 54 + bit_size: 8 + - name: PHASE_MEASURE_CONF + byte_offset: 55 + bit_size: 8 + fieldset: PHASE_MEASURE_CONF + - name: PHASE_MEASURE_REF + byte_offset: 56 + bit_size: 8 + - name: PHASE_MEASURE_AA_RESULT + byte_offset: 57 + bit_size: 8 + - name: PHASE_MEASURE_RESULT + byte_offset: 58 + bit_size: 8 + - name: CAPACITANCE_MEASURE_CONF + byte_offset: 59 + bit_size: 8 + fieldset: CAPACITANCE_MEASURE_CONF + - name: CAPACITANCE_MEASURE_REF + byte_offset: 60 + bit_size: 8 + - name: CAPACITANCE_MEASURE_AA_RESULT + byte_offset: 61 + bit_size: 8 + - name: CAPACITANCE_MEASURE_RESULT + byte_offset: 62 + bit_size: 8 + - name: IC_IDENTITY + byte_offset: 63 + bit_size: 8 + fieldset: IC_IDENTITY + - name: EMD_SUP_CONF + byte_offset: 69 + bit_size: 8 + fieldset: EMD_SUP_CONF + - name: SUBC_START_TIME + byte_offset: 70 + bit_size: 8 + fieldset: SUBC_START_TIME + - name: P2P_RX_CONF + byte_offset: 75 + bit_size: 8 + fieldset: P2P_RX_CONF + - name: CORR_CONF1 + byte_offset: 76 + bit_size: 8 + fieldset: CORR_CONF1 + - name: CORR_CONF2 + byte_offset: 77 + bit_size: 8 + fieldset: CORR_CONF2 + - name: SQUELCH_TIMER + byte_offset: 79 + bit_size: 8 + - name: FIELD_ON_GT + byte_offset: 85 + bit_size: 8 + - name: AUX_MOD + byte_offset: 104 + bit_size: 8 + fieldset: AUX_MOD + - name: TX_DRIVER_TIMING + byte_offset: 105 + bit_size: 8 + fieldset: TX_DRIVER_TIMING + - name: RES_AM_MOD + byte_offset: 106 + bit_size: 8 + fieldset: RES_AM_MOD + - name: TX_DRIVER_STATUS + byte_offset: 107 + bit_size: 8 + fieldset: TX_DRIVER_STATUS + - name: REGULATOR_RESULT + byte_offset: 108 + bit_size: 8 + fieldset: REGULATOR_RESULT + - name: OVERSHOOT_CONF1 + byte_offset: 112 + bit_size: 8 + fieldset: OVERSHOOT_CONF1 + - name: OVERSHOOT_CONF2 + byte_offset: 113 + bit_size: 8 + fieldset: OVERSHOOT_CONF2 + - name: UNDERSHOOT_CONF1 + byte_offset: 114 + bit_size: 8 + fieldset: UNDERSHOOT_CONF1 + - name: UNDERSHOOT_CONF2 + byte_offset: 115 + bit_size: 8 + fieldset: UNDERSHOOT_CONF2 + - name: TEST_UNK + byte_offset: 132 + bit_size: 8 + fieldset: TEST_UNK fieldset/AMPLITUDE_MEASURE_CONF: bit_size: 8 fields: - - name: am_ae - bit_offset: 0 - bit_size: 1 - - name: am_aew - bit_offset: 1 - bit_size: 2 - - name: am_aam - bit_offset: 3 - bit_size: 1 - - name: am_d - bit_offset: 4 - bit_size: 4 + - name: am_ae + bit_offset: 0 + bit_size: 1 + - name: am_aew + bit_offset: 1 + bit_size: 2 + - name: am_aam + bit_offset: 3 + bit_size: 1 + - name: am_d + bit_offset: 4 + bit_size: 4 fieldset/AUX: bit_size: 8 fields: - - name: nfc_n - bit_offset: 0 - bit_size: 2 - - name: dis_corr - bit_offset: 2 - bit_size: 1 - - name: mfaz_cl90 - bit_offset: 3 - bit_size: 1 - - name: nfc_id - bit_offset: 4 - bit_size: 2 - enum: AUX_nfc_id - - name: rfu - bit_offset: 6 - bit_size: 1 - - name: no_crc_rx - bit_offset: 7 - bit_size: 1 + - name: nfc_n + bit_offset: 0 + bit_size: 2 + - name: dis_corr + bit_offset: 2 + bit_size: 1 + - name: mfaz_cl90 + bit_offset: 3 + bit_size: 1 + - name: nfc_id + bit_offset: 4 + bit_size: 2 + enum: AUX_nfc_id + - name: rfu + bit_offset: 6 + bit_size: 1 + - name: no_crc_rx + bit_offset: 7 + bit_size: 1 fieldset/AUX_DISPLAY: bit_size: 8 fields: - - name: en_ac - bit_offset: 0 - bit_size: 1 - - name: en_peer - bit_offset: 1 - bit_size: 1 - - name: rx_act - bit_offset: 2 - bit_size: 1 - - name: rx_on - bit_offset: 3 - bit_size: 1 - - name: osc_ok - bit_offset: 4 - bit_size: 1 - - name: tx_on - bit_offset: 5 - bit_size: 1 - - name: efd_o - bit_offset: 6 - bit_size: 1 - - name: a_cha - bit_offset: 7 - bit_size: 1 + - name: en_ac + bit_offset: 0 + bit_size: 1 + - name: en_peer + bit_offset: 1 + bit_size: 1 + - name: rx_act + bit_offset: 2 + bit_size: 1 + - name: rx_on + bit_offset: 3 + bit_size: 1 + - name: osc_ok + bit_offset: 4 + bit_size: 1 + - name: tx_on + bit_offset: 5 + bit_size: 1 + - name: efd_o + bit_offset: 6 + bit_size: 1 + - name: a_cha + bit_offset: 7 + bit_size: 1 fieldset/AUX_MOD: bit_size: 8 fields: - - name: rfu0 - bit_offset: 0 - bit_size: 1 - - name: rfu1 - bit_offset: 1 - bit_size: 1 - - name: rfu2 - bit_offset: 2 - bit_size: 1 - - name: res_am - bit_offset: 3 - bit_size: 1 - - name: lm_dri - bit_offset: 4 - bit_size: 1 - - name: lm_ext - bit_offset: 5 - bit_size: 1 - - name: lm_ext_pol - bit_offset: 6 - bit_size: 1 - - name: dis_reg_am - bit_offset: 7 - bit_size: 1 + - name: rfu0 + bit_offset: 0 + bit_size: 1 + - name: rfu1 + bit_offset: 1 + bit_size: 1 + - name: rfu2 + bit_offset: 2 + bit_size: 1 + - name: res_am + bit_offset: 3 + bit_size: 1 + - name: lm_dri + bit_offset: 4 + bit_size: 1 + - name: lm_ext + bit_offset: 5 + bit_size: 1 + - name: lm_ext_pol + bit_offset: 6 + bit_size: 1 + - name: dis_reg_am + bit_offset: 7 + bit_size: 1 fieldset/BIT_RATE: bit_size: 8 fields: - - name: rxrate - bit_offset: 0 - bit_size: 2 - enum: BIT_RATE_E - - name: txrate - bit_offset: 4 - bit_size: 2 - enum: BIT_RATE_E + - name: rxrate + bit_offset: 0 + bit_size: 2 + enum: BIT_RATE_E + - name: txrate + bit_offset: 4 + bit_size: 2 + enum: BIT_RATE_E fieldset/CAPACITANCE_MEASURE_CONF: bit_size: 8 fields: - - name: cm_ae - bit_offset: 0 - bit_size: 1 - - name: cm_aew - bit_offset: 1 - bit_size: 2 - - name: cm_aam - bit_offset: 3 - bit_size: 1 - - name: cm_d - bit_offset: 4 - bit_size: 4 + - name: cm_ae + bit_offset: 0 + bit_size: 1 + - name: cm_aew + bit_offset: 1 + bit_size: 2 + - name: cm_aam + bit_offset: 3 + bit_size: 1 + - name: cm_d + bit_offset: 4 + bit_size: 4 fieldset/CAP_SENSOR_CONTROL: bit_size: 8 fields: - - name: cs_g - bit_offset: 0 - bit_size: 3 - - name: cs_mcal - bit_offset: 3 - bit_size: 5 + - name: cs_g + bit_offset: 0 + bit_size: 3 + - name: cs_mcal + bit_offset: 3 + bit_size: 5 fieldset/CAP_SENSOR_RESULT: bit_size: 8 fields: - - name: cs_cal_err - bit_offset: 1 - bit_size: 1 - - name: cs_cal_end - bit_offset: 2 - bit_size: 1 - - name: cs_cal_val - bit_offset: 3 - bit_size: 5 + - name: cs_cal_err + bit_offset: 1 + bit_size: 1 + - name: cs_cal_end + bit_offset: 2 + bit_size: 1 + - name: cs_cal_val + bit_offset: 3 + bit_size: 5 fieldset/COLLISION_STATUS: bit_size: 8 fields: - - name: c_pb - bit_offset: 0 - bit_size: 1 - - name: c_bit - bit_offset: 1 - bit_size: 3 - - name: c_byte - bit_offset: 4 - bit_size: 4 + - name: c_pb + bit_offset: 0 + bit_size: 1 + - name: c_bit + bit_offset: 1 + bit_size: 3 + - name: c_byte + bit_offset: 4 + bit_size: 4 fieldset/CORR_CONF1: bit_size: 8 fields: - - name: corr_s0 - bit_offset: 0 - bit_size: 1 - - name: corr_s1 - bit_offset: 1 - bit_size: 1 - - name: corr_s2 - bit_offset: 2 - bit_size: 1 - - name: corr_s3 - bit_offset: 3 - bit_size: 1 - - name: corr_s4 - bit_offset: 4 - bit_size: 1 - - name: corr_s5 - bit_offset: 5 - bit_size: 1 - - name: corr_s6 - bit_offset: 6 - bit_size: 1 - - name: corr_s7 - bit_offset: 7 - bit_size: 1 + - name: corr_s0 + bit_offset: 0 + bit_size: 1 + - name: corr_s1 + bit_offset: 1 + bit_size: 1 + - name: corr_s2 + bit_offset: 2 + bit_size: 1 + - name: corr_s3 + bit_offset: 3 + bit_size: 1 + - name: corr_s4 + bit_offset: 4 + bit_size: 1 + - name: corr_s5 + bit_offset: 5 + bit_size: 1 + - name: corr_s6 + bit_offset: 6 + bit_size: 1 + - name: corr_s7 + bit_offset: 7 + bit_size: 1 fieldset/CORR_CONF2: bit_size: 8 fields: - - name: corr_s8 - bit_offset: 0 - bit_size: 1 - - name: corr_s9 - bit_offset: 1 - bit_size: 1 - - name: rfu0 - bit_offset: 2 - bit_size: 1 - - name: rfu1 - bit_offset: 3 - bit_size: 1 - - name: rfu2 - bit_offset: 4 - bit_size: 1 - - name: rfu3 - bit_offset: 5 - bit_size: 1 - - name: rfu4 - bit_offset: 6 - bit_size: 1 - - name: rfu5 - bit_offset: 7 - bit_size: 1 + - name: corr_s8 + bit_offset: 0 + bit_size: 1 + - name: corr_s9 + bit_offset: 1 + bit_size: 1 + - name: rfu0 + bit_offset: 2 + bit_size: 1 + - name: rfu1 + bit_offset: 3 + bit_size: 1 + - name: rfu2 + bit_offset: 4 + bit_size: 1 + - name: rfu3 + bit_offset: 5 + bit_size: 1 + - name: rfu4 + bit_offset: 6 + bit_size: 1 + - name: rfu5 + bit_offset: 7 + bit_size: 1 fieldset/EMD_SUP_CONF: bit_size: 8 fields: - - name: emd_thld - bit_offset: 0 - bit_size: 4 - - name: rfu0 - bit_offset: 4 - bit_size: 1 - - name: rfu1 - bit_offset: 5 - bit_size: 1 - - name: rx_start_emv - bit_offset: 6 - bit_size: 1 - - name: emd_emv - bit_offset: 7 - bit_size: 1 + - name: emd_thld + bit_offset: 0 + bit_size: 4 + - name: rfu0 + bit_offset: 4 + bit_size: 1 + - name: rfu1 + bit_offset: 5 + bit_size: 1 + - name: rx_start_emv + bit_offset: 6 + bit_size: 1 + - name: emd_emv + bit_offset: 7 + bit_size: 1 fieldset/FIELD_THRESHOLD_ACTV: bit_size: 8 fields: - - name: rfe - bit_offset: 0 - bit_size: 4 - enum: FIELD_THRESHOLD_ACTV_rfe - - name: trg - bit_offset: 4 - bit_size: 3 - enum: FIELD_THRESHOLD_ACTV_trg + - name: rfe + bit_offset: 0 + bit_size: 4 + enum: FIELD_THRESHOLD_ACTV_rfe + - name: trg + bit_offset: 4 + bit_size: 3 + enum: FIELD_THRESHOLD_ACTV_trg fieldset/FIELD_THRESHOLD_DEACTV: bit_size: 8 fields: - - name: rfe - bit_offset: 0 - bit_size: 4 - enum: FIELD_THRESHOLD_DEACTV_rfe - - name: trg - bit_offset: 4 - bit_size: 3 - enum: FIELD_THRESHOLD_DEACTV_trg + - name: rfe + bit_offset: 0 + bit_size: 4 + enum: FIELD_THRESHOLD_DEACTV_rfe + - name: trg + bit_offset: 4 + bit_size: 3 + enum: FIELD_THRESHOLD_DEACTV_trg fieldset/FIFO_STATUS2: bit_size: 8 fields: - - name: np_lb - bit_offset: 0 - bit_size: 1 - - name: fifo_lb - bit_offset: 1 - bit_size: 3 - - name: fifo_ovr - bit_offset: 4 - bit_size: 1 - - name: fifo_unf - bit_offset: 5 - bit_size: 1 - - name: fifo_b - bit_offset: 6 - bit_size: 2 + - name: np_lb + bit_offset: 0 + bit_size: 1 + - name: fifo_lb + bit_offset: 1 + bit_size: 3 + - name: fifo_ovr + bit_offset: 4 + bit_size: 1 + - name: fifo_unf + bit_offset: 5 + bit_size: 1 + - name: fifo_b + bit_offset: 6 + bit_size: 2 fieldset/GAIN_RED_STATE: bit_size: 8 fields: - - name: gs_pm - bit_offset: 0 - bit_size: 4 - - name: gs_am - bit_offset: 4 - bit_size: 4 + - name: gs_pm + bit_offset: 0 + bit_size: 4 + - name: gs_am + bit_offset: 4 + bit_size: 4 fieldset/IC_IDENTITY: bit_size: 8 fields: - - name: ic_rev - bit_offset: 0 - bit_size: 3 - enum: IC_IDENTITY_ic_rev - - name: ic_type - bit_offset: 3 - bit_size: 5 - enum: IC_IDENTITY_ic_type + - name: ic_rev + bit_offset: 0 + bit_size: 3 + enum: IC_IDENTITY_ic_rev + - name: ic_type + bit_offset: 3 + bit_size: 5 + enum: IC_IDENTITY_ic_type fieldset/IO_CONF1: bit_size: 8 fields: - - name: lf_clk_off - bit_offset: 0 - bit_size: 1 - - name: out_cl - bit_offset: 1 - bit_size: 2 - enum: IO_CONF1_out_cl - - name: rfu - bit_offset: 3 - bit_size: 1 - - name: i2c_thd - bit_offset: 4 - bit_size: 2 - - name: rfo2 - bit_offset: 6 - bit_size: 1 - - name: single - bit_offset: 7 - bit_size: 1 + - name: lf_clk_off + bit_offset: 0 + bit_size: 1 + - name: out_cl + bit_offset: 1 + bit_size: 2 + enum: IO_CONF1_out_cl + - name: rfu + bit_offset: 3 + bit_size: 1 + - name: i2c_thd + bit_offset: 4 + bit_size: 2 + - name: rfo2 + bit_offset: 6 + bit_size: 1 + - name: single + bit_offset: 7 + bit_size: 1 fieldset/IO_CONF2: bit_size: 8 fields: - - name: slow_up - bit_offset: 0 - bit_size: 1 - - name: am_ref_rf - bit_offset: 1 - bit_size: 1 - - name: io_drv_lvl - bit_offset: 2 - bit_size: 1 - - name: miso_pd1 - bit_offset: 3 - bit_size: 1 - - name: miso_pd2 - bit_offset: 4 - bit_size: 1 - - name: aat_en - bit_offset: 5 - bit_size: 1 - - name: vspd_off - bit_offset: 6 - bit_size: 1 - - name: sup_3v - bit_offset: 7 - bit_size: 1 + - name: slow_up + bit_offset: 0 + bit_size: 1 + - name: am_ref_rf + bit_offset: 1 + bit_size: 1 + - name: io_drv_lvl + bit_offset: 2 + bit_size: 1 + - name: miso_pd1 + bit_offset: 3 + bit_size: 1 + - name: miso_pd2 + bit_offset: 4 + bit_size: 1 + - name: aat_en + bit_offset: 5 + bit_size: 1 + - name: vspd_off + bit_offset: 6 + bit_size: 1 + - name: sup_3v + bit_offset: 7 + bit_size: 1 fieldset/ISO14443A_NFC: bit_size: 8 fields: - - name: antcl - bit_offset: 0 - bit_size: 1 - - name: p_len - bit_offset: 1 - bit_size: 4 - - name: nfc_f0 - bit_offset: 5 - bit_size: 1 - - name: no_rx_par - bit_offset: 6 - bit_size: 1 - - name: no_tx_par - bit_offset: 7 - bit_size: 1 + - name: antcl + bit_offset: 0 + bit_size: 1 + - name: p_len + bit_offset: 1 + bit_size: 4 + - name: nfc_f0 + bit_offset: 5 + bit_size: 1 + - name: no_rx_par + bit_offset: 6 + bit_size: 1 + - name: no_tx_par + bit_offset: 7 + bit_size: 1 fieldset/ISO14443B_1: bit_size: 8 fields: - - name: rx_st_om - bit_offset: 0 - bit_size: 1 - - name: half - bit_offset: 1 - bit_size: 1 - - name: eof - bit_offset: 2 - bit_size: 1 - - name: eof_11etu - bit_offset: 2 - bit_size: 1 - - name: sof_1 - bit_offset: 3 - bit_size: 1 - enum: ISO14443B_1_sof_1 - - name: sof_0_11etu - bit_offset: 4 - bit_size: 1 - - name: sof_0_mak - bit_offset: 4 - bit_size: 1 - - name: egt - bit_offset: 5 - bit_size: 3 + - name: rx_st_om + bit_offset: 0 + bit_size: 1 + - name: half + bit_offset: 1 + bit_size: 1 + - name: eof + bit_offset: 2 + bit_size: 1 + - name: eof_11etu + bit_offset: 2 + bit_size: 1 + - name: sof_1 + bit_offset: 3 + bit_size: 1 + enum: ISO14443B_1_sof_1 + - name: sof_0_11etu + bit_offset: 4 + bit_size: 1 + - name: sof_0_mak + bit_offset: 4 + bit_size: 1 + - name: egt + bit_offset: 5 + bit_size: 3 fieldset/ISO14443B_2: bit_size: 8 fields: - - name: f_p - bit_offset: 0 - bit_size: 2 - enum: ISO14443B_2_f_p - - name: no_eof - bit_offset: 4 - bit_size: 1 - - name: no_sof - bit_offset: 5 - bit_size: 1 - - name: tr1 - bit_offset: 6 - bit_size: 2 - enum: ISO14443B_2_tr1 + - name: f_p + bit_offset: 0 + bit_size: 2 + enum: ISO14443B_2_f_p + - name: no_eof + bit_offset: 4 + bit_size: 1 + - name: no_sof + bit_offset: 5 + bit_size: 1 + - name: tr1 + bit_offset: 6 + bit_size: 2 + enum: ISO14443B_2_tr1 fieldset/MODE: bit_size: 8 fields: - - name: nfc_ar - bit_offset: 0 - bit_size: 2 - enum: MODE_nfc_ar - - name: tr_am - bit_offset: 2 - bit_size: 1 - - name: om - bit_offset: 3 - bit_size: 4 - enum: MODE_om - - name: targ - bit_offset: 7 - bit_size: 1 - - name: targ_targ - bit_offset: 7 - bit_size: 1 + - name: nfc_ar + bit_offset: 0 + bit_size: 2 + enum: MODE_nfc_ar + - name: tr_am + bit_offset: 2 + bit_size: 1 + - name: om + bit_offset: 3 + bit_size: 4 + enum: MODE_om + - name: targ + bit_offset: 7 + bit_size: 1 + - name: targ_targ + bit_offset: 7 + bit_size: 1 fieldset/NFCIP1_BIT_RATE: bit_size: 8 fields: - - name: mrt_on - bit_offset: 0 - bit_size: 1 - - name: nrt_on - bit_offset: 1 - bit_size: 1 - - name: gpt_on - bit_offset: 2 - bit_size: 1 - - name: ppt2_on - bit_offset: 3 - bit_size: 1 - - name: nfc_rate - bit_offset: 4 - bit_size: 2 - - name: nfc_rfu0 - bit_offset: 6 - bit_size: 1 - - name: nfc_rfu1 - bit_offset: 7 - bit_size: 1 + - name: mrt_on + bit_offset: 0 + bit_size: 1 + - name: nrt_on + bit_offset: 1 + bit_size: 1 + - name: gpt_on + bit_offset: 2 + bit_size: 1 + - name: ppt2_on + bit_offset: 3 + bit_size: 1 + - name: nfc_rate + bit_offset: 4 + bit_size: 2 + - name: nfc_rfu0 + bit_offset: 6 + bit_size: 1 + - name: nfc_rfu1 + bit_offset: 7 + bit_size: 1 fieldset/NUM_TX_BYTES2: bit_size: 8 fields: - - name: nbtx - bit_offset: 0 - bit_size: 3 - - name: ntx - bit_offset: 3 - bit_size: 5 + - name: nbtx + bit_offset: 0 + bit_size: 3 + - name: ntx + bit_offset: 3 + bit_size: 5 fieldset/OP_CONTROL: bit_size: 8 fields: - - name: en_fd - bit_offset: 0 - bit_size: 2 - enum: OP_CONTROL_en_fd - - name: wu - bit_offset: 2 - bit_size: 1 - - name: tx_en - bit_offset: 3 - bit_size: 1 - - name: rx_man - bit_offset: 4 - bit_size: 1 - - name: rx_chn - bit_offset: 5 - bit_size: 1 - - name: rx_en - bit_offset: 6 - bit_size: 1 - - name: en - bit_offset: 7 - bit_size: 1 + - name: en_fd + bit_offset: 0 + bit_size: 2 + enum: OP_CONTROL_en_fd + - name: wu + bit_offset: 2 + bit_size: 1 + - name: tx_en + bit_offset: 3 + bit_size: 1 + - name: rx_man + bit_offset: 4 + bit_size: 1 + - name: rx_chn + bit_offset: 5 + bit_size: 1 + - name: rx_en + bit_offset: 6 + bit_size: 1 + - name: en + bit_offset: 7 + bit_size: 1 fieldset/OVERSHOOT_CONF1: bit_size: 8 fields: - - name: ov_pattern - bit_offset: 0 - bit_size: 6 - - name: ov_tx_mode0 - bit_offset: 6 - bit_size: 1 - - name: ov_tx_mode1 - bit_offset: 7 - bit_size: 1 + - name: ov_pattern + bit_offset: 0 + bit_size: 6 + - name: ov_tx_mode0 + bit_offset: 6 + bit_size: 1 + - name: ov_tx_mode1 + bit_offset: 7 + bit_size: 1 fieldset/OVERSHOOT_CONF2: bit_size: 8 fields: - - name: ov_pattern - bit_offset: 0 - bit_size: 8 + - name: ov_pattern + bit_offset: 0 + bit_size: 8 fieldset/P2P_RX_CONF: bit_size: 8 fields: - - name: ask_thd - bit_offset: 0 - bit_size: 1 - - name: ask_rc0 - bit_offset: 1 - bit_size: 1 - - name: ask_rc1 - bit_offset: 2 - bit_size: 1 - - name: ook_thd0 - bit_offset: 3 - bit_size: 1 - - name: ook_thd1 - bit_offset: 4 - bit_size: 1 - - name: ook_rc0 - bit_offset: 5 - bit_size: 1 - - name: ook_rc1 - bit_offset: 6 - bit_size: 1 - - name: ook_fd - bit_offset: 7 - bit_size: 1 + - name: ask_thd + bit_offset: 0 + bit_size: 1 + - name: ask_rc0 + bit_offset: 1 + bit_size: 1 + - name: ask_rc1 + bit_offset: 2 + bit_size: 1 + - name: ook_thd0 + bit_offset: 3 + bit_size: 1 + - name: ook_thd1 + bit_offset: 4 + bit_size: 1 + - name: ook_rc0 + bit_offset: 5 + bit_size: 1 + - name: ook_rc1 + bit_offset: 6 + bit_size: 1 + - name: ook_fd + bit_offset: 7 + bit_size: 1 fieldset/PASSIVE_TARGET: bit_size: 8 fields: - - name: d_106_ac_a - bit_offset: 0 - bit_size: 1 - - name: rfu - bit_offset: 1 - bit_size: 1 - - name: d_212_424_1r - bit_offset: 2 - bit_size: 1 - - name: d_ac_ap2p - bit_offset: 3 - bit_size: 1 - - name: fdel - bit_offset: 4 - bit_size: 4 + - name: d_106_ac_a + bit_offset: 0 + bit_size: 1 + - name: rfu + bit_offset: 1 + bit_size: 1 + - name: d_212_424_1r + bit_offset: 2 + bit_size: 1 + - name: d_ac_ap2p + bit_offset: 3 + bit_size: 1 + - name: fdel + bit_offset: 4 + bit_size: 4 fieldset/PASSIVE_TARGET_STATUS: bit_size: 8 fields: - - name: pta_state - bit_offset: 0 - bit_size: 4 - enum: PASSIVE_TARGET_STATUS_pta_state - - name: rfu3 - bit_offset: 4 - bit_size: 1 - - name: rfu2 - bit_offset: 5 - bit_size: 1 - - name: rfu1 - bit_offset: 6 - bit_size: 1 - - name: rfu - bit_offset: 7 - bit_size: 1 + - name: pta_state + bit_offset: 0 + bit_size: 4 + enum: PASSIVE_TARGET_STATUS_pta_state + - name: rfu3 + bit_offset: 4 + bit_size: 1 + - name: rfu2 + bit_offset: 5 + bit_size: 1 + - name: rfu1 + bit_offset: 6 + bit_size: 1 + - name: rfu + bit_offset: 7 + bit_size: 1 fieldset/PHASE_MEASURE_CONF: bit_size: 8 fields: - - name: pm_ae - bit_offset: 0 - bit_size: 1 - - name: pm_aew - bit_offset: 1 - bit_size: 2 - - name: pm_aam - bit_offset: 3 - bit_size: 1 - - name: pm_d - bit_offset: 4 - bit_size: 4 + - name: pm_ae + bit_offset: 0 + bit_size: 1 + - name: pm_aew + bit_offset: 1 + bit_size: 2 + - name: pm_aam + bit_offset: 3 + bit_size: 1 + - name: pm_d + bit_offset: 4 + bit_size: 4 fieldset/PT_MOD: bit_size: 8 fields: - - name: pt_res - bit_offset: 0 - bit_size: 4 - - name: ptm_res - bit_offset: 4 - bit_size: 4 + - name: pt_res + bit_offset: 0 + bit_size: 4 + - name: ptm_res + bit_offset: 4 + bit_size: 4 fieldset/REGULATOR_CONTROL: bit_size: 8 fields: - - name: mpsv - bit_offset: 0 - bit_size: 3 - enum: REGULATOR_CONTROL_mpsv - - name: rege - bit_offset: 3 - bit_size: 4 - - name: reg_s - bit_offset: 7 - bit_size: 1 + - name: mpsv + bit_offset: 0 + bit_size: 3 + enum: REGULATOR_CONTROL_mpsv + - name: rege + bit_offset: 3 + bit_size: 4 + - name: reg_s + bit_offset: 7 + bit_size: 1 fieldset/REGULATOR_RESULT: bit_size: 8 fields: - - name: i_lim - bit_offset: 0 - bit_size: 1 - - name: reg - bit_offset: 4 - bit_size: 4 + - name: i_lim + bit_offset: 0 + bit_size: 1 + - name: reg + bit_offset: 4 + bit_size: 4 fieldset/RES_AM_MOD: bit_size: 8 fields: - - name: md_res - bit_offset: 0 - bit_size: 7 - - name: fa3_f - bit_offset: 7 - bit_size: 1 + - name: md_res + bit_offset: 0 + bit_size: 7 + - name: fa3_f + bit_offset: 7 + bit_size: 1 fieldset/RSSI_RESULT: bit_size: 8 fields: - - name: rssi_pm - bit_offset: 0 - bit_size: 4 - - name: rssi_am - bit_offset: 4 - bit_size: 4 + - name: rssi_pm + bit_offset: 0 + bit_size: 4 + - name: rssi_am + bit_offset: 4 + bit_size: 4 fieldset/RX_CONF1: bit_size: 8 fields: - - name: hz - bit_offset: 0 - bit_size: 4 - enum: RX_CONF1_hz - - name: z12k - bit_offset: 0 - bit_size: 1 - - name: h80 - bit_offset: 1 - bit_size: 1 - - name: h200 - bit_offset: 2 - bit_size: 1 - - name: z600k - bit_offset: 3 - bit_size: 1 - - name: lp - bit_offset: 4 - bit_size: 3 - enum: RX_CONF1_lp - - name: ch_sel - bit_offset: 7 - bit_size: 1 + - name: hz + bit_offset: 0 + bit_size: 4 + enum: RX_CONF1_hz + - name: z12k + bit_offset: 0 + bit_size: 1 + - name: h80 + bit_offset: 1 + bit_size: 1 + - name: h200 + bit_offset: 2 + bit_size: 1 + - name: z600k + bit_offset: 3 + bit_size: 1 + - name: lp + bit_offset: 4 + bit_size: 3 + enum: RX_CONF1_lp + - name: ch_sel + bit_offset: 7 + bit_size: 1 fieldset/RX_CONF2: bit_size: 8 fields: - - name: agc6_3 - bit_offset: 0 - bit_size: 1 - - name: agc_alg - bit_offset: 1 - bit_size: 1 - - name: agc_m - bit_offset: 2 - bit_size: 1 - - name: agc_en - bit_offset: 3 - bit_size: 1 - - name: pulz_61 - bit_offset: 4 - bit_size: 1 - - name: sqm_dyn - bit_offset: 5 - bit_size: 1 - - name: amd_sel - bit_offset: 6 - bit_size: 1 - - name: amd_sel_mixer - bit_offset: 6 - bit_size: 1 - - name: demod_mode - bit_offset: 7 - bit_size: 1 + - name: agc6_3 + bit_offset: 0 + bit_size: 1 + - name: agc_alg + bit_offset: 1 + bit_size: 1 + - name: agc_m + bit_offset: 2 + bit_size: 1 + - name: agc_en + bit_offset: 3 + bit_size: 1 + - name: pulz_61 + bit_offset: 4 + bit_size: 1 + - name: sqm_dyn + bit_offset: 5 + bit_size: 1 + - name: amd_sel + bit_offset: 6 + bit_size: 1 + - name: amd_sel_mixer + bit_offset: 6 + bit_size: 1 + - name: demod_mode + bit_offset: 7 + bit_size: 1 fieldset/RX_CONF3: bit_size: 8 fields: - - name: lf_op - bit_offset: 0 - bit_size: 1 - - name: lf_en - bit_offset: 1 - bit_size: 1 - - name: rg1_pm - bit_offset: 2 - bit_size: 3 - - name: rg1_am - bit_offset: 5 - bit_size: 3 + - name: lf_op + bit_offset: 0 + bit_size: 1 + - name: lf_en + bit_offset: 1 + bit_size: 1 + - name: rg1_pm + bit_offset: 2 + bit_size: 3 + - name: rg1_am + bit_offset: 5 + bit_size: 3 fieldset/RX_CONF4: bit_size: 8 fields: - - name: rg2_pm - bit_offset: 0 - bit_size: 4 - - name: rg2_am - bit_offset: 4 - bit_size: 4 + - name: rg2_pm + bit_offset: 0 + bit_size: 4 + - name: rg2_am + bit_offset: 4 + bit_size: 4 fieldset/STREAM_MODE: bit_size: 8 fields: - - name: stx - bit_offset: 0 - bit_size: 3 - enum: STREAM_MODE_stx - - name: scp - bit_offset: 3 - bit_size: 2 - enum: STREAM_MODE_scp - - name: scf - bit_offset: 5 - bit_size: 2 - enum: STREAM_MODE_scf - - name: rfu - bit_offset: 7 - bit_size: 1 + - name: stx + bit_offset: 0 + bit_size: 3 + enum: STREAM_MODE_stx + - name: scp + bit_offset: 3 + bit_size: 2 + enum: STREAM_MODE_scp + - name: scf + bit_offset: 5 + bit_size: 2 + enum: STREAM_MODE_scf + - name: rfu + bit_offset: 7 + bit_size: 1 fieldset/SUBC_START_TIME: bit_size: 8 fields: - - name: sst - bit_offset: 0 - bit_size: 5 - - name: rfu0 - bit_offset: 5 - bit_size: 1 - - name: rfu1 - bit_offset: 6 - bit_size: 1 - - name: rfu2 - bit_offset: 7 - bit_size: 1 + - name: sst + bit_offset: 0 + bit_size: 5 + - name: rfu0 + bit_offset: 5 + bit_size: 1 + - name: rfu1 + bit_offset: 6 + bit_size: 1 + - name: rfu2 + bit_offset: 7 + bit_size: 1 +fieldset/TEST_UNK: + bit_size: 8 + fields: + - name: dis_overheat_prot + bit_offset: 4 + bit_size: 1 fieldset/TIMER_EMV_CONTROL: bit_size: 8 fields: - - name: nrt_step - bit_offset: 0 - bit_size: 1 - enum: TIMER_EMV_CONTROL_nrt_step - - name: nrt_emv - bit_offset: 1 - bit_size: 1 - - name: nrt_nfc - bit_offset: 2 - bit_size: 1 - - name: mrt_step - bit_offset: 3 - bit_size: 1 - enum: TIMER_EMV_CONTROL_mrt_step - - name: rfu - bit_offset: 4 - bit_size: 1 - - name: gptc - bit_offset: 5 - bit_size: 3 - enum: TIMER_EMV_CONTROL_gptc + - name: nrt_step + bit_offset: 0 + bit_size: 1 + enum: TIMER_EMV_CONTROL_nrt_step + - name: nrt_emv + bit_offset: 1 + bit_size: 1 + - name: nrt_nfc + bit_offset: 2 + bit_size: 1 + - name: mrt_step + bit_offset: 3 + bit_size: 1 + enum: TIMER_EMV_CONTROL_mrt_step + - name: rfu + bit_offset: 4 + bit_size: 1 + - name: gptc + bit_offset: 5 + bit_size: 3 + enum: TIMER_EMV_CONTROL_gptc fieldset/TX_DRIVER: bit_size: 8 fields: - - name: d_res - bit_offset: 0 - bit_size: 4 - - name: am_mod - bit_offset: 4 - bit_size: 4 - enum: TX_DRIVER_am_mod + - name: d_res + bit_offset: 0 + bit_size: 4 + - name: am_mod + bit_offset: 4 + bit_size: 4 + enum: TX_DRIVER_am_mod fieldset/TX_DRIVER_STATUS: bit_size: 8 fields: - - name: d_tim - bit_offset: 0 - bit_size: 3 - enum: TX_DRIVER_STATUS_d_tim - - name: rfu - bit_offset: 3 - bit_size: 1 - - name: d_rat - bit_offset: 4 - bit_size: 4 + - name: d_tim + bit_offset: 0 + bit_size: 3 + enum: TX_DRIVER_STATUS_d_tim + - name: rfu + bit_offset: 3 + bit_size: 1 + - name: d_rat + bit_offset: 4 + bit_size: 4 fieldset/TX_DRIVER_TIMING: bit_size: 8 fields: - - name: d_tim_m - bit_offset: 0 - bit_size: 3 - - name: rfu - bit_offset: 3 - bit_size: 1 - - name: d_rat - bit_offset: 4 - bit_size: 4 + - name: d_tim_m + bit_offset: 0 + bit_size: 3 + - name: rfu + bit_offset: 3 + bit_size: 1 + - name: d_rat + bit_offset: 4 + bit_size: 4 fieldset/UNDERSHOOT_CONF1: bit_size: 8 fields: - - name: un_pattern - bit_offset: 0 - bit_size: 6 - - name: un_tx_mode0 - bit_offset: 6 - bit_size: 1 - - name: un_tx_mode1 - bit_offset: 7 - bit_size: 1 + - name: un_pattern + bit_offset: 0 + bit_size: 6 + - name: un_tx_mode0 + bit_offset: 6 + bit_size: 1 + - name: un_tx_mode1 + bit_offset: 7 + bit_size: 1 fieldset/UNDERSHOOT_CONF2: bit_size: 8 fields: - - name: un_pattern - bit_offset: 0 - bit_size: 8 + - name: un_pattern + bit_offset: 0 + bit_size: 8 fieldset/WUP_TIMER_CONTROL: bit_size: 8 fields: - - name: wcap - bit_offset: 0 - bit_size: 1 - - name: wph - bit_offset: 1 - bit_size: 1 - - name: wam - bit_offset: 2 - bit_size: 1 - - name: wto - bit_offset: 3 - bit_size: 1 - - name: wut - bit_offset: 4 - bit_size: 3 - - name: wur - bit_offset: 7 - bit_size: 1 + - name: wcap + bit_offset: 0 + bit_size: 1 + - name: wph + bit_offset: 1 + bit_size: 1 + - name: wam + bit_offset: 2 + bit_size: 1 + - name: wto + bit_offset: 3 + bit_size: 1 + - name: wut + bit_offset: 4 + bit_size: 3 + - name: wur + bit_offset: 7 + bit_size: 1 enum/AUX_nfc_id: bit_size: 2 variants: - - name: 4bytes - value: 0 - - name: 7bytes - value: 1 + - name: 4bytes + value: 0 + - name: 7bytes + value: 1 enum/BIT_RATE_E: bit_size: 2 variants: - - name: "106" - value: 0 - - name: "212" - value: 1 - - name: "424" - value: 2 - - name: "848" - value: 3 + - name: '106' + value: 0 + - name: '212' + value: 1 + - name: '424' + value: 2 + - name: '848' + value: 3 enum/FIELD_THRESHOLD_ACTV_rfe: bit_size: 4 variants: - - name: 75mv - value: 0 - - name: 105mv - value: 1 - - name: 150mv - value: 2 - - name: 205mv - value: 3 - - name: 290mv - value: 4 - - name: 400mv - value: 5 - - name: 560mv - value: 6 - - name: 800mv - value: 7 - - name: 25mv - value: 8 - - name: 33mv - value: 9 - - name: 47mv - value: 10 - - name: 64mv - value: 11 - - name: 90mv - value: 12 - - name: 125mv - value: 13 - - name: 175mv - value: 14 - - name: 250mv - value: 15 + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 + - name: 25mv + value: 8 + - name: 33mv + value: 9 + - name: 47mv + value: 10 + - name: 64mv + value: 11 + - name: 90mv + value: 12 + - name: 125mv + value: 13 + - name: 175mv + value: 14 + - name: 250mv + value: 15 enum/FIELD_THRESHOLD_ACTV_trg: bit_size: 3 variants: - - name: 75mv - value: 0 - - name: 105mv - value: 1 - - name: 150mv - value: 2 - - name: 205mv - value: 3 - - name: 290mv - value: 4 - - name: 400mv - value: 5 - - name: 560mv - value: 6 - - name: 800mv - value: 7 + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 enum/FIELD_THRESHOLD_DEACTV_rfe: bit_size: 4 variants: - - name: 75mv - value: 0 - - name: 105mv - value: 1 - - name: 150mv - value: 2 - - name: 205mv - value: 3 - - name: 290mv - value: 4 - - name: 400mv - value: 5 - - name: 560mv - value: 6 - - name: 800mv - value: 7 - - name: 25mv - value: 8 - - name: 33mv - value: 9 - - name: 47mv - value: 10 - - name: 64mv - value: 11 - - name: 90mv - value: 12 - - name: 125mv - value: 13 - - name: 175mv - value: 14 - - name: 250mv - value: 15 + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 + - name: 25mv + value: 8 + - name: 33mv + value: 9 + - name: 47mv + value: 10 + - name: 64mv + value: 11 + - name: 90mv + value: 12 + - name: 125mv + value: 13 + - name: 175mv + value: 14 + - name: 250mv + value: 15 enum/FIELD_THRESHOLD_DEACTV_trg: bit_size: 3 variants: - - name: 75mv - value: 0 - - name: 105mv - value: 1 - - name: 150mv - value: 2 - - name: 205mv - value: 3 - - name: 290mv - value: 4 - - name: 400mv - value: 5 - - name: 560mv - value: 6 - - name: 800mv - value: 7 + - name: 75mv + value: 0 + - name: 105mv + value: 1 + - name: 150mv + value: 2 + - name: 205mv + value: 3 + - name: 290mv + value: 4 + - name: 400mv + value: 5 + - name: 560mv + value: 6 + - name: 800mv + value: 7 enum/IC_IDENTITY_ic_rev: bit_size: 3 variants: - - name: v0 - value: 0 + - name: v0 + value: 0 enum/IC_IDENTITY_ic_type: bit_size: 5 variants: - - name: st25r3916 - value: 5 + - name: st25r3916 + value: 5 enum/IO_CONF1_out_cl: bit_size: 2 variants: - - name: _3_39_mhz - value: 0 - - name: _6_78_mhz - value: 1 - - name: _13_86_mhz - value: 2 - - name: disabled - value: 3 + - name: _3_39_mhz + value: 0 + - name: _6_78_mhz + value: 1 + - name: _13_86_mhz + value: 2 + - name: disabled + value: 3 enum/ISO14443B_1_sof_1: bit_size: 1 variants: - - name: 2etu - value: 0 - - name: 3etu - value: 1 + - name: 2etu + value: 0 + - name: 3etu + value: 1 enum/ISO14443B_2_f_p: bit_size: 2 variants: - - name: "48" - value: 0 - - name: "64" - value: 1 - - name: "80" - value: 2 - - name: "96" - value: 3 + - name: '48' + value: 0 + - name: '64' + value: 1 + - name: '80' + value: 2 + - name: '96' + value: 3 enum/ISO14443B_2_tr1: bit_size: 2 variants: - - name: 80fs80fs - value: 0 - - name: 64fs32fs - value: 1 + - name: 80fs80fs + value: 0 + - name: 64fs32fs + value: 1 enum/MODE_nfc_ar: bit_size: 2 variants: - - name: "off" - value: 0 - - name: auto_rx - value: 1 - - name: eof - value: 2 - - name: rfu - value: 3 + - name: off + value: 0 + - name: auto_rx + value: 1 + - name: eof + value: 2 + - name: rfu + value: 3 enum/MODE_om: bit_size: 4 variants: - - name: ini_nfc - value: 0 - - name: ini_iso14443a - value: 1 - - name: targ_nfca - value: 1 - - name: ini_iso14443b - value: 2 - - name: targ_nfcb - value: 2 - - name: ini_felica - value: 3 - - name: ini_topaz - value: 4 - - name: targ_nfcf - value: 4 - - name: targ_nfcip - value: 7 - - name: ini_subcarrier_stream - value: 14 - - name: ini_bpsk_stream - value: 15 + - name: ini_nfc + value: 0 + - name: ini_iso14443a + value: 1 + - name: targ_nfca + value: 1 + - name: ini_iso14443b + value: 2 + - name: targ_nfcb + value: 2 + - name: ini_felica + value: 3 + - name: ini_topaz + value: 4 + - name: targ_nfcf + value: 4 + - name: targ_nfcip + value: 7 + - name: ini_subcarrier_stream + value: 14 + - name: ini_bpsk_stream + value: 15 enum/OP_CONTROL_en_fd: bit_size: 2 variants: - - name: efd_off - value: 0 - - name: manual_efd_ca - value: 1 - - name: manual_efd_pdt - value: 2 - - name: auto_efd - value: 3 + - name: efd_off + value: 0 + - name: manual_efd_ca + value: 1 + - name: manual_efd_pdt + value: 2 + - name: auto_efd + value: 3 enum/PASSIVE_TARGET_STATUS_pta_state: bit_size: 4 variants: - - name: power_off - value: 0 - - name: idle - value: 1 - - name: ready_l1 - value: 2 - - name: ready_l2 - value: 3 - - name: rfu4 - value: 4 - - name: active - value: 5 - - name: rfu6 - value: 6 - - name: rfu7 - value: 7 - - name: rfu8 - value: 8 - - name: halt - value: 9 - - name: ready_l1_x - value: 10 - - name: ready_l2_x - value: 11 - - name: rfu12 - value: 12 - - name: active_x - value: 13 + - name: power_off + value: 0 + - name: idle + value: 1 + - name: ready_l1 + value: 2 + - name: ready_l2 + value: 3 + - name: rfu4 + value: 4 + - name: active + value: 5 + - name: rfu6 + value: 6 + - name: rfu7 + value: 7 + - name: rfu8 + value: 8 + - name: halt + value: 9 + - name: ready_l1_x + value: 10 + - name: ready_l2_x + value: 11 + - name: rfu12 + value: 12 + - name: active_x + value: 13 enum/REGULATOR_CONTROL_mpsv: bit_size: 3 variants: - - name: vdd - value: 0 - - name: vdd_a - value: 1 - - name: vdd_d - value: 2 - - name: vdd_rf - value: 3 - - name: vdd_am - value: 4 - - name: rfu - value: 5 - - name: rfu1 - value: 6 - - name: rfu2 - value: 7 + - name: vdd + value: 0 + - name: vdd_a + value: 1 + - name: vdd_d + value: 2 + - name: vdd_rf + value: 3 + - name: vdd_am + value: 4 + - name: rfu + value: 5 + - name: rfu1 + value: 6 + - name: rfu2 + value: 7 enum/RX_CONF1_hz: bit_size: 4 variants: - - name: 60_400khz - value: 0 - - name: 12_200khz - value: 1 - - name: 40_80khz - value: 2 - - name: 12_80khz - value: 3 - - name: 60_200khz - value: 4 - - name: 12_200khz_alt - value: 5 - - name: 600_400khz - value: 8 - - name: 600_200khz - value: 12 + - name: 60_400khz + value: 0 + - name: 12_200khz + value: 1 + - name: 40_80khz + value: 2 + - name: 12_80khz + value: 3 + - name: 60_200khz + value: 4 + - name: 12_200khz_alt + value: 5 + - name: 600_400khz + value: 8 + - name: 600_200khz + value: 12 enum/RX_CONF1_lp: bit_size: 3 variants: - - name: 1200khz - value: 0 - - name: 600khz - value: 1 - - name: 300khz - value: 2 - - name: 2000khz - value: 4 - - name: 7000khz - value: 5 + - name: 1200khz + value: 0 + - name: 600khz + value: 1 + - name: 300khz + value: 2 + - name: 2000khz + value: 4 + - name: 7000khz + value: 5 enum/STREAM_MODE_scf: bit_size: 2 variants: - - name: bpsk848 - value: 0 - - name: sc212 - value: 0 - - name: bpsk1695 - value: 1 - - name: sc424 - value: 1 - - name: bpsk3390 - value: 2 - - name: sc848 - value: 2 - - name: bpsk106 - value: 3 - - name: sc1695 - value: 3 + - name: bpsk848 + value: 0 + - name: sc212 + value: 0 + - name: bpsk1695 + value: 1 + - name: sc424 + value: 1 + - name: bpsk3390 + value: 2 + - name: sc848 + value: 2 + - name: bpsk106 + value: 3 + - name: sc1695 + value: 3 enum/STREAM_MODE_scp: bit_size: 2 variants: - - name: 1pulse - value: 0 - - name: 2pulses - value: 1 - - name: 4pulses - value: 2 - - name: 8pulses - value: 3 + - name: 1pulse + value: 0 + - name: 2pulses + value: 1 + - name: 4pulses + value: 2 + - name: 8pulses + value: 3 enum/STREAM_MODE_stx: bit_size: 3 variants: - - name: "106" - value: 0 - - name: "212" - value: 1 - - name: "424" - value: 2 - - name: "848" - value: 3 + - name: '106' + value: 0 + - name: '212' + value: 1 + - name: '424' + value: 2 + - name: '848' + value: 3 enum/TIMER_EMV_CONTROL_gptc: bit_size: 3 variants: - - name: no_trigger - value: 0 - - name: erx - value: 1 - - name: srx - value: 2 - - name: etx_nfc - value: 3 + - name: no_trigger + value: 0 + - name: erx + value: 1 + - name: srx + value: 2 + - name: etx_nfc + value: 3 enum/TIMER_EMV_CONTROL_mrt_step: bit_size: 1 variants: - - name: "64" - value: 0 - - name: "512" - value: 1 + - name: '64' + value: 0 + - name: '512' + value: 1 enum/TIMER_EMV_CONTROL_nrt_step: bit_size: 1 variants: - - name: 64fc - value: 0 - - name: 4096_fc - value: 1 + - name: 64fc + value: 0 + - name: 4096_fc + value: 1 enum/TX_DRIVER_STATUS_d_tim: bit_size: 3 variants: - - name: slow - value: 0 - - name: medium_slow - value: 1 - - name: nominal - value: 2 - - name: medium_fast - value: 3 - - name: fast - value: 4 + - name: slow + value: 0 + - name: medium_slow + value: 1 + - name: nominal + value: 2 + - name: medium_fast + value: 3 + - name: fast + value: 4 enum/TX_DRIVER_am_mod: bit_size: 4 variants: - - name: 5percent - value: 0 - - name: 6percent - value: 1 - - name: 7percent - value: 2 - - name: 8percent - value: 3 - - name: 9percent - value: 4 - - name: 10percent - value: 5 - - name: 11percent - value: 6 - - name: 12percent - value: 7 - - name: 13percent - value: 8 - - name: 14percent - value: 9 - - name: 15percent - value: 10 - - name: 17percent - value: 11 - - name: 19percent - value: 12 - - name: 22percent - value: 13 - - name: 26percent - value: 14 - - name: 40percent - value: 15 + - name: 5percent + value: 0 + - name: 6percent + value: 1 + - name: 7percent + value: 2 + - name: 8percent + value: 3 + - name: 9percent + value: 4 + - name: 10percent + value: 5 + - name: 11percent + value: 6 + - name: 12percent + value: 7 + - name: 13percent + value: 8 + - name: 14percent + value: 9 + - name: 15percent + value: 10 + - name: 17percent + value: 11 + - name: 19percent + value: 12 + - name: 22percent + value: 13 + - name: 26percent + value: 14 + - name: 40percent + value: 15 From c7e7d7b0bc0d63b0675b89c5950258922f0dfcf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Tue, 4 Mar 2025 15:04:11 +0100 Subject: [PATCH 5/8] review: changes part 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - remove stubs - compact Commands together, cfg's when diffrences - update ci (no chip selection is a compile error) - update st25r39-disco to use feature Signed-off-by: Krzysztof Królczyk --- ci.sh | 4 - examples/st25r39-disco/Cargo.toml | 2 +- rnfc-st25r39/src/commands/cmds_st25r3911b.rs | 68 ---- rnfc-st25r39/src/commands/cmds_st25r3916.rs | 70 ----- rnfc-st25r39/src/commands/mod.rs | 108 ++++++- rnfc-st25r39/src/commands/stub.rs | 15 - rnfc-st25r39/src/impls/mod.rs | 5 - rnfc-st25r39/src/impls/stub.rs | 59 ---- rnfc-st25r39/src/lib.rs | 9 +- rnfc-st25r39/src/regs/mod.rs | 15 +- rnfc-st25r39/src/regs/regs_st25r3916.rs | 9 +- rnfc-st25r39/src/regs/stub.rs | 310 ------------------- 12 files changed, 109 insertions(+), 565 deletions(-) delete mode 100644 rnfc-st25r39/src/commands/cmds_st25r3911b.rs delete mode 100644 rnfc-st25r39/src/commands/cmds_st25r3916.rs delete mode 100644 rnfc-st25r39/src/commands/stub.rs delete mode 100644 rnfc-st25r39/src/impls/stub.rs delete mode 100644 rnfc-st25r39/src/regs/stub.rs diff --git a/ci.sh b/ci.sh index 6eb022c..6c88d4e 100755 --- a/ci.sh +++ b/ci.sh @@ -17,12 +17,8 @@ cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features '' cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features 'defmt' cargo build --release --manifest-path rnfc-fm175xx/Cargo.toml --features 'log' -echo "no-features" -cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features '' -echo "st25r3916" cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3916, defmt' cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3916, log' -echo "st25r3911b" cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3911b, defmt' cargo build --release --manifest-path rnfc-st25r39/Cargo.toml --features 'st25r3911b, log' diff --git a/examples/st25r39-disco/Cargo.toml b/examples/st25r39-disco/Cargo.toml index 69e2243..03ee0d3 100644 --- a/examples/st25r39-disco/Cargo.toml +++ b/examples/st25r39-disco/Cargo.toml @@ -11,7 +11,7 @@ default = [ ] [dependencies] -rnfc-st25r39 = { path = "../../rnfc-st25r39", features = [ "defmt" ] } +rnfc-st25r39 = { path = "../../rnfc-st25r39", features = [ "defmt", "st25r3916" ] } rnfc = { path = "../../rnfc", features = [ "defmt" ] } embassy-executor = { version = "0.7", features = ["defmt", "nightly", "arch-cortex-m", "executor-thread"] } diff --git a/rnfc-st25r39/src/commands/cmds_st25r3911b.rs b/rnfc-st25r39/src/commands/cmds_st25r3911b.rs deleted file mode 100644 index 902c5d8..0000000 --- a/rnfc-st25r39/src/commands/cmds_st25r3911b.rs +++ /dev/null @@ -1,68 +0,0 @@ -/// Direct commands -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[allow(unused)] -pub enum Command { - /// Puts the chip in default state (same as after power-up) - SetDefault = 0xC1, - /// Stops all activities and clears FIFO same as C3 - Stop = 0xC2, - /// Stops all activities and clears FIFO same as C2 - Clear = 0xC3, - /// Transmit with CRC - TransmitWithCrc = 0xC4, - /// Transmit without CRC - TransmitWithoutCrc = 0xC5, - /// Transmit REQA - TransmitReqa = 0xC6, - /// Transmit WUPA - TransmitWupa = 0xC7, - /// NFC transmit with Initial RF Collision Avoidance - InitialRfCollision = 0xC8, - /// NFC transmit with Response RF Collision Avoidance - ResponseRfCollisionN = 0xC9, - /// NFC transmit with Response RF Collision Avoidance with n=0 - ResponseRfCollisionNzero = 0xCA, - /// Accepted in NFCIP-1 active communication bitrate detection mode - GotoNormalNFCMode = 0xCB, - /// Presets Rx and Tx configuration based on state of Mode definition register and Bit rate definition register - PresetAnalog = 0xCC, - /// Mask receive data - MaskReceiveData = 0xD0, - /// Unmask receive data - UnmaskReceiveData = 0xD1, - /// Measure singal amplitude on RFI inputs - MeasureAmplitude = 0xD3, - /// Performs gain reduction based on the current noise level - Squelch = 0xD4, - /// Reset RX Gain - ResetRxgain = 0xD5, - /// Adjust regulators - AdjustRegulators = 0xD6, - /// Starts sequence that activates the Tx, measures the modulation depth, and adapts it to comply with the specified modulation depth - CalibrateModDepth = 0xD7, - /// Starts the sequence to adjust parallel capacitances connected to TRIMx_y pins so that the antenna LC tank is in resonance - CalibrateAntenna = 0xD8, - /// Measurement of phase difference between the signal on RFO and RFI - MeasurePhase = 0xD9, - /// Clear RSSI bits and restart the measurement - ClearRssi = 0xDA, - /// Amplitude of signal present on RFI inputs is measured, result is stored in A/D converter output register - TransparentMode = 0xDC, - /// Calibrate the capacitive sensor - CalibrateCSensor = 0xDD, - /// Measure capacitance sensor - MeasureCapacitance = 0xDE, - /// Measure power supply voltage - MeasureVdd = 0xDF, - /// Start the general purpose timer - StartGpTimer = 0xE0, - /// Start the wake-up timer - StartWupTimer = 0xE1, - /// Start the mask-receive timer - StartMaskReceiveTimer = 0xE2, - /// Start the no-response timer - StartNoResponseTimer = 0xE3, - /// Enable R/W access to the test registers - TestAccess = 0xFC, -} diff --git a/rnfc-st25r39/src/commands/cmds_st25r3916.rs b/rnfc-st25r39/src/commands/cmds_st25r3916.rs deleted file mode 100644 index bc2723b..0000000 --- a/rnfc-st25r39/src/commands/cmds_st25r3916.rs +++ /dev/null @@ -1,70 +0,0 @@ -/// Direct commands -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[allow(unused)] -pub enum Command { - /// Puts the chip in default state (same as after power-up) - SetDefault = 0xC1, - /// Stops all activities and clears FIFO - Stop = 0xC2, - /// Transmit with CRC - TransmitWithCrc = 0xC4, - /// Transmit without CRC - TransmitWithoutCrc = 0xC5, - /// Transmit REQA - TransmitReqa = 0xC6, - /// Transmit WUPA - TransmitWupa = 0xC7, - /// NFC transmit with Initial RF Collision Avoidance - InitialRfCollision = 0xC8, - /// NFC transmit with Response RF Collision Avoidance - ResponseRfCollisionN = 0xC9, - /// Passive target logic to Sense/Idle state - GotoSense = 0xCD, - /// Passive target logic to Sleep/Halt state - GotoSleep = 0xCE, - /// Mask receive data - MaskReceiveData = 0xD0, - /// Unmask receive data - UnmaskReceiveData = 0xD1, - /// AM Modulation state change - AmModStateChange = 0xD2, - /// Measure singal amplitude on RFI inputs - MeasureAmplitude = 0xD3, - /// Reset RX Gain - ResetRxgain = 0xD5, - /// Adjust regulators - AdjustRegulators = 0xD6, - /// Starts the sequence to adjust the driver timing - CalibrateDriverTiming = 0xD8, - /// Measure phase between RFO and RFI signal - MeasurePhase = 0xD9, - /// Clear RSSI bits and restart the measurement - ClearRssi = 0xDA, - /// Clears FIFO, Collision and IRQ status - ClearFifo = 0xDB, - /// Transparent mode - TransparentMode = 0xDC, - /// Calibrate the capacitive sensor - CalibrateCSensor = 0xDD, - /// Measure capacitance - MeasureCapacitance = 0xDE, - /// Measure power supply voltage - MeasureVdd = 0xDF, - /// Start the general purpose timer - StartGpTimer = 0xE0, - /// Start the wake-up timer - StartWupTimer = 0xE1, - /// Start the mask-receive timer - StartMaskReceiveTimer = 0xE2, - /// Start the no-response timer - StartNoResponseTimer = 0xE3, - /// Start PPon2 timer - StartPpon2Timer = 0xE4, - /// Stop No Response Timer - StopNrt = 0xE8, - /// Enable R/W access to the test registers - SpaceBAccess = 0xFB, - /// Enable R/W access to the test registers - TestAccess = 0xFC, -} diff --git a/rnfc-st25r39/src/commands/mod.rs b/rnfc-st25r39/src/commands/mod.rs index 7e21b7c..748486b 100644 --- a/rnfc-st25r39/src/commands/mod.rs +++ b/rnfc-st25r39/src/commands/mod.rs @@ -1,14 +1,94 @@ -#[cfg(feature = "st25r3916")] -pub mod cmds_st25r3916; -#[cfg(feature = "st25r3916")] -pub use cmds_st25r3916::Command; - -#[cfg(feature = "st25r3911b")] -pub mod cmds_st25r3911b; -#[cfg(feature = "st25r3911b")] -pub use cmds_st25r3911b::Command; - -#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] -mod stub; -#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] -pub use stub::Command; +/// Direct commands +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[allow(unused)] +pub enum Command { + /// Puts the chip in default state (same as after power-up) + SetDefault = 0xC1, + /// Stops all activities and clears FIFO same as C3 + Stop = 0xC2, + /// Stops all activities and clears FIFO same as C2 + Clear = 0xC3, + /// Transmit with CRC + TransmitWithCrc = 0xC4, + /// Transmit without CRC + TransmitWithoutCrc = 0xC5, + /// Transmit REQA + TransmitReqa = 0xC6, + /// Transmit WUPA + TransmitWupa = 0xC7, + /// NFC transmit with Initial RF Collision Avoidance + InitialRfCollision = 0xC8, + /// NFC transmit with Response RF Collision Avoidance + ResponseRfCollisionN = 0xC9, + #[cfg(feature = "st25r3911b")] + /// NFC transmit with Response RF Collision Avoidance with n=0 + ResponseRfCollisionNzero = 0xCA, + #[cfg(feature = "st25r3911b")] + /// Accepted in NFCIP-1 active communication bitrate detection mode + GotoNormalNFCMode = 0xCB, + #[cfg(feature = "st25r3911b")] + /// Presets Rx and Tx configuration based on state of Mode definition register and Bit rate definition register + PresetAnalog = 0xCC, + #[cfg(feature = "st25r3916")] + /// Passive target logic to Sense/Idle state + GotoSense = 0xCD, + #[cfg(feature = "st25r3916")] + /// Passive target logic to Sleep/Halt state + GotoSleep = 0xCE, + /// Mask receive data + MaskReceiveData = 0xD0, + /// Unmask receive data + UnmaskReceiveData = 0xD1, + #[cfg(feature = "st25r3916")] + /// AM Modulation state change + AmModStateChange = 0xD2, + /// Measure singal amplitude on RFI inputs + MeasureAmplitude = 0xD3, + #[cfg(feature = "st25r3911b")] + /// Performs gain reduction based on the current noise level + Squelch = 0xD4, + /// Reset RX Gain + ResetRxgain = 0xD5, + /// Adjust regulators + AdjustRegulators = 0xD6, + #[cfg(feature = "st25r3911b")] + /// Starts sequence that activates the Tx, measures the modulation depth, and adapts it to comply with the specified modulation depth + CalibrateModDepth = 0xD7, + /// Starts the sequence to adjust the driver timing. Called CalibrateAntenna in st25r3911b + CalibrateDriverTiming = 0xD8, + /// Measure phase between RFO and RFI signal + MeasurePhase = 0xD9, + /// Clear RSSI bits and restart the measurement + ClearRssi = 0xDA, + #[cfg(feature = "st25r3916")] + /// Clears FIFO, Collision and IRQ status + ClearFifo = 0xDB, + /// Transparent mode - amplitude of signal present on RFI inputs is measured, result is stored in A/D converter output register + TransparentMode = 0xDC, + /// Calibrate the capacitive sensor + CalibrateCSensor = 0xDD, + /// Measure capacitance sensor + MeasureCapacitance = 0xDE, + /// Measure power supply voltage + MeasureVdd = 0xDF, + /// Start the general purpose timer + StartGpTimer = 0xE0, + /// Start the wake-up timer + StartWupTimer = 0xE1, + /// Start the mask-receive timer + StartMaskReceiveTimer = 0xE2, + /// Start the no-response timer + StartNoResponseTimer = 0xE3, + #[cfg(feature = "st25r3916")] + /// Start PPon2 timer + StartPpon2Timer = 0xE4, + #[cfg(feature = "st25r3916")] + /// Stop No Response Timer + StopNrt = 0xE8, + #[cfg(feature = "st25r3916")] + /// Enable R/W access to the test registers + SpaceBAccess = 0xFB, + /// Enable R/W access to the test registers + TestAccess = 0xFC, +} diff --git a/rnfc-st25r39/src/commands/stub.rs b/rnfc-st25r39/src/commands/stub.rs deleted file mode 100644 index cbbcd59..0000000 --- a/rnfc-st25r39/src/commands/stub.rs +++ /dev/null @@ -1,15 +0,0 @@ -/// Direct commands -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[allow(unused)] -pub enum Command { - Stop, - SetDefault = 0xCA, - SetOther = 0xFE, - // required by iso14443a - ResetRxgain, - TransmitReqa, - TransmitWupa, - TransmitWithoutCrc, - TransmitWithCrc, -} diff --git a/rnfc-st25r39/src/impls/mod.rs b/rnfc-st25r39/src/impls/mod.rs index f2e07a0..4324a13 100644 --- a/rnfc-st25r39/src/impls/mod.rs +++ b/rnfc-st25r39/src/impls/mod.rs @@ -8,11 +8,6 @@ pub mod lib_st25r3911b; #[cfg(feature = "st25r3911b")] pub use lib_st25r3911b::*; -#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] -mod stub; -#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] -pub use stub::*; - // TODO: check wup and other wake-up registers in st25r3911b #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/rnfc-st25r39/src/impls/stub.rs b/rnfc-st25r39/src/impls/stub.rs deleted file mode 100644 index b863f37..0000000 --- a/rnfc-st25r39/src/impls/stub.rs +++ /dev/null @@ -1,59 +0,0 @@ -use embedded_hal::digital::InputPin; -use embedded_hal_async::digital::Wait; - -use super::WakeupConfig; -use crate::commands::Command; -use crate::impls::FieldOnError; -use crate::regs::Regs; -use crate::{Error, Interface, Mode, St25r39}; - -impl St25r39 { - pub async fn new(iface: I, irq: IrqPin) -> Result> { - Ok(Self { - iface, - irq, - irqs: 0, - mode: Mode::Off, - }) - } - pub async fn mode_on(&mut self) -> Result<(), FieldOnError> { - self.mode = Mode::On; - let _ = Mode::Wakeup; - Ok(()) - } - pub fn mode_off(&mut self) -> Result<(), FieldOnError> { - self.mode = Mode::Off; - let _ = self.irq; - Ok(()) - } - pub async fn field_on(&self) -> Result<(), FieldOnError> { - Ok(()) - } - pub async fn field_off(&self) -> Result<(), Error> { - Ok(()) - } - pub fn cmd(&mut self, _cmd: Command) -> Result<(), Error> { - Ok(()) - } - pub fn regs(&mut self) -> Regs { - crate::regs::Regs::new(&mut self.iface) - } - pub fn irq_update(&mut self) -> Result<(), Error> { - Ok(()) - } - pub fn irq(&mut self, _irq: Interrupt) -> bool { - true - } - pub async fn wait_for_card(&self, _: WakeupConfig) -> Result<(), Error> { - Ok(()) - } -} - -pub enum Interrupt { - // required by iso14443a - Err1, - Par, - Crc, - Col, - Rxe, -} diff --git a/rnfc-st25r39/src/lib.rs b/rnfc-st25r39/src/lib.rs index 1d083db..740b17b 100644 --- a/rnfc-st25r39/src/lib.rs +++ b/rnfc-st25r39/src/lib.rs @@ -5,9 +5,9 @@ // This must go FIRST so that other mods see its macros. mod fmt; -// no-chip-specified, maybe it'd be useful to have common api -// or support a mock, in case some tests to validate calculations? -#[cfg(any(feature = "st25r3911b", feature = "st25r3916"))] +#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] +compile_error!("A chip/feature has to be selected in Cargo.toml"); + mod aat; pub mod commands; pub mod impls; @@ -28,8 +28,11 @@ pub enum Error { #[derive(PartialEq, Eq, Clone, Copy)] enum Mode { + /// SPI running, AFE static power consumpton mnimized Off, + /// Ready mode On, + /// Low power mode, card presence detection Wakeup, } diff --git a/rnfc-st25r39/src/regs/mod.rs b/rnfc-st25r39/src/regs/mod.rs index e32b24c..8ceac51 100644 --- a/rnfc-st25r39/src/regs/mod.rs +++ b/rnfc-st25r39/src/regs/mod.rs @@ -1,5 +1,6 @@ #[cfg(feature = "st25r3911b")] mod regs_st25r3911b; +use core::marker::PhantomData; #[cfg(feature = "st25r3911b")] pub use regs_st25r3911b::*; @@ -9,17 +10,9 @@ mod regs_st25r3916; #[cfg(feature = "st25r3916")] pub use regs_st25r3916::*; -#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] -mod stub; -use core::marker::PhantomData; - -#[cfg(all(not(feature = "st25r3911b"), not(feature = "st25r3916")))] -pub use stub::*; - use crate::interface::Interface; use crate::Error; -// TODO: if this api is set, then maybe one somehow could remove some bolierplate generation for regs pub struct Reg<'a, I: Interface, T: Copy> { addr: u8, iface: &'a mut I, @@ -59,9 +52,3 @@ impl<'a, I: Interface, T: Default + Copy + Into + From> Reg<'a, I, T> { Ok(res) } } - -// just for stub -#[cfg(not(any(feature = "st25r3911b", feature = "st25r3916")))] -pub struct Regs<'a, I: Interface> { - iface: &'a mut I, -} diff --git a/rnfc-st25r39/src/regs/regs_st25r3916.rs b/rnfc-st25r39/src/regs/regs_st25r3916.rs index cb3f404..4d093a8 100644 --- a/rnfc-st25r39/src/regs/regs_st25r3916.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3916.rs @@ -118,6 +118,10 @@ impl<'a, I: Interface> Regs<'a, I> { pub fn ppon2(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 21) } + pub fn irq_mask(&mut self, n: u8) -> Reg<'_, I, u8> { + assert!(n < 4); + Reg::new(self.iface, 22 + n) + } pub fn irq_mask_main(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 22) } @@ -130,8 +134,9 @@ impl<'a, I: Interface> Regs<'a, I> { pub fn irq_mask_target(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 25) } - pub fn irq_main(&mut self) -> Reg<'_, I, u8> { - Reg::new(self.iface, 26) + pub fn irq_main(&mut self, n: u8) -> Reg<'_, I, u8> { + assert!(n < 4); + Reg::new(self.iface, 26 + n) } pub fn irq_timer_nfc(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 27) diff --git a/rnfc-st25r39/src/regs/stub.rs b/rnfc-st25r39/src/regs/stub.rs deleted file mode 100644 index 7e765fd..0000000 --- a/rnfc-st25r39/src/regs/stub.rs +++ /dev/null @@ -1,310 +0,0 @@ -use super::{Reg, Regs}; -use crate::Interface; - -impl<'a, I: Interface> Regs<'a, I> { - pub fn new(iface: &'a mut I) -> Self { - Self { iface } - } - - /// IO configuration register 1 - pub fn io_conf1(&mut self) -> Reg<'_, I, u8> { - Reg::new(self.iface, 0) - } - pub fn aux(&mut self) -> Reg<'_, I, Aux> { - Reg::new(self.iface, 1) - } - pub fn rx_conf2(&mut self) -> Reg<'_, I, RxConf2> { - Reg::new(self.iface, 0) - } - pub fn num_tx_bytes2(&mut self) -> Reg<'_, I, u8> { - Reg::new(self.iface, 0) - } - pub fn num_tx_bytes1(&mut self) -> Reg<'_, I, u8> { - Reg::new(self.iface, 0) - } - pub fn fifo_status1(&mut self) -> Reg<'_, I, u8> { - Reg::new(self.iface, 0) - } - pub fn fifo_status2(&mut self) -> Reg<'_, I, FifoStatus2> { - Reg::new(self.iface, 0) - } - pub fn iso14443a_nfc(&mut self) -> Reg<'_, I, Iso14443ANfc> { - Reg::new(self.iface, 0) - } - pub fn collision_status(&mut self) -> Reg<'_, I, CollisionStatus> { - Reg::new(self.iface, 0) - } -} - -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Aux(pub u8); -impl Aux { - pub const fn nfc_n(&self) -> u8 { - let val = (self.0 >> 0_usize) & 2; - val as u8 - } - pub fn set_nfc_n(&mut self, val: u8) { - self.0 = (self.0 & !(2 << 0_usize)) | ((val as u8) & 2) << 0_usize; - } - pub const fn rx_tol(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 - } - pub fn set_rx_tol(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn ook_hr(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 - } - pub fn set_ook_hr(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; - } - pub const fn en_fd(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; - val != 0 - } - pub fn set_en_fd(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; - } - pub const fn tr_am(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 - } - pub fn set_tr_am(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn crc_2_fifo(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 - } - pub fn set_crc_2_fifo(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; - } - pub const fn no_crc_rx(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 - } - pub fn set_no_crc_rx(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; - } -} -impl Default for Aux { - fn default() -> Aux { - Aux(0) - } -} -impl From for Aux { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: Aux) -> u8 { - val.0 - } -} - -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct RxConf2(pub u8); -impl RxConf2 { - pub const fn pmix_cl(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub fn set_pmix_cl(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn sqm_dyn(&self) -> bool { - let val = (self.0 >> 1_usize) & 1; - val != 0 - } - pub fn set_sqm_dyn(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 1_usize)) | ((val as u8) & 1) << 1_usize; - } - pub const fn agc_alg(&self) -> bool { - let val = (self.0 >> 2_usize) & 1; - val != 0 - } - pub fn set_agc_alg(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 2_usize)) | ((val as u8) & 1) << 2_usize; - } - pub const fn agc_m(&self) -> bool { - let val = (self.0 >> 3_usize) & 1; - val != 0 - } - pub fn set_agc_m(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 3_usize)) | ((val as u8) & 1) << 3_usize; - } - pub const fn agc_en(&self) -> bool { - let val = (self.0 >> 4_usize) & 1; - val != 0 - } - pub fn set_agc_en(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 4_usize)) | ((val as u8) & 1) << 4_usize; - } - pub const fn lf_en(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 - } - pub fn set_lf_en(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn lf_op(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 - } - pub fn set_lf_op(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; - } - pub const fn rx_lp(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 - } - pub fn set_rx_lp(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; - } -} -impl Default for RxConf2 { - fn default() -> RxConf2 { - RxConf2(0) - } -} -impl From for RxConf2 { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: RxConf2) -> u8 { - val.0 - } -} - -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FifoStatus2(pub u8); -impl FifoStatus2 { - pub const fn np_lb(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub const fn fifo_lb(&self) -> u8 { - let val = (self.0 >> 1_usize) & 3; - val as u8 - } - pub const fn fifo_ovr(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 - } - pub const fn fifo_unf(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 - } -} -impl Default for FifoStatus2 { - fn default() -> FifoStatus2 { - FifoStatus2(0) - } -} -impl From for FifoStatus2 { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: FifoStatus2) -> u8 { - val.0 - } -} - -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Iso14443ANfc(pub u8); -impl Iso14443ANfc { - pub const fn antcl(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub fn set_antcl(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 0_usize)) | ((val as u8) & 1) << 0_usize; - } - pub const fn p_len(&self) -> u8 { - let val = (self.0 >> 1_usize) & 4; - val as u8 - } - pub fn set_p_len(&mut self, val: u8) { - self.0 = (self.0 & !(4 << 1_usize)) | ((val as u8) & 4) << 1_usize; - } - pub const fn nfc_f0(&self) -> bool { - let val = (self.0 >> 5_usize) & 1; - val != 0 - } - pub fn set_nfc_f0(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 5_usize)) | ((val as u8) & 1) << 5_usize; - } - pub const fn no_rx_par(&self) -> bool { - let val = (self.0 >> 6_usize) & 1; - val != 0 - } - pub fn set_no_rx_par(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 6_usize)) | ((val as u8) & 1) << 6_usize; - } - pub const fn no_tx_par(&self) -> bool { - let val = (self.0 >> 7_usize) & 1; - val != 0 - } - pub fn set_no_tx_par(&mut self, val: bool) { - self.0 = (self.0 & !(1 << 7_usize)) | ((val as u8) & 1) << 7_usize; - } -} -impl Default for Iso14443ANfc { - fn default() -> Iso14443ANfc { - Iso14443ANfc(0) - } -} -impl From for Iso14443ANfc { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: Iso14443ANfc) -> u8 { - val.0 - } -} - -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct CollisionStatus(pub u8); -impl CollisionStatus { - pub const fn c_pb(&self) -> bool { - let val = (self.0 >> 0_usize) & 1; - val != 0 - } - pub const fn c_bit(&self) -> u8 { - let val = (self.0 >> 1_usize) & 3; - val as u8 - } - pub const fn c_byte(&self) -> u8 { - let val = (self.0 >> 4_usize) & 4; - val as u8 - } -} -impl Default for CollisionStatus { - fn default() -> CollisionStatus { - CollisionStatus(0) - } -} -impl From for CollisionStatus { - fn from(val: u8) -> Self { - Self(val) - } -} -impl From for u8 { - fn from(val: CollisionStatus) -> u8 { - val.0 - } -} From 8d1ce6f24220eb49295dff4109e8e754463fc38b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Mon, 31 Mar 2025 18:41:00 +0200 Subject: [PATCH 6/8] review: changes part 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - combined the implementation back to one file, different/not supported features on the older chip are guarded by feature gates. - IRQs adjusted to handle differences between chips. - dropped unrelated changes Signed-off-by: Krzysztof Królczyk --- rnfc-st25r39/src/commands/mod.rs | 9 +- rnfc-st25r39/src/impls/lib.rs | 535 +++++++++++++++++++++++ rnfc-st25r39/src/impls/lib_st25r3911b.rs | 493 +-------------------- rnfc-st25r39/src/impls/lib_st25r3916.rs | 461 ------------------- rnfc-st25r39/src/impls/mod.rs | 2 + rnfc-st25r39/src/regs/mod.rs | 2 +- rnfc-st25r39/src/regs/regs_st25r3911b.rs | 18 +- 7 files changed, 563 insertions(+), 957 deletions(-) create mode 100644 rnfc-st25r39/src/impls/lib.rs diff --git a/rnfc-st25r39/src/commands/mod.rs b/rnfc-st25r39/src/commands/mod.rs index 748486b..1d8d5ce 100644 --- a/rnfc-st25r39/src/commands/mod.rs +++ b/rnfc-st25r39/src/commands/mod.rs @@ -3,6 +3,9 @@ #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[allow(unused)] pub enum Command { + // #[cfg(feature = "st25r3916")] + // Puts the chip in default state, st25r39{16,20} (same as after power-up) + // SetDefault1 = 0xC0, /// Puts the chip in default state (same as after power-up) SetDefault = 0xC1, /// Stops all activities and clears FIFO same as C3 @@ -55,7 +58,11 @@ pub enum Command { #[cfg(feature = "st25r3911b")] /// Starts sequence that activates the Tx, measures the modulation depth, and adapts it to comply with the specified modulation depth CalibrateModDepth = 0xD7, - /// Starts the sequence to adjust the driver timing. Called CalibrateAntenna in st25r3911b + #[cfg(feature = "st25r3911b")] + /// Calibrates antenna + CalibrateAntenna = 0xD8, + #[cfg(feature = "st25r3916")] + /// Starts the sequence to adjust the driver timing. CalibrateDriverTiming = 0xD8, /// Measure phase between RFO and RFI signal MeasurePhase = 0xD9, diff --git a/rnfc-st25r39/src/impls/lib.rs b/rnfc-st25r39/src/impls/lib.rs new file mode 100644 index 0000000..af18fcc --- /dev/null +++ b/rnfc-st25r39/src/impls/lib.rs @@ -0,0 +1,535 @@ +use embassy_futures::yield_now; +use embassy_time::{Duration, Instant}; +use embedded_hal::digital::InputPin; +use embedded_hal_async::digital::Wait; + +// use crate::aat::AatConfig; +use crate::commands::Command; +use crate::interface::Interface; +use crate::regs::{self, Regs}; +use crate::{Error, Mode, St25r39}; +pub const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); +use crate::impls::*; + +impl St25r39 { + pub async fn new(iface: I, irq: IrqPin) -> Result> { + let mut this = Self { + iface, + irq, + irqs: 0, + mode: Mode::On, + }; + this.init().await?; + Ok(this) + } + + pub fn regs(&mut self) -> Regs { + Regs::new(&mut self.iface) + } + + pub fn cmd(&mut self, cmd: Command) -> Result<(), Error> { + self.iface.do_command(cmd as u8).map_err(Error::Interface) + } + + async fn cmd_wait(&mut self, cmd: Command) -> Result<(), Error> { + self.irq_clear()?; + self.cmd(cmd)?; + self.irq_wait(Interrupt::Dct).await + } + + async fn enable_osc(&mut self) -> Result<(), Error> { + trace!("Starting osc..."); + self.regs().op_control().write(|w| w.set_en(true))?; + while !self.regs().aux_display().read()?.osc_ok() {} + Ok(()) + } + + async fn init(&mut self) -> Result<(), Error> { + self.cmd(Command::SetDefault)?; + + #[cfg(feature = "st25r3916")] + self.regs().test_unk().write(|w| { + w.set_dis_overheat_prot(true); + })?; + + let id = self.regs().ic_identity().read()?; + trace!("ic_type = {:02x} ic_rev = {:02x}", id.ic_type().0, id.ic_rev().0); + + // Enable OSC + self.enable_osc().await?; + + // Measure vdd + trace!("measuring vdd..."); + let vdd_mv = self.measure_vdd().await?; + trace!("measure vdd result = {}mv", vdd_mv); + + let sup3v = vdd_mv < 3600; + if sup3v { + #[cfg(feature = "st25r3911b")] + self.regs().io_conf2().write(|w| { + w.set_sup_3v(sup3v); + })?; + trace!("using 3v3 supply mode"); + } else { + // default value + trace!("using 5v supply mode"); + } + + // Disable MCU_CLK + self.regs().io_conf1().write(|w| { + w.set_out_cl(regs::IoConf1OutCl::DISABLED); + w.set_lf_clk_off(true); + #[cfg(feature = "st25r3911b")] + // use 27.12Mhz Xtal + w.set_osc(true); + })?; + + // Enable minimum non-overlap + //self.regs().res_am_mod().write(|w| w.set_fa3_f(true))?; + + // Set ext field detect activ/deactiv thresholds + //self.regs().field_threshold_actv().write(|w| { + // w.set_trg(regs::FieldThresholdActvTrg::_105MV); + // w.set_rfe(regs::FieldThresholdActvRfe::_105MV); + //})?; + //self.regs().field_threshold_deactv().write(|w| { + // w.set_trg(regs::FieldThresholdDeactvTrg::_75MV); + // w.set_rfe(regs::FieldThresholdDeactvRfe::_75MV); + //})?; + + //self.regs().aux_mod().write(|w| { + // w.set_lm_ext(false); // Disable external Load Modulation + // w.set_lm_dri(true); // Enable internal Load Modulation + //})?; + + //self.regs().emd_sup_conf().write(|w| { + // w.set_rx_start_emv(true); + //})?; + + // AAT not in use + //self.regs().ant_tune_a().write_value(0x82)?; + //self.regs().ant_tune_b().write_value(0x82)?; + + // Enable external field detector automatically. + #[cfg(feature = "st25r3916")] + self.regs().op_control().modify(|w| { + w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); + })?; + // Enable external field detector. + #[cfg(feature = "st25r3911b")] + self.regs().aux().modify(|w| { + w.set_en_fd(true); + })?; + + // Adjust regulators + + // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. + #[cfg(feature = "st25r3916")] + self.regs().regulator_control().write(|w| w.set_reg_s(true))?; + #[cfg(feature = "st25r3916")] + self.regs().regulator_control().write(|w| w.set_reg_s(false))?; + #[cfg(feature = "st25r3911b")] + self.regs().regulator_volt_control().write(|w| w.set_reg_s(true))?; + #[cfg(feature = "st25r3911b")] + self.regs().regulator_volt_control().write(|w| w.set_reg_s(false))?; + + self.cmd_wait(Command::AdjustRegulators).await?; + + #[cfg(feature = "st25r3916")] + let res = self.regs().regulator_result().read()?.0; + #[cfg(feature = "st25r3911b")] + let res = self.regs().regulator_and_tim_disp().read()?.0; + trace!("reg result = {}", res); + + Ok(()) + } + + pub async fn measure_amplitude(&mut self) -> Result> { + self.cmd_wait(Command::MeasureAmplitude).await?; + self.regs().ad_result().read() + } + + pub async fn measure_phase(&mut self) -> Result> { + self.cmd_wait(Command::MeasurePhase).await?; + self.regs().ad_result().read() + } + + pub async fn measure_capacitance(&mut self) -> Result> { + self.cmd_wait(Command::MeasureCapacitance).await?; + self.regs().ad_result().read() + } + + pub async fn calibrate_capacitance(&mut self) -> Result> { + self.regs().cap_sensor_control().write(|w| { + // Clear Manual calibration values to enable automatic calibration mode + w.set_cs_mcal(0); + w.set_cs_g(0b01); // 6.5v/pF, highest one + })?; + + // Don't use `cmd_wait`, the irq only fires in Ready mode (op_control.en = 1). + // Instead, wait for cap_sensor_result.cs_cal_end + self.cmd(Command::CalibrateCSensor)?; + + let deadline = Instant::now() + DEFAULT_TIMEOUT; + + let res = loop { + if Instant::now() > deadline { + return Err(Error::Timeout); + } + + let res = self.regs().cap_sensor_result().read()?; + if res.cs_cal_err() { + panic!("Capacitive sensor calibration failed!"); + } + if res.cs_cal_end() { + break res; + } + + yield_now().await; + }; + Ok(res.cs_cal_val()) + } + + pub(crate) async fn mode_on(&mut self) -> Result<(), Error> { + self.mode = Mode::On; + self.enable_osc().await?; + + #[cfg(feature = "st25r3916")] + self.regs().op_control().modify(|w| { + w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); + })?; + #[cfg(feature = "st25r3911b")] + self.regs().aux().modify(|w| { + w.set_en_fd(true); + })?; + + // RFO driver resistance, set to 8.3 + #[cfg(feature = "st25r3916")] + self.regs().tx_driver().write(|w| { + w.set_d_res(3); + })?; + #[cfg(feature = "st25r3911b")] + self.regs().rfo_normal_level_def().write(|w| { + w.set_d5(true); + })?; + + Ok(()) + } + + pub(crate) fn mode_off(&mut self) -> Result<(), Error> { + self.mode = Mode::Off; + self.cmd(Command::Stop)?; + // disable everything + self.regs().op_control().write(|_| {})?; + Ok(()) + } + + /// Change into wakeup mode, return immediately. + /// The IRQ pin will go high on wakeup. + pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { + self.mode_on().await?; + + self.mode = Mode::Wakeup; + debug!("Entering wakeup mode"); + + self.cmd(Command::Stop)?; + self.regs().op_control().write(|_| {})?; + self.regs().mode().write(|w| w.set_om(regs::ModeOm::INI_ISO14443A))?; + + let mut wtc = regs::WupTimerControl(0); + let mut irqs = 0; + + wtc.set_wur(config.period as u8 & 0x10 == 0); + wtc.set_wut(config.period as u8 & 0x0F); + + if let Some(m) = config.inductive_amplitude { + let mut conf = regs::AmplitudeMeasureConf(0); + conf.set_am_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().amplitude_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_amplitude().await?; + self.regs().amplitude_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_amplitude().await?; + self.regs().amplitude_measure_ref().write_value(val)?; + conf.set_am_ae(true); + conf.set_am_aam(include_irq_measurement); + conf.set_am_aew(weight); + } + } + self.regs().amplitude_measure_conf().write_value(conf)?; + wtc.set_wam(true); + irqs |= 1 << Interrupt::Wam as u32; + } + if let Some(m) = config.inductive_phase { + let mut conf = regs::PhaseMeasureConf(0); + conf.set_pm_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().phase_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_phase().await?; + self.regs().phase_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_phase().await?; + self.regs().phase_measure_ref().write_value(val)?; + conf.set_pm_ae(true); + conf.set_pm_aam(include_irq_measurement); + conf.set_pm_aew(weight); + } + } + self.regs().phase_measure_conf().write_value(conf)?; + wtc.set_wph(true); + irqs |= 1 << Interrupt::Wph as u32; + } + if let Some(m) = config.capacitive { + debug!("capacitance calibrating..."); + let val = self.calibrate_capacitance().await?; + info!("capacitance calibrated: {}", val); + + let mut conf = regs::CapacitanceMeasureConf(0); + conf.set_cm_d(m.delta); + match m.reference { + WakeupReference::Manual(val) => { + self.regs().capacitance_measure_ref().write_value(val)?; + } + WakeupReference::Automatic => { + let val = self.measure_capacitance().await?; + info!("Measured: {}", val); + self.regs().capacitance_measure_ref().write_value(val)?; + } + WakeupReference::AutoAverage { + include_irq_measurement, + weight, + } => { + let val = self.measure_capacitance().await?; + info!("Measured: {}", val); + self.regs().capacitance_measure_ref().write_value(val)?; + conf.set_cm_ae(true); + conf.set_cm_aam(include_irq_measurement); + conf.set_cm_aew(weight); + } + } + self.regs().capacitance_measure_conf().write_value(conf)?; + #[cfg(feature = "st25r3916")] + wtc.set_wcap(true); + irqs |= 1 << Interrupt::Wcap as u32; + } + + self.irq_clear()?; + + self.regs().wup_timer_control().write_value(wtc)?; + self.regs().op_control().write(|w| w.set_wu(true))?; + self.irq_set_mask(!irqs)?; + + debug!("Entered wakeup mode, waiting for pin IRQ"); + self.irq.wait_for_high().await.unwrap(); + debug!("got pin IRQ!"); + + Ok(()) + } + + pub async fn field_on(&mut self) -> Result<(), FieldOnError> { + self.regs().mode().write(|w| { + w.set_om(regs::ModeOm::INI_ISO14443A); + #[cfg(feature = "st25r3916")] + w.set_tr_am(false); // use OOK + })?; + #[cfg(feature = "st25r3911b")] + self.regs().aux().write(|w| { + w.set_tr_am(false); // use OOK + })?; + + #[cfg(feature = "st25r3916")] + self.regs().tx_driver().write(|w| { + w.set_am_mod(regs::TxDriverAmMod::_12PERCENT); + })?; + #[cfg(feature = "st25r3911b")] + self.regs().am_mod_depth_ctrl().write(|w| { + w.set_am_s(false); + w.set_modd(0b010010) // 12.3%, see table 17 + })?; + + #[cfg(feature = "st25r3916")] + self.regs().aux_mod().write(|w| { + w.set_lm_dri(true); // Enable internal Load Modulation + w.set_dis_reg_am(false); // Enable regulator-based AM + w.set_res_am(false); + })?; + + #[cfg(feature = "st25r3916")] + // Default over/under-shoot protection + self.regs().overshoot_conf1().write_value(0x40.into())?; + #[cfg(feature = "st25r3916")] + self.regs().overshoot_conf2().write_value(0x03.into())?; + #[cfg(feature = "st25r3916")] + self.regs().undershoot_conf1().write_value(0x40.into())?; + #[cfg(feature = "st25r3916")] + self.regs().undershoot_conf2().write_value(0x03.into())?; + + #[cfg(feature = "st25r3916")] + self.regs().aux().write(|w| { + w.set_dis_corr(false); // Enable correlator reception + w.set_nfc_n(0); // todo this changes + })?; + /* + self.regs().rx_conf1().write_value(0x08.into())?; + self.regs().rx_conf2().write_value(0x2D.into())?; + self.regs().rx_conf3().write_value(0x00.into())?; + self.regs().rx_conf4().write_value(0x00.into())?; + self.regs().corr_conf1().write_value(0x51.into())?; + self.regs().corr_conf2().write_value(0x00.into())?; + */ + + self.regs().bit_rate().write(|w| { + w.set_rxrate(regs::BitRateE::_106); + w.set_txrate(regs::BitRateE::_106); + })?; + + // defaults + self.regs().iso14443a_nfc().write(|_| {})?; + + // Field ON + + #[cfg(feature = "st25r3916")] + // GT is done by software, GT = guard timer, see table 57 + self.regs().field_on_gt().write_value(0)?; + + self.irq_clear()?; // clear + self.cmd(Command::InitialRfCollision)?; + + loop { + if self.irq(Interrupt::Cac) { + return Err(FieldOnError::FieldCollision); + } + #[cfg(feature = "st25r3911b")] + if self.irq(Interrupt::Cat) { + break; + } + #[cfg(feature = "st25r3916")] + if self.irq(Interrupt::Apon) { + break; + } + + self.irq_update()?; + } + + self.regs().op_control().modify(|w| { + w.set_tx_en(true); + w.set_rx_en(true); + })?; + + Ok(()) + } + + async fn measure_vdd(&mut self) -> Result> { + #[cfg(feature = "st25r3916")] + self.regs() + .regulator_control() + .write(|w| w.set_mpsv(regs::RegulatorControlMpsv::VDD))?; + #[cfg(feature = "st25r3911b")] + self.regs().regulator_volt_control().write(|w| w.set_mpsv(0))?; + + self.cmd_wait(Command::MeasureVdd).await?; + let res = self.regs().ad_result().read()? as u32; + + // result is in units of 23.4mV + Ok((res * 234 + 5) / 10) + } + + // ======================= + // irq stuff + + pub fn irq(&self, irq: Interrupt) -> bool { + return (self.irqs & (1 << (irq as u8))) != 0; + } + + pub async fn irq_wait_timeout(&mut self, irq: Interrupt, timeout: Duration) -> Result<(), Error> { + let deadline = Instant::now() + timeout; + self.irq_update()?; + while !self.irq(irq) { + if Instant::now() > deadline { + return Err(Error::Timeout); + } + yield_now().await; + self.irq_update()?; + } + Ok(()) + } + + pub async fn irq_wait(&mut self, irq: Interrupt) -> Result<(), Error> { + self.irq_wait_timeout(irq, DEFAULT_TIMEOUT).await + } + + pub fn irq_update(&mut self) -> Result<(), Error> { + #[cfg(feature = "st25r3911b")] + const REGS_CNT: u8 = 3; + #[cfg(feature = "st25r3916")] + const REGS_CNT: u8 = 4; + for i in 0..REGS_CNT { + self.irqs |= (self.regs().irq_main(i).read()? as u32) << (i * 8); + } + Ok(()) + } + + fn irq_clear(&mut self) -> Result<(), Error> { + self.irq_update()?; + self.irqs = 0; + Ok(()) + } + + fn irq_set_mask(&mut self, mask: u32) -> Result<(), Error> { + for i in 0..4 { + self.regs().irq_mask(i).write_value((mask >> (i * 8)) as u8)?; + } + Ok(()) + } + + pub fn raw(&mut self) -> Raw<'_, I, IrqPin> { + Raw { inner: self } + } +} + +pub struct Raw<'a, I: Interface, IrqPin: InputPin + Wait> { + inner: &'a mut St25r39, +} + +impl<'a, I: Interface, IrqPin: InputPin + Wait> Raw<'a, I, IrqPin> { + pub async fn field_on(&mut self) -> Result<(), FieldOnError> { + self.inner.mode_on().await?; + self.inner.field_on().await?; + Ok(()) + } + pub async fn field_off(&mut self) -> Result<(), Error> { + self.inner.mode_off()?; + Ok(()) + } + + pub async fn driver_hi_z(&mut self) -> Result<(), Error> { + self.inner.mode_off()?; + + #[cfg(feature = "st25r3916")] + self.inner.regs().tx_driver().write(|w| { + w.set_d_res(15); // hi-z + })?; + #[cfg(feature = "st25r3911b")] + self.inner + .regs() + .rfo_normal_level_def() + .write_value(regs::regs_st25r3911b::RfoAmLevelDef(0xff))?; + + Ok(()) + } +} diff --git a/rnfc-st25r39/src/impls/lib_st25r3911b.rs b/rnfc-st25r39/src/impls/lib_st25r3911b.rs index 4a44eab..4fd5250 100644 --- a/rnfc-st25r39/src/impls/lib_st25r3911b.rs +++ b/rnfc-st25r39/src/impls/lib_st25r3911b.rs @@ -1,22 +1,6 @@ -#![allow(async_fn_in_trait)] -#![deny(unused_must_use)] - -use embassy_futures::yield_now; -use embassy_time::{with_timeout, Duration, Instant, Timer}; -use embedded_hal::digital::InputPin; -use embedded_hal_async::digital::Wait; - -use crate::commands::Command; -use crate::impls::{FieldOnError, WakeupConfig, WakeupReference}; -use crate::interface::Interface; -use crate::regs::Regs; -use crate::{regs, Error, Mode, St25r39}; -const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); - -// TODO: This is here temporarily, just to provide abstraction similar to st25r3916. -// Thus - bits do not match. -// This chip offers 3 different registers for IRQs. -// Possibly whole IRQ handling would need to be done differently. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[allow(unused)] pub enum Interrupt { /// IRQ due to error and wake-up timer Err = 0, @@ -66,475 +50,4 @@ pub enum Interrupt { Par = 22, /// CRC error interrupt Crc = 23, - /// RXE with an automatic response interrupt - RxePta = 28, - /// Anticollision done and Field On interrupt - Apon = 29, -} - -/// Device starts with default configuration. Initially the oscillator is not enabled. -/// It's possible to verify register contents; then call `configure` to enable RF. -impl St25r39 { - pub async fn new(iface: I, irq: IrqPin) -> Result> { - let mut this = Self { - iface, - irq, - irqs: 0, - mode: Mode::Off, - }; - this.init().await?; - //this.configure(); - // preferably called by user, - // after checking IC_rev, ect - // otherwise we might spin forever waiting for OSC - Ok(this) - } - - pub fn regs(&mut self) -> Regs { - Regs::::new(&mut self.iface) - } - - pub fn cmd(&mut self, cmd: Command) -> Result<(), Error> { - self.iface.do_command(cmd as u8).map_err(Error::Interface) - } - - async fn cmd_wait(&mut self, cmd: Command) -> Result<(), Error> { - self.irq_clear()?; - self.cmd(cmd)?; - match self.regs().irq_timer_nfc().read()?.dcd() { - true => Ok(()), - false => Err(Error::Timeout), - } - } - - async fn is_osc_stable(&mut self) -> Result<(), Error> { - let failed = Err(Error::Timeout); - match with_timeout( - DEFAULT_TIMEOUT / 10, // table 101, Tosc max 10ms, we'll wait 50ms - async { self.regs().aux_display().read() }, - ) - .await - { - Ok(val) => { - if val?.osc_ok() { - Ok(()) - } else { - failed - } - } - Err(_) => failed, - } - } - - pub async fn enable_osc(&mut self) -> Result<(), Error> { - trace!("Starting osc..."); - if self.is_osc_stable().await.is_err() { - self.regs().op_control().write(|w| w.set_en(true))?; - } - self.is_osc_stable().await - } - - async fn init(&mut self) -> Result<(), Error> { - self.cmd(Command::SetDefault)?; - self.cmd(Command::Clear)?; - - let id = self.regs().ic_identity().read()?; - trace!("ic_type = {:02x} ic_rev = {:02x}", id.ic_type().0, id.ic_rev().0); - - Ok(()) - } - - pub async fn mcu_clk_off(&mut self) -> Result<(), Error> { - // Disable MCU_CLK (default, on power-up is 3.39MHz) - self.regs().io_conf1().write(|w| { - w.set_out_cl(regs::IoConf1OutCl::DISABLED); - w.set_osc(true); // use 27.12Mhz Xtal - })?; - - match self.regs().io_conf1().read()?.out_cl() == regs::IoConf1OutCl::DISABLED { - true => Ok(()), - false => Err(Error::Timeout), - } - } - - pub async fn configure(&mut self) -> Result<(), Error> { - self.irq_clear()?; - // Enable OSC - self.enable_osc().await?; - self.irq_clear()?; // mask osc first - - // Measure vdd - trace!("measuring vdd..."); - let vdd_mv = self.measure_vdd().await?; - trace!("measure vdd result = {}mv", vdd_mv); - - let sup3v = vdd_mv < 3600; - if sup3v { - self.regs().io_conf2().write(|w| { - w.set_sup_3v(sup3v); - })?; - trace!("using 3v3 supply mode"); - } else { - trace!("using 5v supply mode"); - } - - // Disable MCU_CLK, default on power-up 3.39MHz - self.regs().io_conf1().write(|w| { - w.set_out_cl(regs::IoConf1OutCl::DISABLED); - w.set_osc(true); // use 27.12Mhz Xtal - })?; - - // Enable minimum non-overlap - //self.regs().res_am_mod().write(|w| w.set_fa3_f(true))?; - - // Set ext field detect activ/deactiv thresholds - //self.regs().field_threshold_actv().write(|w| { - // w.set_trg(regs::FieldThresholdActvTrg::_105MV); - // w.set_rfe(regs::FieldThresholdActvRfe::_105MV); - //})?; - //self.regs().field_threshold_deactv().write(|w| { - // w.set_trg(regs::FieldThresholdDeactvTrg::_75MV); - // w.set_rfe(regs::FieldThresholdDeactvRfe::_75MV); - //})?; - - //self.regs().aux_mod().write(|w| { - // w.set_lm_ext(false); // Disable external Load Modulation - // w.set_lm_dri(true); // Enable internal Load Modulation - //})?; - - //self.regs().emd_sup_conf().write(|w| { - // w.set_rx_start_emv(true); - //})?; - - // AAT not in use - //self.regs().ant_tune_a().write_value(0x82)?; - //self.regs().ant_tune_b().write_value(0x82)?; - - // Adjust regulators - - // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. - self.regs().regulator_volt_control().write(|w| w.set_reg_s(true))?; - self.regs().regulator_volt_control().write(|w| w.set_reg_s(false))?; - - self.cmd_wait(Command::AdjustRegulators).await?; - - let res = self.regs().regulator_and_tim_disp().read()?.0; - trace!("reg result = {}", res); - - Ok(()) - } - - pub async fn mode_on(&mut self) -> Result<(), Error> { - self.mode = Mode::On; - self.enable_osc().await?; - - Ok(()) - } - - pub fn mode_off(&mut self) -> Result<(), Error> { - self.mode = Mode::Off; - self.cmd(Command::Stop)?; - // disable everything - self.regs().op_control().write(|_| {})?; - Ok(()) - } - - pub async fn measure_amplitude(&mut self) -> Result> { - self.cmd_wait(Command::MeasureAmplitude).await?; - self.regs().ad_conv_result().read() - } - - pub async fn measure_phase(&mut self) -> Result> { - self.cmd_wait(Command::MeasurePhase).await?; - self.regs().ad_conv_result().read() - } - - pub async fn measure_capacitance(&mut self) -> Result> { - self.cmd_wait(Command::MeasureCapacitance).await?; - self.regs().ad_conv_result().read() - } - - pub async fn calibrate_capacitance(&mut self) -> Result> { - self.regs().cap_sensor_control().write(|w| { - // Clear Manual calibration values to enable automatic calibration mode - w.set_cs_mcal(0); - w.set_cs_g(0b01); // 6.5v/pF, highest one - })?; - - // Don't use `cmd_wait`, the irq only fires in Ready mode (op_control.en = 1). - // Instead, wait for cap_sensor_result.cs_cal_end - self.cmd(Command::CalibrateCSensor)?; - - let deadline = Instant::now() + DEFAULT_TIMEOUT; - - let res = loop { - if Instant::now() > deadline { - return Err(Error::Timeout); - } - - let res = self.regs().cap_sensor_disp().read()?; - if res.cs_cal_err() { - panic!("Capacitive sensor calibration failed!"); - } - if res.cs_cal_end() { - break res; - } - - yield_now().await; - }; - Ok(res.cs_cal_val()) - } - - /// Change into wakeup mode, return immediately. - /// The IRQ pin will go high on wakeup. - pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { - self.mode_on().await?; - - self.mode = Mode::Wakeup; - debug!("Entering wakeup mode"); - - self.cmd(Command::Stop)?; - self.regs().op_control().write(|_| {})?; - self.regs().mode().write(|w| w.set_om(regs::ModeOm::INI_ISO14443A))?; - - let mut wtc = regs::WupTimerControl(0); - // let mut irqs = 0; - - wtc.set_wur(config.period as u8 & 0x10 == 0); - wtc.set_wut(config.period as u8 & 0x0F); - - if let Some(m) = config.inductive_amplitude { - let mut conf = regs::AmplitudeMeasureConf(0); - conf.set_am_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().amplitude_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_amplitude().await?; - self.regs().amplitude_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_amplitude().await?; - self.regs().amplitude_measure_ref().write_value(val)?; - conf.set_am_ae(true); - conf.set_am_aam(include_irq_measurement); - conf.set_am_aew(weight); - } - } - self.regs().amplitude_measure_conf().write_value(conf)?; - wtc.set_wam(true); - //irqs |= 1 << Interrupt::Wam as u32; - } - if let Some(m) = config.inductive_phase { - let mut conf = regs::PhaseMeasureConf(0); - conf.set_pm_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().phase_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_phase().await?; - self.regs().phase_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_phase().await?; - self.regs().phase_measure_ref().write_value(val)?; - conf.set_pm_ae(true); - conf.set_pm_aam(include_irq_measurement); - conf.set_pm_aew(weight); - } - } - self.regs().phase_measure_conf().write_value(conf)?; - wtc.set_wph(true); - // irqs |= 1 << Interrupt::Wph as u32; - } - if let Some(m) = config.capacitive { - debug!("capacitance calibrating..."); - let val = self.calibrate_capacitance().await?; - info!("capacitance calibrated: {}", val); - - let mut conf = regs::CapacitanceMeasureConf(0); - conf.set_cm_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().capacitance_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_capacitance().await?; - info!("Measured: {}", val); - self.regs().capacitance_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_capacitance().await?; - info!("Measured: {}", val); - self.regs().capacitance_measure_ref().write_value(val)?; - conf.set_cm_ae(true); - conf.set_cm_aam(include_irq_measurement); - conf.set_cm_aew(weight); - } - } - self.regs().capacitance_measure_conf().write_value(conf)?; - // wtc.set_wcap(true); // wto? - // irqs |= 1 << Interrupt::Wcap as u32; - } - - self.regs().wup_timer_control().write_value(wtc)?; - self.regs().op_control().write(|w| w.set_wu(true))?; - // self.irq_set_mask(!irqs)?; - - debug!("Entered wakeup mode, waiting for pin IRQ"); - self.irq.wait_for_high().await.unwrap(); - debug!("got pin IRQ!"); - - Ok(()) - } - - pub async fn field_on(&mut self) -> Result<(), FieldOnError> { - self.regs().mode().write(|w| { - w.set_om(regs::ModeOm::INI_ISO14443A); - })?; - // note: set automatically if command AnalogPreset is used - self.regs().aux().write(|w| { - w.set_tr_am(false); // use OOK - })?; - - // self.regs().aux_mod().write(|w| { - // w.set_lm_dri(true); // Enable internal Load Modulation - // w.set_dis_reg_am(false); // Enable regulator-based AM - // w.set_res_am(false); - // })?; - - // // Default over/under shoot protiection - // self.regs().overshoot_conf1().write_value(0x40.into())?; - // self.regs().overshoot_conf2().write_value(0x03.into())?; - // self.regs().undershoot_conf1().write_value(0x40.into())?; - // self.regs().undershoot_conf2().write_value(0x03.into())?; - - self.regs().aux().write(|w| { - // w.set_dis_corr(false); // Enable correlator reception - w.set_nfc_n(0); // todo this changes - })?; - /* - self.regs().rx_conf1().write_value(0x08.into())?; - self.regs().rx_conf2().write_value(0x2D.into())?; - self.regs().rx_conf3().write_value(0x00.into())?; - self.regs().rx_conf4().write_value(0x00.into())?; - self.regs().corr_conf1().write_value(0x51.into())?; - self.regs().corr_conf2().write_value(0x00.into())?; - */ - - self.regs().bit_rate().write(|w| { - w.set_rxrate(regs::BitRateE::_106); - w.set_txrate(regs::BitRateE::_106); - })?; - - // defaults - self.regs().iso14443a_nfc().write(|_| {})?; - - // Field ON - - // GT is done by software - // self.regs().field_on_gt().write_value(0)?; - - self.irq_clear()?; // clear - self.cmd(Command::InitialRfCollision)?; - - // loop { - // if self.irq(Interrupt::Cac) { - // return Err(FieldOnError::FieldCollision); - // } - // if self.irq(Interrupt::Apon) { - // break; - // } - - // self.irq_update()?; - // } - - self.regs().op_control().modify(|w| { - w.set_tx_en(true); - w.set_rx_en(true); - })?; - - Ok(()) - } - - async fn measure_vdd(&mut self) -> Result> { - self.regs().regulator_volt_control().write(|w| w.set_mpsv(0))?; - self.cmd_wait(Command::MeasureVdd).await?; - let res = self.regs().ad_conv_result().read()? as u32; - - // result is in units of 23.4mV - Ok((res * 234 + 5) / 10) - } - - // ======================= - // irq stuff - - // This chip offers 3 different registers to check for different IRQs - // Either an abstraction between chips would need to be build, or - #[inline] - pub fn irq(&mut self, irq: Interrupt) -> bool { - let r = self.regs().irq_main().read().expect("be readable"); - match irq { - Interrupt::Err => r.err(), - Interrupt::Tim => r.tim(), - Interrupt::Col => r.col(), - Interrupt::Txe => r.txe(), - Interrupt::Rxe => r.rxe(), - _ => todo!(), // TODO: ect huge match which doesn't make much sense? - } - } - - pub async fn irq_wait_timeout(&self, mut fn_to_call: F, timeout: Duration) -> Result<(), Error> - where - F: FnMut() -> bool, - { - match with_timeout( - timeout, - async { - while !fn_to_call() { - Timer::after_millis(5).await - } - embassy_futures::yield_now() - } - .await, - ) - .await - { - Ok(_) => Ok(()), - Err(_) => Err(Error::Timeout), - } - } - - pub async fn irq_wait(&self, fn_to_call: F) -> Result<(), Error> - where - F: Fn() -> bool, - { - self.irq_wait_timeout(fn_to_call, DEFAULT_TIMEOUT).await - } - - pub fn irq_update(&mut self) -> Result<(), Error> { - self.regs().irq_main().read()?; - Ok(()) - } - - #[inline] - fn irq_clear(&mut self) -> Result<(), Error> { - self.regs().irq_main().write(|v| v.0 = 0)?; - Ok(()) - } - - // pub fn raw(&mut self) -> Raw<'_, I, IrqPin> { - // Raw { inner: self } - // } } diff --git a/rnfc-st25r39/src/impls/lib_st25r3916.rs b/rnfc-st25r39/src/impls/lib_st25r3916.rs index aca8787..817947c 100644 --- a/rnfc-st25r39/src/impls/lib_st25r3916.rs +++ b/rnfc-st25r39/src/impls/lib_st25r3916.rs @@ -1,16 +1,3 @@ -use embassy_futures::yield_now; -use embassy_time::{Duration, Instant}; -use embedded_hal::digital::InputPin; -use embedded_hal_async::digital::Wait; - -// use crate::aat::AatConfig; -use crate::commands::Command; -use crate::interface::Interface; -use crate::regs::{self, Regs}; -use crate::{Error, Mode, St25r39}; -pub const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); -use crate::impls::*; - #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[allow(unused)] @@ -80,451 +67,3 @@ pub enum Interrupt { /// PPON2 Field on waiting Timer interrupt Ppon2 = 31, } - -impl St25r39 { - pub async fn new(iface: I, irq: IrqPin) -> Result> { - let mut this = Self { - iface, - irq, - irqs: 0, - mode: Mode::On, - }; - this.init().await?; - Ok(this) - } - - pub fn regs(&mut self) -> Regs { - Regs::new(&mut self.iface) - } - - pub fn cmd(&mut self, cmd: Command) -> Result<(), Error> { - self.iface.do_command(cmd as u8).map_err(Error::Interface) - } - - async fn cmd_wait(&mut self, cmd: Command) -> Result<(), Error> { - self.irq_clear()?; - self.cmd(cmd)?; - self.irq_wait(Interrupt::Dct).await - } - - async fn enable_osc(&mut self) -> Result<(), Error> { - trace!("Starting osc..."); - self.regs().op_control().write(|w| w.set_en(true))?; - while !self.regs().aux_display().read()?.osc_ok() {} - Ok(()) - } - - async fn init(&mut self) -> Result<(), Error> { - self.cmd(Command::SetDefault)?; - - self.regs().test_unk().write(|w| { - w.set_dis_overheat_prot(true); - })?; - - let id = self.regs().ic_identity().read()?; - trace!("ic_type = {:02x} ic_rev = {:02x}", id.ic_type().0, id.ic_rev().0); - - // Enable OSC - self.enable_osc().await?; - - // Measure vdd - trace!("measuring vdd..."); - let vdd_mv = self.measure_vdd().await?; - trace!("measure vdd result = {}mv", vdd_mv); - - let sup3v = vdd_mv < 3600; - if sup3v { - trace!("using 3v3 supply mode"); - } else { - trace!("using 5v supply mode"); - } - - self.regs().io_conf2().write(|w| { - w.set_sup_3v(sup3v); - })?; - - // Disable MCU_CLK - self.regs().io_conf1().write(|w| { - w.set_out_cl(regs::IoConf1OutCl::DISABLED); - w.set_lf_clk_off(true); - })?; - - // Enable minimum non-overlap - //self.regs().res_am_mod().write(|w| w.set_fa3_f(true))?; - - // Set ext field detect activ/deactiv thresholds - //self.regs().field_threshold_actv().write(|w| { - // w.set_trg(regs::FieldThresholdActvTrg::_105MV); - // w.set_rfe(regs::FieldThresholdActvRfe::_105MV); - //})?; - //self.regs().field_threshold_deactv().write(|w| { - // w.set_trg(regs::FieldThresholdDeactvTrg::_75MV); - // w.set_rfe(regs::FieldThresholdDeactvRfe::_75MV); - //})?; - - //self.regs().aux_mod().write(|w| { - // w.set_lm_ext(false); // Disable external Load Modulation - // w.set_lm_dri(true); // Enable internal Load Modulation - //})?; - - //self.regs().emd_sup_conf().write(|w| { - // w.set_rx_start_emv(true); - //})?; - - // AAT not in use - //self.regs().ant_tune_a().write_value(0x82)?; - //self.regs().ant_tune_b().write_value(0x82)?; - - self.regs().op_control().modify(|w| { - w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); - })?; - - // Adjust regulators - - // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. - self.regs().regulator_control().write(|w| w.set_reg_s(true))?; - self.regs().regulator_control().write(|w| w.set_reg_s(false))?; - - self.cmd_wait(Command::AdjustRegulators).await?; - - let res = self.regs().regulator_result().read()?.0; - trace!("reg result = {}", res); - - Ok(()) - } - - pub(crate) fn mode_off(&mut self) -> Result<(), Error> { - self.mode = Mode::Off; - self.cmd(Command::Stop)?; - // disable everything - self.regs().op_control().write(|_| {})?; - Ok(()) - } - - pub async fn measure_amplitude(&mut self) -> Result> { - self.cmd_wait(Command::MeasureAmplitude).await?; - self.regs().ad_result().read() - } - - pub async fn measure_phase(&mut self) -> Result> { - self.cmd_wait(Command::MeasurePhase).await?; - self.regs().ad_result().read() - } - - pub async fn measure_capacitance(&mut self) -> Result> { - self.cmd_wait(Command::MeasureCapacitance).await?; - self.regs().ad_result().read() - } - - pub async fn calibrate_capacitance(&mut self) -> Result> { - self.regs().cap_sensor_control().write(|w| { - // Clear Manual calibration values to enable automatic calibration mode - w.set_cs_mcal(0); - w.set_cs_g(0b01); // 6.5v/pF, highest one - })?; - - // Don't use `cmd_wait`, the irq only fires in Ready mode (op_control.en = 1). - // Instead, wait for cap_sensor_result.cs_cal_end - self.cmd(Command::CalibrateCSensor)?; - - let deadline = Instant::now() + DEFAULT_TIMEOUT; - - let res = loop { - if Instant::now() > deadline { - return Err(Error::Timeout); - } - - let res = self.regs().cap_sensor_result().read()?; - if res.cs_cal_err() { - panic!("Capacitive sensor calibration failed!"); - } - if res.cs_cal_end() { - break res; - } - - yield_now().await; - }; - Ok(res.cs_cal_val()) - } - - pub(crate) async fn mode_on(&mut self) -> Result<(), Error> { - self.mode = Mode::On; - self.enable_osc().await?; - - self.regs().op_control().modify(|w| { - w.set_en_fd(regs::OpControlEnFd::AUTO_EFD); - })?; - self.regs().tx_driver().write(|w| { - w.set_d_res(3); - })?; - Ok(()) - } - - /// Change into wakeup mode, return immediately. - /// The IRQ pin will go high on wakeup. - pub async fn wait_for_card(&mut self, config: WakeupConfig) -> Result<(), Error> { - self.mode_on().await?; - - self.mode = Mode::Wakeup; - debug!("Entering wakeup mode"); - - self.cmd(Command::Stop)?; - self.regs().op_control().write(|_| {})?; - self.regs().mode().write(|w| w.set_om(regs::ModeOm::INI_ISO14443A))?; - - let mut wtc = regs::WupTimerControl(0); - let mut irqs = 0; - - wtc.set_wur(config.period as u8 & 0x10 == 0); - wtc.set_wut(config.period as u8 & 0x0F); - - if let Some(m) = config.inductive_amplitude { - let mut conf = regs::AmplitudeMeasureConf(0); - conf.set_am_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().amplitude_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_amplitude().await?; - self.regs().amplitude_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_amplitude().await?; - self.regs().amplitude_measure_ref().write_value(val)?; - conf.set_am_ae(true); - conf.set_am_aam(include_irq_measurement); - conf.set_am_aew(weight); - } - } - self.regs().amplitude_measure_conf().write_value(conf)?; - wtc.set_wam(true); - irqs |= 1 << Interrupt::Wam as u32; - } - if let Some(m) = config.inductive_phase { - let mut conf = regs::PhaseMeasureConf(0); - conf.set_pm_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().phase_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_phase().await?; - self.regs().phase_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_phase().await?; - self.regs().phase_measure_ref().write_value(val)?; - conf.set_pm_ae(true); - conf.set_pm_aam(include_irq_measurement); - conf.set_pm_aew(weight); - } - } - self.regs().phase_measure_conf().write_value(conf)?; - wtc.set_wph(true); - irqs |= 1 << Interrupt::Wph as u32; - } - if let Some(m) = config.capacitive { - debug!("capacitance calibrating..."); - let val = self.calibrate_capacitance().await?; - info!("capacitance calibrated: {}", val); - - let mut conf = regs::CapacitanceMeasureConf(0); - conf.set_cm_d(m.delta); - match m.reference { - WakeupReference::Manual(val) => { - self.regs().capacitance_measure_ref().write_value(val)?; - } - WakeupReference::Automatic => { - let val = self.measure_capacitance().await?; - info!("Measured: {}", val); - self.regs().capacitance_measure_ref().write_value(val)?; - } - WakeupReference::AutoAverage { - include_irq_measurement, - weight, - } => { - let val = self.measure_capacitance().await?; - info!("Measured: {}", val); - self.regs().capacitance_measure_ref().write_value(val)?; - conf.set_cm_ae(true); - conf.set_cm_aam(include_irq_measurement); - conf.set_cm_aew(weight); - } - } - self.regs().capacitance_measure_conf().write_value(conf)?; - wtc.set_wcap(true); - irqs |= 1 << Interrupt::Wcap as u32; - } - - self.irq_clear()?; - - self.regs().wup_timer_control().write_value(wtc)?; - self.regs().op_control().write(|w| w.set_wu(true))?; - self.irq_set_mask(!irqs)?; - - debug!("Entered wakeup mode, waiting for pin IRQ"); - self.irq.wait_for_high().await.unwrap(); - debug!("got pin IRQ!"); - - Ok(()) - } - - pub async fn field_on(&mut self) -> Result<(), FieldOnError> { - self.regs().mode().write(|w| { - w.set_om(regs::ModeOm::INI_ISO14443A); - w.set_tr_am(false); // use OOK - })?; - self.regs().tx_driver().write(|w| { - w.set_am_mod(regs::TxDriverAmMod::_12PERCENT); - })?; - self.regs().aux_mod().write(|w| { - w.set_lm_dri(true); // Enable internal Load Modulation - w.set_dis_reg_am(false); // Enable regulator-based AM - w.set_res_am(false); - })?; - - // Default over/under shoot protiection - self.regs().overshoot_conf1().write_value(0x40.into())?; - self.regs().overshoot_conf2().write_value(0x03.into())?; - self.regs().undershoot_conf1().write_value(0x40.into())?; - self.regs().undershoot_conf2().write_value(0x03.into())?; - - self.regs().aux().write(|w| { - w.set_dis_corr(false); // Enable correlator reception - w.set_nfc_n(0); // todo this changes - })?; - /* - self.regs().rx_conf1().write_value(0x08.into())?; - self.regs().rx_conf2().write_value(0x2D.into())?; - self.regs().rx_conf3().write_value(0x00.into())?; - self.regs().rx_conf4().write_value(0x00.into())?; - self.regs().corr_conf1().write_value(0x51.into())?; - self.regs().corr_conf2().write_value(0x00.into())?; - */ - - self.regs().bit_rate().write(|w| { - w.set_rxrate(regs::BitRateE::_106); - w.set_txrate(regs::BitRateE::_106); - })?; - - // defaults - self.regs().iso14443a_nfc().write(|_| {})?; - - // Field ON - - // GT is done by software - self.regs().field_on_gt().write_value(0)?; - - self.irq_clear()?; // clear - self.cmd(Command::InitialRfCollision)?; - - loop { - if self.irq(Interrupt::Cac) { - return Err(FieldOnError::FieldCollision); - } - if self.irq(Interrupt::Apon) { - break; - } - - self.irq_update()?; - } - - self.regs().op_control().modify(|w| { - w.set_tx_en(true); - w.set_rx_en(true); - })?; - - Ok(()) - } - - async fn measure_vdd(&mut self) -> Result> { - self.regs() - .regulator_control() - .write(|w| w.set_mpsv(regs::RegulatorControlMpsv::VDD))?; - self.cmd_wait(Command::MeasureVdd).await?; - let res = self.regs().ad_result().read()? as u32; - - // result is in units of 23.4mV - Ok((res * 234 + 5) / 10) - } - - // ======================= - // irq stuff - - pub fn irq(&self, irq: Interrupt) -> bool { - return (self.irqs & (1 << (irq as u8))) != 0; - } - - pub async fn irq_wait_timeout(&mut self, irq: Interrupt, timeout: Duration) -> Result<(), Error> { - let deadline = Instant::now() + timeout; - self.irq_update()?; - while !self.irq(irq) { - if Instant::now() > deadline { - return Err(Error::Timeout); - } - yield_now().await; - self.irq_update()?; - } - Ok(()) - } - - pub async fn irq_wait(&mut self, irq: Interrupt) -> Result<(), Error> { - self.irq_wait_timeout(irq, DEFAULT_TIMEOUT).await - } - - pub fn irq_update(&mut self) -> Result<(), Error> { - for i in 0..4 { - self.irqs |= (self.regs().irq_main(i).read()? as u32) << (i * 8); - } - Ok(()) - } - - fn irq_clear(&mut self) -> Result<(), Error> { - self.irq_update()?; - self.irqs = 0; - Ok(()) - } - - fn irq_set_mask(&mut self, mask: u32) -> Result<(), Error> { - for i in 0..4 { - self.regs().irq_mask(i).write_value((mask >> (i * 8)) as u8)?; - } - Ok(()) - } - - pub fn raw(&mut self) -> Raw<'_, I, IrqPin> { - Raw { inner: self } - } -} - -pub struct Raw<'a, I: Interface, IrqPin: InputPin + Wait> { - inner: &'a mut St25r39, -} - -impl<'a, I: Interface, IrqPin: InputPin + Wait> Raw<'a, I, IrqPin> { - pub async fn field_on(&mut self) -> Result<(), FieldOnError> { - self.inner.mode_on().await?; - self.inner.field_on().await?; - Ok(()) - } - pub async fn field_off(&mut self) -> Result<(), Error> { - self.inner.mode_off()?; - Ok(()) - } - - pub async fn driver_hi_z(&mut self) -> Result<(), Error> { - self.inner.mode_off()?; - self.inner.regs().tx_driver().write(|w| { - w.set_d_res(15); // hi-z - })?; - - Ok(()) - } -} diff --git a/rnfc-st25r39/src/impls/mod.rs b/rnfc-st25r39/src/impls/mod.rs index 4324a13..1dcaca0 100644 --- a/rnfc-st25r39/src/impls/mod.rs +++ b/rnfc-st25r39/src/impls/mod.rs @@ -8,6 +8,8 @@ pub mod lib_st25r3911b; #[cfg(feature = "st25r3911b")] pub use lib_st25r3911b::*; +pub mod lib; + // TODO: check wup and other wake-up registers in st25r3911b #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/rnfc-st25r39/src/regs/mod.rs b/rnfc-st25r39/src/regs/mod.rs index 8ceac51..5ac8d7f 100644 --- a/rnfc-st25r39/src/regs/mod.rs +++ b/rnfc-st25r39/src/regs/mod.rs @@ -1,5 +1,5 @@ #[cfg(feature = "st25r3911b")] -mod regs_st25r3911b; +pub mod regs_st25r3911b; use core::marker::PhantomData; #[cfg(feature = "st25r3911b")] diff --git a/rnfc-st25r39/src/regs/regs_st25r3911b.rs b/rnfc-st25r39/src/regs/regs_st25r3911b.rs index 3a365ac..bd8e209 100644 --- a/rnfc-st25r39/src/regs/regs_st25r3911b.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3911b.rs @@ -132,7 +132,12 @@ impl<'a, I: Interface> Regs<'a, I> { pub fn gpt2(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 19) } - /// Main interrupt register + /// Main interrupt register mask, combined wth offset to other irq mask regs + pub fn irq_mask(&mut self, n: u8) -> Reg<'_, I, u8> { + assert!(n < 3); + Reg::new(self.iface, 20 + n) + } + /// Main interrupt register mask pub fn irq_mask_main(&mut self) -> Reg<'_, I, IrqMaskMain> { Reg::new(self.iface, 20) } @@ -145,9 +150,14 @@ impl<'a, I: Interface> Regs<'a, I> { Reg::new(self.iface, 22) } /// Main interrupt register - pub fn irq_main(&mut self) -> Reg<'_, I, IrqMain> { + pub fn irq_main_direct(&mut self) -> Reg<'_, I, IrqMain> { Reg::new(self.iface, 23) } + /// Main interrupt register, combined with offset to other regs + pub fn irq_main(&mut self, n: u8) -> Reg<'_, I, u8> { + assert!(n < 3); + Reg::new(self.iface, 23 + n) + } /// Mask timer and NFC interrupt register pub fn irq_timer_nfc(&mut self) -> Reg<'_, I, IrqTimerNfc> { Reg::new(self.iface, 24) @@ -181,7 +191,7 @@ impl<'a, I: Interface> Regs<'a, I> { Reg::new(self.iface, 31) } /// A/D converter output register - pub fn ad_conv_result(&mut self) -> Reg<'_, I, u8> { + pub fn ad_result(&mut self) -> Reg<'_, I, u8> { Reg::new(self.iface, 32) } /// Antenna calibration control register @@ -237,7 +247,7 @@ impl<'a, I: Interface> Regs<'a, I> { Reg::new(self.iface, 46) } /// Capacitive sensor display register - pub fn cap_sensor_disp(&mut self) -> Reg<'_, I, CapSensorDisp> { + pub fn cap_sensor_result(&mut self) -> Reg<'_, I, CapSensorDisp> { Reg::new(self.iface, 47) } /// Auxiliary display register From 6dd280823a10ada2fa692da7a7a3e0360d99cbf2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Tue, 1 Apr 2025 11:42:09 +0200 Subject: [PATCH 7/8] review: changes part 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Manually adjusted register names in generated regs file to match names other chip (thus avoiding feature gate) Merge 2 interrupts files back to one Signed-off-by: Krzysztof Królczyk --- rnfc-st25r39/src/aat.rs | 21 ++------ .../impls/{lib_st25r3916.rs => interrupts.rs} | 16 ++++++ rnfc-st25r39/src/impls/lib.rs | 12 ++--- rnfc-st25r39/src/impls/lib_st25r3911b.rs | 53 ------------------- rnfc-st25r39/src/impls/mod.rs | 12 +---- rnfc-st25r39/src/iso14443a.rs | 18 +------ rnfc-st25r39/src/regs/regs_st25r3911b.rs | 4 +- 7 files changed, 28 insertions(+), 108 deletions(-) rename rnfc-st25r39/src/impls/{lib_st25r3916.rs => interrupts.rs} (78%) delete mode 100644 rnfc-st25r39/src/impls/lib_st25r3911b.rs diff --git a/rnfc-st25r39/src/aat.rs b/rnfc-st25r39/src/aat.rs index ea2fa81..d468c09 100644 --- a/rnfc-st25r39/src/aat.rs +++ b/rnfc-st25r39/src/aat.rs @@ -55,28 +55,15 @@ impl St25r39 { b = new_b; } - #[cfg(feature = "st25r3916")] - self.regs().ant_tune_a().write_value(a)?; - #[cfg(feature = "st25r3916")] - self.regs().ant_tune_a().write_value(b)?; - - // st25r3911b chip might offer a better approach, simlar to what lib does - // self.regs().ant_tune_ctrl().write(|v| v.set_tre(1)) ect - // and whole procedure might need to be adjusted, - // to take "CalibrateAntenna" command into account, ant_tune_target ect - #[cfg(feature = "st25r3911b")] - self.regs().ant_tune_ctrl().write_value(a.into())?; - #[cfg(feature = "st25r3911b")] - self.regs().ant_tune_ctrl().write_value(b.into())?; + self.regs().ant_tune_a().write_value(a.into())?; + self.regs().ant_tune_a().write_value(b.into())?; Ok(()) } async fn aat_measure(&mut self, a: u8, b: u8, conf: &AatConfig) -> Result> { - #[cfg(feature = "st25r3916")] - self.regs().ant_tune_a().write_value(a)?; - #[cfg(feature = "st25r3916")] - self.regs().ant_tune_a().write_value(b)?; + self.regs().ant_tune_a().write_value(a.into())?; + self.regs().ant_tune_a().write_value(b.into())?; // Wait for caps to settle. Timer::after(Duration::from_millis(1)).await; diff --git a/rnfc-st25r39/src/impls/lib_st25r3916.rs b/rnfc-st25r39/src/impls/interrupts.rs similarity index 78% rename from rnfc-st25r39/src/impls/lib_st25r3916.rs rename to rnfc-st25r39/src/impls/interrupts.rs index 817947c..7d37aa5 100644 --- a/rnfc-st25r39/src/impls/lib_st25r3916.rs +++ b/rnfc-st25r39/src/impls/interrupts.rs @@ -2,8 +2,16 @@ #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[allow(unused)] pub enum Interrupt { + #[cfg(feature = "st25r3911b")] + /// IRQ due to error and wake-up timer + Err = 0, + #[cfg(feature = "st25r3916")] /// RFU interrupt Rfu = 0, + #[cfg(feature = "st25r3911b")] + /// IRQ due to timer or NFC event + Tim = 1, + #[cfg(feature = "st25r3916")] /// automatic reception restart interrupt RxRest = 1, /// bit collision interrupt @@ -50,20 +58,28 @@ pub enum Interrupt { Par = 22, /// CRC error interrupt Crc = 23, + #[cfg(feature = "st25r3916")] /// 106kb/s Passive target state interrupt: Active WuA = 24, + #[cfg(feature = "st25r3916")] /// 106kb/s Passive target state interrupt: Active* WuAX = 25, + #[cfg(feature = "st25r3916")] /// RFU2 interrupt Rfu2 = 26, + #[cfg(feature = "st25r3916")] /// 212/424b/s Passive target interrupt: Active WuF = 27, + #[cfg(feature = "st25r3916")] /// RXE with an automatic response interrupt RxePta = 28, + #[cfg(feature = "st25r3916")] /// Anticollision done and Field On interrupt Apon = 29, + #[cfg(feature = "st25r3916")] /// Passive target slot number water level interrupt SlWl = 30, + #[cfg(feature = "st25r3916")] /// PPON2 Field on waiting Timer interrupt Ppon2 = 31, } diff --git a/rnfc-st25r39/src/impls/lib.rs b/rnfc-st25r39/src/impls/lib.rs index af18fcc..103454c 100644 --- a/rnfc-st25r39/src/impls/lib.rs +++ b/rnfc-st25r39/src/impls/lib.rs @@ -3,13 +3,13 @@ use embassy_time::{Duration, Instant}; use embedded_hal::digital::InputPin; use embedded_hal_async::digital::Wait; -// use crate::aat::AatConfig; use crate::commands::Command; use crate::interface::Interface; use crate::regs::{self, Regs}; use crate::{Error, Mode, St25r39}; pub const DEFAULT_TIMEOUT: Duration = Duration::from_millis(500); -use crate::impls::*; +pub use crate::impls::interrupts::Interrupt; +pub use crate::impls::{FieldOnError, WakeupConfig, WakeupMethodConfig, WakeupReference}; impl St25r39 { pub async fn new(iface: I, irq: IrqPin) -> Result> { @@ -124,14 +124,8 @@ impl St25r39 { // Adjust regulators // Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. - #[cfg(feature = "st25r3916")] self.regs().regulator_control().write(|w| w.set_reg_s(true))?; - #[cfg(feature = "st25r3916")] self.regs().regulator_control().write(|w| w.set_reg_s(false))?; - #[cfg(feature = "st25r3911b")] - self.regs().regulator_volt_control().write(|w| w.set_reg_s(true))?; - #[cfg(feature = "st25r3911b")] - self.regs().regulator_volt_control().write(|w| w.set_reg_s(false))?; self.cmd_wait(Command::AdjustRegulators).await?; @@ -440,7 +434,7 @@ impl St25r39 { .regulator_control() .write(|w| w.set_mpsv(regs::RegulatorControlMpsv::VDD))?; #[cfg(feature = "st25r3911b")] - self.regs().regulator_volt_control().write(|w| w.set_mpsv(0))?; + self.regs().regulator_control().write(|w| w.set_mpsv(0))?; self.cmd_wait(Command::MeasureVdd).await?; let res = self.regs().ad_result().read()? as u32; diff --git a/rnfc-st25r39/src/impls/lib_st25r3911b.rs b/rnfc-st25r39/src/impls/lib_st25r3911b.rs deleted file mode 100644 index 4fd5250..0000000 --- a/rnfc-st25r39/src/impls/lib_st25r3911b.rs +++ /dev/null @@ -1,53 +0,0 @@ -#[derive(Debug, Clone, Copy, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[allow(unused)] -pub enum Interrupt { - /// IRQ due to error and wake-up timer - Err = 0, - /// IRQ due to timer or NFC event - Tim = 1, - /// bit collision interrupt - Col = 2, - /// end of transmission interrupt - Txe = 3, - /// end of receive interrupt - Rxe = 4, - /// start of receive interrupt - Rxs = 5, - /// FIFO water level interrupt - Fwl = 6, - /// oscillator stable interrupt - Osc = 7, - /// initiator bit rate recognised interrupt - Nfct = 8, - /// minimum guard time expired interrupt - Cat = 9, - /// collision during RF collision avoidance interrupt - Cac = 10, - /// external field off interrupt - Eof = 11, - /// external field on interrupt - Eon = 12, - /// general purpose timer expired interrupt - Gpe = 13, - /// no-response timer expired interrupt - Nre = 14, - /// termination of direct command interrupt - Dct = 15, - /// wake-up due to capacitance measurement - Wcap = 16, - /// wake-up due to phase interrupt - Wph = 17, - /// wake-up due to amplitude interrupt - Wam = 18, - /// wake-up interrupt - Wt = 19, - /// hard framing error interrupt - Err1 = 20, - /// soft framing error interrupt - Err2 = 21, - /// parity error interrupt - Par = 22, - /// CRC error interrupt - Crc = 23, -} diff --git a/rnfc-st25r39/src/impls/mod.rs b/rnfc-st25r39/src/impls/mod.rs index 1dcaca0..b1431f4 100644 --- a/rnfc-st25r39/src/impls/mod.rs +++ b/rnfc-st25r39/src/impls/mod.rs @@ -1,16 +1,6 @@ -#[cfg(feature = "st25r3916")] -pub mod lib_st25r3916; -#[cfg(feature = "st25r3916")] -pub use lib_st25r3916::*; - -#[cfg(feature = "st25r3911b")] -pub mod lib_st25r3911b; -#[cfg(feature = "st25r3911b")] -pub use lib_st25r3911b::*; - +pub mod interrupts; pub mod lib; -// TODO: check wup and other wake-up registers in st25r3911b #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum WakeupPeriod { diff --git a/rnfc-st25r39/src/iso14443a.rs b/rnfc-st25r39/src/iso14443a.rs index 6a6abbb..f6305eb 100644 --- a/rnfc-st25r39/src/iso14443a.rs +++ b/rnfc-st25r39/src/iso14443a.rs @@ -8,7 +8,8 @@ use rnfc_traits::iso14443a_ll as ll; use crate::commands::Command; use crate::fmt::Bytes; -use crate::impls::{FieldOnError, Interrupt}; +use crate::impls::interrupts::Interrupt; +use crate::impls::FieldOnError; use crate::interface::Interface; use crate::St25r39; @@ -158,29 +159,14 @@ impl<'d, I: Interface + 'd, IrqPin: InputPin + Wait + 'd> ll::Reader for Iso1444 this.cmd(cmd)?; // Wait for tx ended - #[cfg(feature = "st25r3916")] this.irq_wait(Interrupt::Txe).await?; - // #[cfg(feature = "st25r3911b")] - // this.irq_wait(|| this.regs().irq_main().read().expect("be readable").txe()).await?; // Wait for RX started - #[cfg(feature = "st25r3916")] this.irq_wait_timeout(Interrupt::Rxs, Duration::from_millis(fwt_ms as _)) .await?; - // #[cfg(feature = "st25r3911b")] - // this.irq_wait_timeout( - // || this.regs().irq_main().read().expect("be readable").rxs(), - // Duration::from_millis(fwt_ms as _)); - #[cfg(not(feature = "st25r3916"))] - let _ = fwt_ms; - #[cfg(feature = "st25r3916")] this.irq_wait_timeout(Interrupt::Rxs, Duration::from_millis(fwt_ms as _)) .await?; - // #[cfg(feature = "st25r3911b")] - // with_timeout(Duration::from_millis(fwt_ms as _), - // async { this.regs().irq_main().read().expect("read reg ok").txe() } - // ); // Wait for rx ended or error // The timeout should never hit, it's just for safety. diff --git a/rnfc-st25r39/src/regs/regs_st25r3911b.rs b/rnfc-st25r39/src/regs/regs_st25r3911b.rs index bd8e209..7998055 100644 --- a/rnfc-st25r39/src/regs/regs_st25r3911b.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3911b.rs @@ -195,7 +195,7 @@ impl<'a, I: Interface> Regs<'a, I> { Reg::new(self.iface, 32) } /// Antenna calibration control register - pub fn ant_tune_ctrl(&mut self) -> Reg<'_, I, AntTuneCtrl> { + pub fn ant_tune_a(&mut self) -> Reg<'_, I, AntTuneCtrl> { Reg::new(self.iface, 33) } /// Antenna calibration target register @@ -227,7 +227,7 @@ impl<'a, I: Interface> Regs<'a, I> { Reg::new(self.iface, 41) } /// Regulator voltage control register - pub fn regulator_volt_control(&mut self) -> Reg<'_, I, RegulatorVoltControl> { + pub fn regulator_control(&mut self) -> Reg<'_, I, RegulatorVoltControl> { Reg::new(self.iface, 42) } /// Regulator and timer display register From 325d104280d217a23324c280df79c311d4b27690 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Kr=C3=B3lczyk?= Date: Sun, 13 Apr 2025 21:52:46 +0200 Subject: [PATCH 8/8] fix: irq max regs offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Królczyk --- rnfc-st25r39/src/impls/lib.rs | 2 +- rnfc-st25r39/src/regs/regs_st25r3911b.rs | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/rnfc-st25r39/src/impls/lib.rs b/rnfc-st25r39/src/impls/lib.rs index 103454c..e0cc7c7 100644 --- a/rnfc-st25r39/src/impls/lib.rs +++ b/rnfc-st25r39/src/impls/lib.rs @@ -469,7 +469,7 @@ impl St25r39 { pub fn irq_update(&mut self) -> Result<(), Error> { #[cfg(feature = "st25r3911b")] - const REGS_CNT: u8 = 3; + const REGS_CNT: u8 = 5; #[cfg(feature = "st25r3916")] const REGS_CNT: u8 = 4; for i in 0..REGS_CNT { diff --git a/rnfc-st25r39/src/regs/regs_st25r3911b.rs b/rnfc-st25r39/src/regs/regs_st25r3911b.rs index 7998055..3510852 100644 --- a/rnfc-st25r39/src/regs/regs_st25r3911b.rs +++ b/rnfc-st25r39/src/regs/regs_st25r3911b.rs @@ -134,7 +134,7 @@ impl<'a, I: Interface> Regs<'a, I> { } /// Main interrupt register mask, combined wth offset to other irq mask regs pub fn irq_mask(&mut self, n: u8) -> Reg<'_, I, u8> { - assert!(n < 3); + assert!(n < 5); Reg::new(self.iface, 20 + n) } /// Main interrupt register mask @@ -155,7 +155,7 @@ impl<'a, I: Interface> Regs<'a, I> { } /// Main interrupt register, combined with offset to other regs pub fn irq_main(&mut self, n: u8) -> Reg<'_, I, u8> { - assert!(n < 3); + assert!(n < 5); Reg::new(self.iface, 23 + n) } /// Mask timer and NFC interrupt register