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LLVM 18 no longer emits atomic load/store machine code for targets without s32c1i
LLVM 18 no longer emits atomic load/store machine code for targets without s32c1i (LLVM-408)
Oct 25, 2024
Checklist
How often does this bug occurs?
often
Expected behavior
Atomic load/stores to function on the esp32s2
Actual behavior (suspected bug)
We sometimes get linker errors on the s2: https://github.com/esp-rs/esp-hal/actions/runs/11518396724/job/32065069522, in the Rust target we set max atomic width to 32, but in here it gets set to 0:
llvm-project/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Lines 440 to 445 in 256abfe
This heavily relates to LLVM-175 and we should now take the time to implement it and follow what the RISCV backend does:
llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Lines 631 to 638 in 256abfe
Error logs or terminal output
No response
Steps to reproduce the behavior
cargo xtask run-example examples esp32s2 embassy_usb_serial
in the rootProject release version
latest 18 release branch
System architecture
Intel/AMD 64-bit (modern PC, older Mac)
Operating system
Linux
Operating system version
Gentoo
Shell
ZSH
Additional context
No response
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