fixup! RISC-V: Add instruction patterns for 32-bit multiply-add and bit-extraxt fusion.

luismgsilva · luismgsilva · commit 10f17dd2a2d1 · 2025-12-16T14:02:34.000Z
Signed-off-by: Luis Silva &lt;luiss@synopsys.com&gt;
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
@@ -4612,7 +4612,8 @@
      if (REGNO (operands[0]) == REGNO (operands[3]))
        {
 	emit_insn (gen_mulsi3 (operands[4], operands[1], operands[2]));
-	emit_insn (gen_addsi3 (operands[0], operands[3], operands[4]));
+	emit_insn (gen_addsi3 (operands[4], operands[3], operands[4]));
+	emit_move_insn (operands[0], operands[4]);
        }
      else
        {

Original file line number	Diff line number	Diff line change
`@@ -4612,7 +4612,8 @@`
`4612`	`4612`	`if (REGNO (operands[0]) == REGNO (operands[3]))`
`4613`	`4613`	`{`
`4614`	`4614`	`emit_insn (gen_mulsi3 (operands[4], operands[1], operands[2]));`
`4615`		`- emit_insn (gen_addsi3 (operands[0], operands[3], operands[4]));`
	`4615`	`+ emit_insn (gen_addsi3 (operands[4], operands[3], operands[4]));`
	`4616`	`+ emit_move_insn (operands[0], operands[4]);`
`4616`	`4617`	`}`
`4617`	`4618`	`else`
`4618`	`4619`	`{`