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luismgsilvaluismgsilva
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arcv: Fix ARCVvdsp vnsra_{s,2s} intrinsics to accept LMUL=1 first argument.
The vnsra_s and vnsra_2s intrinsics were incorrectly defined with wider LMUL vector types (m2/m4) for their first input argument. According to their semantics, these narrowing operations should accept LMUL=1 vectors matching the narrow result type. This patch corrects the operand types by: - Updating patterns in arcv-vector.md to use <V_LMUL1> for operand 3. - Adding new argument type descriptors (vvwv, vvwx, vvqv, vvqx) in riscv-vector-builtins.cc to properly represent LMUL=1 inputs. - Updating builtin function definitions in arcv-vector-builtins-functions.def. - Correcting all affected test cases. This change creates overload conflicts because multiple intrinsics now share identical argument lists while differing only in return types. Since RVV overload resolution ignores return types, overload support for has been disabled. Signed-off-by: Luis Silva <[email protected]>
1 parent fb6c48d commit ef2d980

16 files changed

+124
-76
lines changed

‎gcc/config/riscv/arcv-vector-builtins-functions.def‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -47,14 +47,14 @@ DEF_RVV_FUNCTION (arcv_vnsra, narrow_quad_alu, none_m_preds, i_narrow_signed_shi
4747
DEF_RVV_FUNCTION (arcv_vnsra, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vwx_ops)
4848
DEF_RVV_FUNCTION (arcv_vnsra, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vqv_ops)
4949
DEF_RVV_FUNCTION (arcv_vnsra, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vqx_ops)
50-
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vwv_ops)
51-
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vwx_ops)
52-
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vqv_ops)
53-
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vqx_ops)
54-
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vwv_ops)
55-
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vwx_ops)
56-
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vqv_ops)
57-
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vqx_ops)
50+
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvwv_ops)
51+
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvwx_ops)
52+
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvqv_ops)
53+
DEF_RVV_FUNCTION (arcv_vnsra_s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvqx_ops)
54+
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvwv_ops)
55+
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvwx_ops)
56+
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvqv_ops)
57+
DEF_RVV_FUNCTION (arcv_vnsra_2s, narrow_quad_alu, none_m_preds, i_narrow_signed_shift_vvqx_ops)
5858
DEF_RVV_FUNCTION (arcv_vwsra, widen_alu, none_m_preds, i_signed_shift_wvv_ops)
5959
DEF_RVV_FUNCTION (arcv_vwsra, widen_alu, none_m_preds, i_signed_shift_wvx_ops)
6060
DEF_RVV_FUNCTION (arcv_vaddsub, alu, none_m_preds, iu_vvv_ops)

‎gcc/config/riscv/arcv-vector.md‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -563,7 +563,7 @@
563563
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
564564
(truncate:<V_DOUBLE_TRUNC>
565565
(unspec:VWEXTI
566-
[(match_operand:VWEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
566+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
567567
(sign_extend:VWEXTI
568568
(match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk"))]
569569
UNSPEC_ARCV_VNSRA_S))
@@ -588,7 +588,7 @@
588588
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
589589
(truncate:<V_QUAD_TRUNC>
590590
(unspec:VQEXTI
591-
[(match_operand:VQEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
591+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
592592
(sign_extend:VQEXTI
593593
(match_operand:<V_QUAD_TRUNC> 4 "vector_shift_operand" "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk"))]
594594
UNSPEC_ARCV_VNSRA_S))
@@ -613,7 +613,7 @@
613613
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
614614
(truncate:<V_DOUBLE_TRUNC>
615615
(unspec:VWEXTI
616-
[(match_operand:VWEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
616+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
617617
(match_operand:SI 4 "reg_or_int_operand" "r,r,r,r,r,r,i,i,i,i,i,i")]
618618
UNSPEC_ARCV_VNSRA_S))
619619
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
@@ -637,7 +637,7 @@
637637
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
638638
(truncate:<V_QUAD_TRUNC>
639639
(unspec:VQEXTI
640-
[(match_operand:VQEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
640+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
641641
(match_operand:SI 4 "reg_or_int_operand" "r,r,r,r,r,r,i,i,i,i,i,i")]
642642
UNSPEC_ARCV_VNSRA_S))
643643
(match_operand:<V_QUAD_TRUNC> 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
@@ -661,7 +661,7 @@
661661
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
662662
(truncate:<V_DOUBLE_TRUNC>
663663
(unspec:VWEXTI
664-
[(match_operand:VWEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
664+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
665665
(sign_extend:VWEXTI
666666
(match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk"))]
667667
UNSPEC_ARCV_VNSRA_2S))
@@ -686,7 +686,7 @@
686686
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
687687
(truncate:<V_QUAD_TRUNC>
688688
(unspec:VQEXTI
689-
[(match_operand:VQEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
689+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
690690
(sign_extend:VQEXTI
691691
(match_operand:<V_QUAD_TRUNC> 4 "vector_shift_operand" "0,0,0,0,vr,vr,vr,vr,vk,vk,vk,vk"))]
692692
UNSPEC_ARCV_VNSRA_2S))
@@ -711,7 +711,7 @@
711711
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
712712
(truncate:<V_DOUBLE_TRUNC>
713713
(unspec:VWEXTI
714-
[(match_operand:VWEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
714+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
715715
(match_operand:SI 4 "reg_or_int_operand" "r,r,r,r,r,r,i,i,i,i,i,i")]
716716
UNSPEC_ARCV_VNSRA_2S))
717717
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
@@ -735,7 +735,7 @@
735735
(reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
736736
(truncate:<V_QUAD_TRUNC>
737737
(unspec:VQEXTI
738-
[(match_operand:VQEXTI 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
738+
[(match_operand:<V_LMUL1> 3 "register_operand" "vr,vr,vr,vr,0,0,vr,vr,0,0,vr,vr")
739739
(match_operand:SI 4 "reg_or_int_operand" "r,r,r,r,r,r,i,i,i,i,i,i")]
740740
UNSPEC_ARCV_VNSRA_2S))
741741
(match_operand:<V_QUAD_TRUNC> 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]

‎gcc/config/riscv/riscv-vector-builtins-shapes.cc‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -616,6 +616,14 @@ struct narrow_quad_alu_def : public build_base
616616
char *get_name (function_builder &b, const function_instance &instance,
617617
bool overloaded_p) const override
618618
{
619+
/* Overloading disabled due to function type conflicts with
620+
vnsra_{2,}s variants. The overload resolver only compares
621+
argument types (ignoring return types), which causes multiple
622+
intrinsics generated from the same instruction to conflict
623+
when their argument lists are identical. */
624+
if (overloaded_p)
625+
return nullptr;
626+
619627
b.append_base_name (instance.base_name);
620628

621629
/* vop --> vop_<op>. */

‎gcc/config/riscv/riscv-vector-builtins.cc‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1130,6 +1130,10 @@ static CONSTEXPR const rvv_arg_type_info signed_shift_qx_args[]
11301130
= { rvv_arg_type_info (RVV_BASE_vector),
11311131
rvv_arg_type_info (RVV_BASE_integer),
11321132
rvv_arg_type_info_end};
1133+
static CONSTEXPR const rvv_arg_type_info signed_shift_qqx_args[]
1134+
= { rvv_arg_type_info (RVV_BASE_lmul1_vector),
1135+
rvv_arg_type_info (RVV_BASE_integer),
1136+
rvv_arg_type_info_end};
11331137
static CONSTEXPR const rvv_arg_type_info surqqvv_args[]
11341138
= { rvv_arg_type_info (RVV_BASE_quad_widen_lmul1_vector),
11351139
rvv_arg_type_info (RVV_BASE_vector),
@@ -1148,6 +1152,10 @@ static CONSTEXPR const rvv_arg_type_info signed_shift_wx_args[]
11481152
= { rvv_arg_type_info (RVV_BASE_vector),
11491153
rvv_arg_type_info (RVV_BASE_integer),
11501154
rvv_arg_type_info_end};
1155+
static CONSTEXPR const rvv_arg_type_info signed_shift_wwx_args[]
1156+
= { rvv_arg_type_info (RVV_BASE_lmul1_vector),
1157+
rvv_arg_type_info (RVV_BASE_integer),
1158+
rvv_arg_type_info_end};
11511159
static CONSTEXPR const rvv_arg_type_info whx_args[]
11521160
= { rvv_arg_type_info (RVV_BASE_quad_trunc_vector),
11531161
rvv_arg_type_info (RVV_BASE_double_trunc_scalar),
@@ -1171,10 +1179,18 @@ static CONSTEXPR const rvv_arg_type_info signed_shift_wv_args[]
11711179
= { rvv_arg_type_info (RVV_BASE_vector),
11721180
rvv_arg_type_info (RVV_BASE_double_trunc_vector),
11731181
rvv_arg_type_info_end};
1182+
static CONSTEXPR const rvv_arg_type_info signed_shift_wwv_args[]
1183+
= { rvv_arg_type_info (RVV_BASE_lmul1_vector),
1184+
rvv_arg_type_info (RVV_BASE_double_trunc_vector),
1185+
rvv_arg_type_info_end};
11741186
static CONSTEXPR const rvv_arg_type_info signed_shift_qv_args[]
11751187
= { rvv_arg_type_info (RVV_BASE_vector),
11761188
rvv_arg_type_info (RVV_BASE_quad_trunc_vector),
11771189
rvv_arg_type_info_end};
1190+
static CONSTEXPR const rvv_arg_type_info signed_shift_qqv_args[]
1191+
= { rvv_arg_type_info (RVV_BASE_lmul1_vector),
1192+
rvv_arg_type_info (RVV_BASE_quad_trunc_vector),
1193+
rvv_arg_type_info_end};
11781194
static CONSTEXPR const rvv_arg_type_info qqvv_args_prime[]
11791195
= { rvv_arg_type_info (RVV_BASE_vector),
11801196
rvv_arg_type_info (RVV_BASE_quad_trunc_vector),
@@ -3192,6 +3208,12 @@ static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vqv_ops
31923208
rvv_arg_type_info (RVV_BASE_quad_trunc_vector), /* Return type */
31933209
signed_shift_qv_args /* Args */};
31943210

3211+
static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vvqv_ops
3212+
= {qexti_ops, /* Types */
3213+
OP_TYPE_qv, /* Suffix */
3214+
rvv_arg_type_info (RVV_BASE_quad_trunc_vector), /* Return type */
3215+
signed_shift_qqv_args /* Args */};
3216+
31953217
static CONSTEXPR const rvv_op_info i_signed_shift_wvv_ops
31963218
= {wexti_ops, /* Types */
31973219
OP_TYPE_vv, /* Suffix */
@@ -3228,6 +3250,12 @@ static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vwv_ops
32283250
rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */
32293251
signed_shift_wv_args /* Args */};
32303252

3253+
static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vvwv_ops
3254+
= {wexti_ops, /* Types */
3255+
OP_TYPE_wv, /* Suffix */
3256+
rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */
3257+
signed_shift_wwv_args /* Args */};
3258+
32313259
static CONSTEXPR const rvv_op_info iu_vv_ops
32323260
= {iu_ops, /* Types */
32333261
OP_TYPE_v, /* Suffix */
@@ -3240,6 +3268,12 @@ static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vwx_ops
32403268
rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */
32413269
signed_shift_wx_args /* Args */};
32423270

3271+
static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vvwx_ops
3272+
= {wexti_ops, /* Types */
3273+
OP_TYPE_wx, /* Suffix */
3274+
rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */
3275+
signed_shift_wwx_args /* Args */};
3276+
32433277
static CONSTEXPR const rvv_op_info wi_vv_ops
32443278
= {wi_ops, /* Types */
32453279
OP_TYPE_vv, /* Suffix */
@@ -3318,6 +3352,12 @@ static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vqx_ops
33183352
rvv_arg_type_info (RVV_BASE_quad_trunc_vector), /* Return type */
33193353
signed_shift_qx_args /* Args */};
33203354

3355+
static CONSTEXPR const rvv_op_info i_narrow_signed_shift_vvqx_ops
3356+
= {qexti_ops, /* Types */
3357+
OP_TYPE_qx, /* Suffix */
3358+
rvv_arg_type_info (RVV_BASE_quad_trunc_vector), /* Return type */
3359+
signed_shift_qqx_args /* Args */};
3360+
33213361
static CONSTEXPR const rvv_op_info i_qqvv_ops_prime
33223362
= {qexti_ops, /* Types */
33233363
OP_TYPE_vv, /* Suffix */

‎gcc/testsuite/gcc.target/riscv/arcv-vdsp-vnsra_2s_qi-compile-1.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
** ret
1616
*/
1717
vint8m1_t
18-
test_vnsra_2s_qi_i8 (vint32m4_t vs2, vint8m1_t vs1, size_t vl)
18+
test_vnsra_2s_qi_i8 (vint32m1_t vs2, vint8m1_t vs1, size_t vl)
1919
{
2020
return __riscv_arcv_vnsra_2s_qx_i8m1 (vs2, 1, 0, vl);
2121
}
@@ -28,7 +28,7 @@ test_vnsra_2s_qi_i8 (vint32m4_t vs2, vint8m1_t vs1, size_t vl)
2828
** ret
2929
*/
3030
vint8m1_t
31-
test_vnsra_2s_qi_i8_m (vbool8_t mask, vint32m4_t vs2, vint8m1_t vs1, size_t vl)
31+
test_vnsra_2s_qi_i8_m (vbool8_t mask, vint32m1_t vs2, vint8m1_t vs1, size_t vl)
3232
{
3333
return __riscv_arcv_vnsra_2s_qx_i8m1_m (mask, vs2, 1, 0, vl);
3434
}
@@ -41,7 +41,7 @@ test_vnsra_2s_qi_i8_m (vbool8_t mask, vint32m4_t vs2, vint8m1_t vs1, size_t vl)
4141
** ret
4242
*/
4343
vint16m1_t
44-
test_vnsra_2s_qi_i16 (vint64m4_t vs2, vint16m1_t vs1, size_t vl)
44+
test_vnsra_2s_qi_i16 (vint64m1_t vs2, vint16m1_t vs1, size_t vl)
4545
{
4646
return __riscv_arcv_vnsra_2s_qx_i16m1 (vs2, 1, 0, vl);
4747
}
@@ -54,7 +54,7 @@ test_vnsra_2s_qi_i16 (vint64m4_t vs2, vint16m1_t vs1, size_t vl)
5454
** ret
5555
*/
5656
vint16m1_t
57-
test_vnsra_2s_qi_i16_m (vbool16_t mask, vint64m4_t vs2, vint16m1_t vs1, size_t vl)
57+
test_vnsra_2s_qi_i16_m (vbool16_t mask, vint64m1_t vs2, vint16m1_t vs1, size_t vl)
5858
{
5959
return __riscv_arcv_vnsra_2s_qx_i16m1_m (mask, vs2, 1, 0, vl);
6060
}

‎gcc/testsuite/gcc.target/riscv/arcv-vdsp-vnsra_2s_qv-compile-1.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
** ret
1616
*/
1717
vint8m1_t
18-
test_vnsra_2s_qv_i8 (vint32m4_t vs2, vint8m1_t vs1, size_t vl)
18+
test_vnsra_2s_qv_i8 (vint32m1_t vs2, vint8m1_t vs1, size_t vl)
1919
{
2020
return __riscv_arcv_vnsra_2s_qv_i8m1 (vs2, vs1, 0, vl);
2121
}
@@ -28,7 +28,7 @@ test_vnsra_2s_qv_i8 (vint32m4_t vs2, vint8m1_t vs1, size_t vl)
2828
** ret
2929
*/
3030
vint8m1_t
31-
test_vnsra_2s_qv_i8_m (vbool8_t mask, vint32m4_t vs2, vint8m1_t vs1, size_t vl)
31+
test_vnsra_2s_qv_i8_m (vbool8_t mask, vint32m1_t vs2, vint8m1_t vs1, size_t vl)
3232
{
3333
return __riscv_arcv_vnsra_2s_qv_i8m1_m (mask, vs2, vs1, 0, vl);
3434
}
@@ -41,7 +41,7 @@ test_vnsra_2s_qv_i8_m (vbool8_t mask, vint32m4_t vs2, vint8m1_t vs1, size_t vl)
4141
** ret
4242
*/
4343
vint16m1_t
44-
test_vnsra_2s_qv_i16 (vint64m4_t vs2, vint16m1_t vs1, size_t vl)
44+
test_vnsra_2s_qv_i16 (vint64m1_t vs2, vint16m1_t vs1, size_t vl)
4545
{
4646
return __riscv_arcv_vnsra_2s_qv_i16m1 (vs2, vs1, 0, vl);
4747
}
@@ -54,7 +54,7 @@ test_vnsra_2s_qv_i16 (vint64m4_t vs2, vint16m1_t vs1, size_t vl)
5454
** ret
5555
*/
5656
vint16m1_t
57-
test_vnsra_2s_qv_i16_m (vbool16_t mask, vint64m4_t vs2, vint16m1_t vs1, size_t vl)
57+
test_vnsra_2s_qv_i16_m (vbool16_t mask, vint64m1_t vs2, vint16m1_t vs1, size_t vl)
5858
{
5959
return __riscv_arcv_vnsra_2s_qv_i16m1_m (mask, vs2, vs1, 0, vl);
6060
}

‎gcc/testsuite/gcc.target/riscv/arcv-vdsp-vnsra_2s_qx-compile-1.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
** ret
1717
*/
1818
vint8m1_t
19-
test_vnsra_2s_qx_i8 (vint32m4_t vs2, int vs1, size_t vl)
19+
test_vnsra_2s_qx_i8 (vint32m1_t vs2, int vs1, size_t vl)
2020
{
2121
return __riscv_arcv_vnsra_2s_qx_i8m1 (vs2, vs1, 0, vl);
2222
}
@@ -29,7 +29,7 @@ test_vnsra_2s_qx_i8 (vint32m4_t vs2, int vs1, size_t vl)
2929
** ret
3030
*/
3131
vint8m1_t
32-
test_vnsra_2s_qx_i8_m (vbool8_t mask, vint32m4_t vs2, int vs1, size_t vl)
32+
test_vnsra_2s_qx_i8_m (vbool8_t mask, vint32m1_t vs2, int vs1, size_t vl)
3333
{
3434
return __riscv_arcv_vnsra_2s_qx_i8m1_m (mask, vs2, vs1, 0, vl);
3535
}
@@ -42,7 +42,7 @@ test_vnsra_2s_qx_i8_m (vbool8_t mask, vint32m4_t vs2, int vs1, size_t vl)
4242
** ret
4343
*/
4444
vint16m1_t
45-
test_vnsra_2s_qx_i16 (vint64m4_t vs2, int vs1, size_t vl)
45+
test_vnsra_2s_qx_i16 (vint64m1_t vs2, int vs1, size_t vl)
4646
{
4747
return __riscv_arcv_vnsra_2s_qx_i16m1 (vs2, vs1, 0, vl);
4848
}
@@ -55,7 +55,7 @@ test_vnsra_2s_qx_i16 (vint64m4_t vs2, int vs1, size_t vl)
5555
** ret
5656
*/
5757
vint16m1_t
58-
test_vnsra_2s_qx_i16_m (vbool16_t mask, vint64m4_t vs2, int vs1, size_t vl)
58+
test_vnsra_2s_qx_i16_m (vbool16_t mask, vint64m1_t vs2, int vs1, size_t vl)
5959
{
6060
return __riscv_arcv_vnsra_2s_qx_i16m1_m (mask, vs2, vs1, 0, vl);
6161
}

‎gcc/testsuite/gcc.target/riscv/arcv-vdsp-vnsra_2s_wi-compile-1.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
** ret
1717
*/
1818
vint8m1_t
19-
test_vnsra_2s_wi_i8 (vint16m2_t vs2, vint8m1_t vs1, size_t vl)
19+
test_vnsra_2s_wi_i8 (vint16m1_t vs2, vint8m1_t vs1, size_t vl)
2020
{
2121
return __riscv_arcv_vnsra_2s_wx_i8m1 (vs2, 1, 0, vl);
2222
}
@@ -29,7 +29,7 @@ test_vnsra_2s_wi_i8 (vint16m2_t vs2, vint8m1_t vs1, size_t vl)
2929
** ret
3030
*/
3131
vint8m1_t
32-
test_vnsra_2s_wi_i8_m (vbool8_t mask, vint16m2_t vs2, vint8m1_t vs1, size_t vl)
32+
test_vnsra_2s_wi_i8_m (vbool8_t mask, vint16m1_t vs2, vint8m1_t vs1, size_t vl)
3333
{
3434
return __riscv_arcv_vnsra_2s_wx_i8m1_m (mask, vs2, 1, 0, vl);
3535
}
@@ -42,7 +42,7 @@ test_vnsra_2s_wi_i8_m (vbool8_t mask, vint16m2_t vs2, vint8m1_t vs1, size_t vl)
4242
** ret
4343
*/
4444
vint16m1_t
45-
test_vnsra_2s_wi_i16 (vint32m2_t vs2, vint16m1_t vs1, size_t vl)
45+
test_vnsra_2s_wi_i16 (vint32m1_t vs2, vint16m1_t vs1, size_t vl)
4646
{
4747
return __riscv_arcv_vnsra_2s_wx_i16m1 (vs2, 1, 0, vl);
4848
}
@@ -55,7 +55,7 @@ test_vnsra_2s_wi_i16 (vint32m2_t vs2, vint16m1_t vs1, size_t vl)
5555
** ret
5656
*/
5757
vint16m1_t
58-
test_vnsra_2s_wi_i16_m (vbool16_t mask, vint32m2_t vs2, vint16m1_t vs1, size_t vl)
58+
test_vnsra_2s_wi_i16_m (vbool16_t mask, vint32m1_t vs2, vint16m1_t vs1, size_t vl)
5959
{
6060
return __riscv_arcv_vnsra_2s_wx_i16m1_m (mask, vs2, 1, 0, vl);
6161
}
@@ -68,7 +68,7 @@ test_vnsra_2s_wi_i16_m (vbool16_t mask, vint32m2_t vs2, vint16m1_t vs1, size_t v
6868
** ret
6969
*/
7070
vint32m1_t
71-
test_vnsra_2s_wi_i32 (vint64m2_t vs2, vint32m1_t vs1, size_t vl)
71+
test_vnsra_2s_wi_i32 (vint64m1_t vs2, vint32m1_t vs1, size_t vl)
7272
{
7373
return __riscv_arcv_vnsra_2s_wx_i32m1 (vs2, 1, 0, vl);
7474
}
@@ -81,7 +81,7 @@ test_vnsra_2s_wi_i32 (vint64m2_t vs2, vint32m1_t vs1, size_t vl)
8181
** ret
8282
*/
8383
vint32m1_t
84-
test_vnsra_2s_wi_i32_m (vbool32_t mask, vint64m2_t vs2, vint32m1_t vs1, size_t vl)
84+
test_vnsra_2s_wi_i32_m (vbool32_t mask, vint64m1_t vs2, vint32m1_t vs1, size_t vl)
8585
{
8686
return __riscv_arcv_vnsra_2s_wx_i32m1_m (mask, vs2, 1, 0, vl);
8787
}

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