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Siyuan Cheng
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DSP: add DSP support for ARC processor
add DSP reg in context switch add AGU reg in context switch to support XY mem add thread option and API to dis/enable DSP switch Signed-off-by: Siyuan Cheng <[email protected]>
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11 files changed

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11 files changed

+663
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‎arch/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -564,6 +564,11 @@ config CPU_HAS_DCLS
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This option is enabled when the processor hardware is configured in
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Dual-redundant Core Lock-step (DCLS) topology.
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config CPU_HAS_DSP
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bool
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help
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This option is enabled when the CPU has hardware DSP unit.
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config CPU_HAS_FPU
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bool
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help
@@ -742,6 +747,24 @@ config FPU_SHARING
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endmenu
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menu "Digital Signal Processing Options"
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config DSP
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bool "This option enables digital signal processing (DSP)"
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depends on CPU_HAS_DSP
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help
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This option enables DSP and DSP instructions.
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config DSP_SHARING
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bool "DSP register sharing"
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depends on DSP && MULTITHREADING
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help
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This option enables preservation of the hardware DSP registers
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across context switches to allow multiple threads to perform concurrent
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DSP operations.
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endmenu
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menu "Cache Options"
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config DCACHE

‎arch/arc/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -327,6 +327,50 @@ config ARC_NORMAL_FIRMWARE
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resources of the ARC processors, and, therefore, it shall avoid
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accessing them.
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config ARC_DSP_BFLY_SHARING
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bool "ARC complex DSP operation"
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depends on DSP && CPU_ARCEM
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default n
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help
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This option is to enable Zephyr to store and restore DSP_BFLY0
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and FFT_CTRL registers during context switch. This option is
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only required when butterfly instructions are used in
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multi-thread.
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config ARC_HAS_AGU_REGS
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bool "ARC address generation unit registers"
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default n
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help
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Processors with XY memory and AGU registers can configure this
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option to accelerate DSP instrctions.
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config AGU_SHARING
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bool "ARC address generation unit register sharing"
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depends on ARC_HAS_AGU_REGS && MULTITHREADING
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help
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This option enables preservation of the hardware AGU registers
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across context switches to allow multiple threads to perform concurrent
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operations on XY memory. Save and restore small size AGU registers is
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set as default, including 4 address pointers regs, 2 address offset regs
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and 4 modifiers regs.
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config ARC_AGU_MEDIUM
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bool "ARC AGU medium size register"
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depends on AGU_SHARING
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default n
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help
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Save and restore medium AGU registers, including 8 address pointers regs,
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4 address offset regs and 12 modifiers regs.
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config ARC_AGU_LARGE
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bool "ARC AGU large size register"
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depends on AGU_SHARING
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default n
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select ARC_AGU_MEDIUM
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help
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Save and restore large AGU registers, including 12 address pointers regs,
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8 address offset regs and 24 modifiers regs.
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menu "ARC MPU Options"
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depends on CPU_HAS_MPU
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‎arch/arc/core/offsets/offsets.c‎

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,69 @@ GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2l);
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GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1h);
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GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1l);
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#endif
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#endif
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#ifdef CONFIG_DSP_SHARING
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GEN_OFFSET_SYM(_callee_saved_stack_t, dsp_ctrl);
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GEN_OFFSET_SYM(_callee_saved_stack_t, acc0_lo);
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GEN_OFFSET_SYM(_callee_saved_stack_t, acc0_glo);
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GEN_OFFSET_SYM(_callee_saved_stack_t, acc0_hi);
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GEN_OFFSET_SYM(_callee_saved_stack_t, acc0_ghi);
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#ifdef CONFIG_ARC_DSP_BFLY_SHARING
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GEN_OFFSET_SYM(_callee_saved_stack_t, dsp_bfly0);
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GEN_OFFSET_SYM(_callee_saved_stack_t, dsp_fft_ctrl);
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#endif
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#endif
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#ifdef CONFIG_AGU_SHARING
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap0);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap1);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap2);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap3);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os0);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os1);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod0);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod1);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod2);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod3);
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#ifdef CONFIG_ARC_AGU_MEDIUM
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap4);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap5);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap6);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap7);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os2);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os3);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod4);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod5);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod6);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod7);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod8);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod9);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod10);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod11);
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#endif
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#ifdef CONFIG_ARC_AGU_LARGE
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap8);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap9);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap10);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_ap11);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os4);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os5);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os6);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_os7);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod12);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod13);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod14);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod15);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod16);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod17);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod18);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod19);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod20);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod21);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod22);
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GEN_OFFSET_SYM(_callee_saved_stack_t, agu_mod23);
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#endif
179+
#endif
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GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
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GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));

‎arch/arc/core/thread.c‎

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Original file line numberDiff line numberDiff line change
@@ -20,6 +20,9 @@
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#include <zephyr/arch/arc/v2/mpu/arc_core_mpu.h>
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#endif
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#if defined(CONFIG_DSP) && defined(CONFIG_DSP_SHARING)
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static struct k_spinlock lock;
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#endif
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/* initial stack frame */
2427
struct init_stack_frame {
2528
uintptr_t pc;
@@ -253,3 +256,33 @@ int arch_float_enable(struct k_thread *thread, unsigned int options)
253256
return 0;
254257
}
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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#if defined(CONFIG_DSP) && defined(CONFIG_DSP_SHARING)
261+
int arch_dsp_disable(struct k_thread *thread, unsigned int options)
262+
{
263+
/* Ensure a preemptive context switch does not occur */
264+
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* Disable DSP or AGU capabilities for the thread */
268+
thread->base.user_options &= ~(uint8_t)options;
269+
270+
k_spin_unlock(&lock, key);
271+
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return 0;
273+
}
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275+
int arch_dsp_enable(struct k_thread *thread, unsigned int options)
276+
{
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/* Ensure a preemptive context switch does not occur */
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* Enable dsp or agu capabilities for the thread */
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thread->base.user_options |= (uint8_t)options;
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k_spin_unlock(&lock, key);
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return 0;
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}
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#endif /* CONFIG_DSP && CONFIG_DSP_SHARING */

‎arch/arc/include/kernel_arch_data.h‎

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Original file line numberDiff line numberDiff line change
@@ -156,7 +156,69 @@ struct _callee_saved_stack {
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uintptr_t dpfp1h;
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uintptr_t dpfp1l;
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#endif
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#endif
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#ifdef CONFIG_DSP_SHARING
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#ifdef CONFIG_ARC_DSP_BFLY_SHARING
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uintptr_t dsp_fft_ctrl;
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uintptr_t dsp_bfly0;
165+
#endif
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uintptr_t acc0_ghi;
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uintptr_t acc0_hi;
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uintptr_t acc0_glo;
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uintptr_t acc0_lo;
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uintptr_t dsp_ctrl;
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#endif
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#ifdef CONFIG_AGU_SHARING
174+
uintptr_t agu_ap0;
175+
uintptr_t agu_ap1;
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uintptr_t agu_ap2;
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uintptr_t agu_ap3;
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uintptr_t agu_os0;
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uintptr_t agu_os1;
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uintptr_t agu_mod0;
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uintptr_t agu_mod1;
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uintptr_t agu_mod2;
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uintptr_t agu_mod3;
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#ifdef CONFIG_ARC_AGU_MEDIUM
185+
uintptr_t agu_ap4;
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uintptr_t agu_ap5;
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uintptr_t agu_ap6;
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uintptr_t agu_ap7;
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uintptr_t agu_os2;
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uintptr_t agu_os3;
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uintptr_t agu_mod4;
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uintptr_t agu_mod5;
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uintptr_t agu_mod6;
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uintptr_t agu_mod7;
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uintptr_t agu_mod8;
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uintptr_t agu_mod9;
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uintptr_t agu_mod10;
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uintptr_t agu_mod11;
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#endif
200+
#ifdef CONFIG_ARC_AGU_LARGE
201+
uintptr_t agu_ap8;
202+
uintptr_t agu_ap9;
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uintptr_t agu_ap10;
204+
uintptr_t agu_ap11;
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uintptr_t agu_os4;
206+
uintptr_t agu_os5;
207+
uintptr_t agu_os6;
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uintptr_t agu_os7;
209+
uintptr_t agu_mod12;
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uintptr_t agu_mod13;
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uintptr_t agu_mod14;
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uintptr_t agu_mod15;
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uintptr_t agu_mod16;
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uintptr_t agu_mod17;
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uintptr_t agu_mod18;
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uintptr_t agu_mod19;
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uintptr_t agu_mod20;
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uintptr_t agu_mod21;
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uintptr_t agu_mod22;
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uintptr_t agu_mod23;
221+
#endif
160222
#endif
161223
/*
162224
* No need to save r31 (blink), it's either already pushed as the pc or

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