Verilog support for continuous assignment

[antonblanchard]

I'm not sure if simple continuous assignments are valid structural Verilog, but OpenROAD (well OpenSTA) does use them in some cases, so it would be nice to support it:

// Verilog "ports" are not distinct from nets.
// Use an assign statement to alias the net when it is connected to
// multiple output ports.

Steps to Reproduce the Problem

cat << EOF > testmodule.v
module testmodule (
    in,
    out
);
    input in;
    output out;

    assign out = in;

endmodule
EOF
./bigspicy.py --import --verilog testmodule.v

Specifications

• Version: 7b964ad

[QuantamHD]

Thanks for the bug report Anton!

What were you planning to do with bigspicy?

[antonblanchard]

@QuantamHD we have a ring oscillator based RNG on the FPGA version of Microwatt and I was wondering if we could build something similar on sky130. I want to keep the design as simple as possible (standard cells, OpenROAD to route etc), but did want to simulate it so we don't make an embarrassing mistake (the ring oscillators don't oscillate or they oscillate too slowly etc).

Since I want to combine the spice netlist with SPEF parasitics, I thought it would be an interesting to try bigspicy. Does it seem reasonable?

[QuantamHD]

Seems reasonable to me, just interested in your use case.

[growly]

I think the easiest way to support this is to just rename aliases wherever they appear. I can do that

[growly]

@antonblanchard I have an implementation for basic assignments, where wires just become aliases, but not for assignments where buses alias concatenations. Please send through any additional verilog files you want to share as test cases.

This has dependent changes in vlsir/schema-proto; once those are in I can push these.