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1 parent d952c3e commit 89b0f20Copy full SHA for 89b0f20
doc/usage.rst
@@ -175,7 +175,7 @@ Each port and generic is an instance of :py:class:`~hdlparse.verilog_parser.Veri
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import hdlparse.verilog_parser as vlog
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vlog_ex = vlog.VerilogExtractor()
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- vlog_mods = vlog_ex.extract_objects_from_source('example.v')
+ vlog_mods = vlog_ex.extract_objects('example.v')
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for m in vlog_mods:
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print('Module "{}":'.format(m.name))
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