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replacement policies: PLRU and LFU_aging
Signed-off-by: Aleksandr Mishin <[email protected]>
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‎README.md

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@@ -36,3 +36,39 @@ Expected results don't match current results. This could be on many reasons, for
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- If branches are mostly "true" or mostly "false" bimodal can perform very well;
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- Markov tables are too small;
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- The extra complexity of such predictor hurt more than help.
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# 2. L2 replacement policies.
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4 policies will be compared:
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- LRU (Least Recently Used)
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Tracks when each cache block was last accessed. On eviction, it selects the block not used for the longest time.
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- PLRU (Pseudo LRU)
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Uses a binary tree of bits to approximate LRU behavior with less metadata. Each bit points to the less recently used subtree.
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- LFU with Aging
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Each block has a usage counter. On hit, increment it; periodically, all counters are halved. This allows frequently used blocks to stay, but "forgets" old usage.
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- DRRIP (Dynamic Re-reference Interval Prediction)
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Uses a prediction counter to decide between SRRIP (static) and BRRIP (bimodal) policies dynamically. Balances recency vs. reuse behavior.
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## Expected result:
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| Policy | Hit Rate (↑ = better) |
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| --------- | ----------------------- |
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| LRU | ↑↑ (on temporal reuse) |
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| PLRU | ↑ |
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| LFU_Aging | ↑↑ (on stable patterns) |
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| DRRIP | ↑↑↑ (adaptive) |
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![replacement_comparison.png](replacement_comparison.png)
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## Results:
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| Policy | gmean L2 Miss Rate |
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| --------- | ------------------- |
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| LRU | 0.289 |
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| PLRU | 0.381 |
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| LFU_Aging | 0.284 |
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| DRRIP | 0.388 |
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Results are non-theoretically expected. LFU_aging and LRU are much better than DRRIP and PLRU. Looks like benchmarks data shows strong temporal and stable reuse.

‎drrip_runs/run_600.perlbench_s-1273B.champsimtrace.xz.txt

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[VMEM] WARNING: physical memory size is smaller than virtual memory size.
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WARNING: option --warmup_instructions is deprecated. Use --warmup-instructions instead.
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WARNING: option --simulation_instructions is deprecated. Use --simulation-instructions instead.
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*** ChampSim Multicore Out-of-Order Simulator ***
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Warmup Instructions: 10000000
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Simulation Instructions: 50000000
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Number of CPUs: 1
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Page size: 4096
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Off-chip DRAM Size: 16 GiB Channels: 1 Width: 64-bit Data Rate: 3205 MT/s
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Heartbeat CPU 0 instructions: 10000000 cycles: 2841212 heartbeat IPC: 3.52 cumulative IPC: 3.52 (Simulation time: 00 hr 12 min 50 sec)
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Warmup finished CPU 0 instructions: 10000000 cycles: 2841212 cumulative IPC: 3.52 (Simulation time: 00 hr 12 min 50 sec)
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Warmup complete CPU 0 instructions: 10000000 cycles: 2841212 cumulative IPC: 3.52 (Simulation time: 00 hr 12 min 50 sec)
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Heartbeat CPU 0 instructions: 20000004 cycles: 7626121 heartbeat IPC: 2.09 cumulative IPC: 2.09 (Simulation time: 00 hr 19 min 12 sec)
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Heartbeat CPU 0 instructions: 30000008 cycles: 12411310 heartbeat IPC: 2.09 cumulative IPC: 2.09 (Simulation time: 00 hr 24 min 55 sec)
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Heartbeat CPU 0 instructions: 40000011 cycles: 17280028 heartbeat IPC: 2.054 cumulative IPC: 2.078 (Simulation time: 00 hr 31 min 13 sec)
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Heartbeat CPU 0 instructions: 50000013 cycles: 22035741 heartbeat IPC: 2.103 cumulative IPC: 2.084 (Simulation time: 00 hr 37 min 41 sec)
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Simulation finished CPU 0 instructions: 50000001 cycles: 23704296 cumulative IPC: 2.109 (Simulation time: 00 hr 43 min 39 sec)
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Simulation complete CPU 0 instructions: 50000001 cycles: 23704296 cumulative IPC: 2.109 (Simulation time: 00 hr 43 min 39 sec)
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ChampSim completed all CPUs
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=== Simulation ===
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CPU 0 runs 2017_spec_cpu_traces/600.perlbench_s-1273B.champsimtrace.xz
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Region of Interest Statistics
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CPU 0 cumulative IPC: 2.109 instructions: 50000001 cycles: 23704296
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CPU 0 Branch Prediction Accuracy: 97.29% MPKI: 3.673 Average ROB Occupancy at Mispredict: 113.9
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Branch type MPKI
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BRANCH_DIRECT_JUMP: 0.01212
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BRANCH_INDIRECT: 0.379
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BRANCH_CONDITIONAL: 3.28
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BRANCH_DIRECT_CALL: 0.00112
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BRANCH_INDIRECT_CALL: 0.00022
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BRANCH_RETURN: 0.00112
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cpu0->cpu0_STLB TOTAL ACCESS: 13354 HIT: 13058 MISS: 296 MSHR_MERGE: 0
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cpu0->cpu0_STLB LOAD ACCESS: 13354 HIT: 13058 MISS: 296 MSHR_MERGE: 0
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cpu0->cpu0_STLB RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_STLB AVERAGE MISS LATENCY: 336.3 cycles
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cpu0->cpu0_L2C TOTAL ACCESS: 4178 HIT: 1526 MISS: 2652 MSHR_MERGE: 0
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cpu0->cpu0_L2C LOAD ACCESS: 3557 HIT: 1134 MISS: 2423 MSHR_MERGE: 0
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cpu0->cpu0_L2C RFO ACCESS: 91 HIT: 21 MISS: 70 MSHR_MERGE: 0
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cpu0->cpu0_L2C PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L2C WRITE ACCESS: 261 HIT: 261 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L2C TRANSLATION ACCESS: 269 HIT: 110 MISS: 159 MSHR_MERGE: 0
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cpu0->cpu0_L2C PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_L2C AVERAGE MISS LATENCY: 186.3 cycles
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cpu0->cpu0_L1I TOTAL ACCESS: 1767266 HIT: 1765717 MISS: 1549 MSHR_MERGE: 277
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cpu0->cpu0_L1I LOAD ACCESS: 1767266 HIT: 1765717 MISS: 1549 MSHR_MERGE: 277
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cpu0->cpu0_L1I RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_L1I AVERAGE MISS LATENCY: 35.42 cycles
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cpu0->cpu0_L1D TOTAL ACCESS: 16737763 HIT: 16734183 MISS: 3580 MSHR_MERGE: 935
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cpu0->cpu0_L1D LOAD ACCESS: 6554086 HIT: 6551076 MISS: 3010 MSHR_MERGE: 725
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cpu0->cpu0_L1D RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1D PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1D WRITE ACCESS: 10183356 HIT: 10183055 MISS: 301 MSHR_MERGE: 210
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cpu0->cpu0_L1D TRANSLATION ACCESS: 321 HIT: 52 MISS: 269 MSHR_MERGE: 0
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cpu0->cpu0_L1D PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_L1D AVERAGE MISS LATENCY: 182.2 cycles
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cpu0->cpu0_ITLB TOTAL ACCESS: 1543083 HIT: 1542674 MISS: 409 MSHR_MERGE: 282
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cpu0->cpu0_ITLB LOAD ACCESS: 1543083 HIT: 1542674 MISS: 409 MSHR_MERGE: 282
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cpu0->cpu0_ITLB RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_ITLB AVERAGE MISS LATENCY: 20.31 cycles
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cpu0->cpu0_DTLB TOTAL ACCESS: 15030558 HIT: 15015829 MISS: 14729 MSHR_MERGE: 1502
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cpu0->cpu0_DTLB LOAD ACCESS: 15030558 HIT: 15015829 MISS: 14729 MSHR_MERGE: 1502
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cpu0->cpu0_DTLB RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_DTLB AVERAGE MISS LATENCY: 12.4 cycles
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cpu0->LLC TOTAL ACCESS: 2656 HIT: 5 MISS: 2651 MSHR_MERGE: 0
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cpu0->LLC LOAD ACCESS: 2423 HIT: 1 MISS: 2422 MSHR_MERGE: 0
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cpu0->LLC RFO ACCESS: 70 HIT: 0 MISS: 70 MSHR_MERGE: 0
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cpu0->LLC PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->LLC WRITE ACCESS: 4 HIT: 4 MISS: 0 MSHR_MERGE: 0
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cpu0->LLC TRANSLATION ACCESS: 159 HIT: 0 MISS: 159 MSHR_MERGE: 0
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cpu0->LLC PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->LLC AVERAGE MISS LATENCY: 170.4 cycles
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DRAM Statistics
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Channel 0 RQ ROW_BUFFER_HIT: 40
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ROW_BUFFER_MISS: 2611
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AVG DBUS CONGESTED CYCLE: 2.781
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Channel 0 WQ ROW_BUFFER_HIT: 0
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ROW_BUFFER_MISS: 0
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FULL: 0
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Channel 0 REFRESHES ISSUED: 1976

‎drrip_runs/run_602.gcc_s-1850B.champsimtrace.xz.txt

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[VMEM] WARNING: physical memory size is smaller than virtual memory size.
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WARNING: option --warmup_instructions is deprecated. Use --warmup-instructions instead.
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WARNING: option --simulation_instructions is deprecated. Use --simulation-instructions instead.
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*** ChampSim Multicore Out-of-Order Simulator ***
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Warmup Instructions: 10000000
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Simulation Instructions: 50000000
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Number of CPUs: 1
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Page size: 4096
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Off-chip DRAM Size: 16 GiB Channels: 1 Width: 64-bit Data Rate: 3205 MT/s
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Heartbeat CPU 0 instructions: 10000003 cycles: 2889726 heartbeat IPC: 3.461 cumulative IPC: 3.461 (Simulation time: 00 hr 11 min 27 sec)
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Warmup finished CPU 0 instructions: 10000003 cycles: 2889726 cumulative IPC: 3.461 (Simulation time: 00 hr 11 min 27 sec)
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Warmup complete CPU 0 instructions: 10000003 cycles: 2889726 cumulative IPC: 3.461 (Simulation time: 00 hr 11 min 27 sec)
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Heartbeat CPU 0 instructions: 20000004 cycles: 43010502 heartbeat IPC: 0.2492 cumulative IPC: 0.2492 (Simulation time: 00 hr 43 min 15 sec)
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Heartbeat CPU 0 instructions: 30000004 cycles: 83026193 heartbeat IPC: 0.2499 cumulative IPC: 0.2496 (Simulation time: 01 hr 04 min 01 sec)
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Heartbeat CPU 0 instructions: 40000005 cycles: 123126547 heartbeat IPC: 0.2494 cumulative IPC: 0.2495 (Simulation time: 01 hr 18 min 56 sec)
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Heartbeat CPU 0 instructions: 50000009 cycles: 163175414 heartbeat IPC: 0.2497 cumulative IPC: 0.2496 (Simulation time: 01 hr 32 min 23 sec)
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Simulation finished CPU 0 instructions: 50000004 cycles: 200353478 cumulative IPC: 0.2496 (Simulation time: 01 hr 45 min 35 sec)
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Simulation complete CPU 0 instructions: 50000004 cycles: 200353478 cumulative IPC: 0.2496 (Simulation time: 01 hr 45 min 35 sec)
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ChampSim completed all CPUs
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=== Simulation ===
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CPU 0 runs 2017_spec_cpu_traces/602.gcc_s-1850B.champsimtrace.xz
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Region of Interest Statistics
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CPU 0 cumulative IPC: 0.2496 instructions: 50000004 cycles: 200353478
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CPU 0 Branch Prediction Accuracy: 92.26% MPKI: 19.85 Average ROB Occupancy at Mispredict: 28.67
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Branch type MPKI
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BRANCH_DIRECT_JUMP: 0.01114
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BRANCH_INDIRECT: 0
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BRANCH_CONDITIONAL: 19.84
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BRANCH_DIRECT_CALL: 0
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BRANCH_INDIRECT_CALL: 0
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BRANCH_RETURN: 0
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cpu0->cpu0_STLB TOTAL ACCESS: 16342 HIT: 1123 MISS: 15219 MSHR_MERGE: 0
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cpu0->cpu0_STLB LOAD ACCESS: 16342 HIT: 1123 MISS: 15219 MSHR_MERGE: 0
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cpu0->cpu0_STLB RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_STLB PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_STLB AVERAGE MISS LATENCY: 229.2 cycles
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cpu0->cpu0_L2C TOTAL ACCESS: 1207413 HIT: 314828 MISS: 892585 MSHR_MERGE: 0
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cpu0->cpu0_L2C LOAD ACCESS: 1201557 HIT: 311691 MISS: 889866 MSHR_MERGE: 0
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cpu0->cpu0_L2C RFO ACCESS: 396 HIT: 0 MISS: 396 MSHR_MERGE: 0
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cpu0->cpu0_L2C PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L2C WRITE ACCESS: 3158 HIT: 2749 MISS: 409 MSHR_MERGE: 0
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cpu0->cpu0_L2C TRANSLATION ACCESS: 2302 HIT: 388 MISS: 1914 MSHR_MERGE: 0
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cpu0->cpu0_L2C PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_L2C AVERAGE MISS LATENCY: 158.7 cycles
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cpu0->cpu0_L1I TOTAL ACCESS: 381 HIT: 381 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I LOAD ACCESS: 381 HIT: 381 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1I PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_L1I AVERAGE MISS LATENCY: - cycles
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cpu0->cpu0_L1D TOTAL ACCESS: 14940210 HIT: 12848049 MISS: 2092161 MSHR_MERGE: 887907
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cpu0->cpu0_L1D LOAD ACCESS: 10609256 HIT: 8519793 MISS: 2089463 MSHR_MERGE: 887907
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cpu0->cpu0_L1D RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1D PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_L1D WRITE ACCESS: 4315581 HIT: 4315185 MISS: 396 MSHR_MERGE: 0
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cpu0->cpu0_L1D TRANSLATION ACCESS: 15373 HIT: 13071 MISS: 2302 MSHR_MERGE: 0
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cpu0->cpu0_L1D PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_L1D AVERAGE MISS LATENCY: 126.4 cycles
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cpu0->cpu0_ITLB TOTAL ACCESS: 288 HIT: 288 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB LOAD ACCESS: 288 HIT: 288 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_ITLB PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_ITLB AVERAGE MISS LATENCY: - cycles
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cpu0->cpu0_DTLB TOTAL ACCESS: 14535915 HIT: 14505582 MISS: 30333 MSHR_MERGE: 13991
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cpu0->cpu0_DTLB LOAD ACCESS: 14535915 HIT: 14505582 MISS: 30333 MSHR_MERGE: 13991
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cpu0->cpu0_DTLB RFO ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB WRITE ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB TRANSLATION ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->cpu0_DTLB PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->cpu0_DTLB AVERAGE MISS LATENCY: 219.3 cycles
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cpu0->LLC TOTAL ACCESS: 892495 HIT: 2670 MISS: 889825 MSHR_MERGE: 0
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cpu0->LLC LOAD ACCESS: 889866 HIT: 1968 MISS: 887898 MSHR_MERGE: 0
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cpu0->LLC RFO ACCESS: 396 HIT: 0 MISS: 396 MSHR_MERGE: 0
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cpu0->LLC PREFETCH ACCESS: 0 HIT: 0 MISS: 0 MSHR_MERGE: 0
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cpu0->LLC WRITE ACCESS: 319 HIT: 276 MISS: 43 MSHR_MERGE: 0
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cpu0->LLC TRANSLATION ACCESS: 1914 HIT: 426 MISS: 1488 MSHR_MERGE: 0
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cpu0->LLC PREFETCH REQUESTED: 0 ISSUED: 0 USEFUL: 0 USELESS: 0
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cpu0->LLC AVERAGE MISS LATENCY: 143.1 cycles
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DRAM Statistics
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Channel 0 RQ ROW_BUFFER_HIT: 221645
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ROW_BUFFER_MISS: 668137
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AVG DBUS CONGESTED CYCLE: 16.48
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Channel 0 WQ ROW_BUFFER_HIT: 69
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ROW_BUFFER_MISS: 238
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FULL: 0
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Channel 0 REFRESHES ISSUED: 16696

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