Support for SIMD types and instructions

[yorickpeterse]

Description

A variety of algorithms benefit greatly from SIMD instructions to speed up performance, but we don't support any form of SIMD right now.

I'm not sure yet how I envision this support, what would need to be done, and so on, so this issue serves as a place to collect all that information.

A few things come to mind:

• We need a few dedicated vector types (Vector128, Vector256, etc) to account for the different vector sizes.
  • While RISC-V and possibly others (I think ARM?) support variable/"scalable" vectors instead of fixed-size vectors, I don't know what it would take to support both and if LLVM even has proper support for it.
• Instead of users specifying that they want AVXwhatever, NEON, etc, we'd default to requiring at least some recent version of SSE or even AVX, then provide more generic flags (e.g. --simd=256) to enable specific bit sizes, with the compiler figuring out whether that translates to AVX, NEON, whatever
• I have no idea how move semantics would apply to vectors, as they're essentially a high-level representation of a bunch of SIMD registers. For example, what if you call a method on a vector type and the method isn't inlined? LLVM wouldn't be able to use actual vector registers I think, as the call would create a new stack frame. This likely means we first need the ability to forcefully inline certain methods
• This is likely quite a way off, as we don't apply any optimizations right now, and I want to tackle that first

Related work

• https://llvm.org/docs/LangRef.html#vector-type