osecpu.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Intel and sold by Intel or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 23:39:10  June 04, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		osecpu_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:39:10  JUNE 04, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_location_assignment PIN_127 -to seg[0]
set_location_assignment PIN_124 -to seg[1]
set_location_assignment PIN_126 -to seg[2]
set_location_assignment PIN_132 -to seg[3]
set_location_assignment PIN_129 -to seg[4]
set_location_assignment PIN_125 -to seg[5]
set_location_assignment PIN_121 -to seg[6]
set_location_assignment PIN_128 -to seg[7]
set_location_assignment PIN_133 -to segsel[0]
set_location_assignment PIN_135 -to segsel[1]
set_location_assignment PIN_136 -to segsel[2]
set_location_assignment PIN_137 -to segsel[3]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_23 -to clk_org
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE mmu.v
set_global_assignment -name VERILOG_FILE def.v
set_global_assignment -name VERILOG_FILE check.v
set_global_assignment -name VERILOG_FILE blockram.v
set_global_assignment -name VERILOG_FILE addrdec.v
set_global_assignment -name VERILOG_FILE datapath.v
set_global_assignment -name VERILOG_FILE labeltable.v
set_global_assignment -name VERILOG_FILE controller.v
set_global_assignment -name VERILOG_FILE osecpu.v
set_global_assignment -name VERILOG_FILE preg.v
set_global_assignment -name VERILOG_FILE testbench.v
set_global_assignment -name VERILOG_FILE opdecoder.v
set_global_assignment -name VERILOG_FILE memory.v
set_global_assignment -name VERILOG_FILE ireg.v
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name VERILOG_FILE led7seg.v
set_global_assignment -name VERILOG_FILE top.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top