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The SPI master is simple controller for communication between FPGA and various peripherals via the SPI interface. The SPI master was implemented using VHDL 93 and is applicable to any FPGA.
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**The SPI master controller support only SPI mode 0 (CPOL=0, CPHA=0)!**
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The SPI master controller was simulated.
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# Synthesis results summary:
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DATA_WIDTH | LE (LUT) | FF | BRAM | Fmax
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:---:|:---:|:---:|:---:|:---:
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8b | 28 | 22 | 0 | 307.4MHz
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16b | 39 | 31 | 0 | 211.3MHz
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*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 for FPGA Altera Cyclone II with these settings: CLK_FREQ = 50 MHz, SCLK_FREQ = 5 MHz.*
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