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jakubcabaljakubcabal
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Some bugfix, added SPI loopback example.
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‎README.md

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@@ -10,8 +10,8 @@ The SPI master and SPI slave controllers have been simulated.
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CONTROLLER | LE (LUT) | FF | BRAM | Fmax
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:---:|:---:|:---:|:---:|:---:
13-
SPI master | 36 | 25 | 0 | 346.9 MHz
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SPI slave | 26 | 19 | 0 | 438.7 MHz
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SPI master | 39 | 26 | 0 | 264.7 MHz
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SPI slave | 23 | 16 | 0 | 359.7 MHz
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*Synthesis have been performed using Quartus Prime 16.1 Lite Edition for FPGA Altera Cyclone IV with these settings: CLK_FREQ = 50 MHz, SCLK_FREQ = 5 MHz, SLAVE_COUNT = 1.*
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@@ -27,8 +27,8 @@ Please read [LICENSE file](LICENSE).
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Generic name | Type | Default value | Generic description
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---|:---:|:---:|:---
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CLK_FREQ | natural | 50 | System clock frequency in MHz.
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SCLK_FREQ | natural | 5 | SPI clock frequency in MHz (must be < CLK_FREQ/9).
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CLK_FREQ | natural | 50 | System clock frequency in Hz.
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SCLK_FREQ | natural | 5 | Set SPI clock frequency in Hz (condition: SCLK_FREQ <= CLK_FREQ/10).
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SLAVE_COUNT | natural | 1 | Count of SPI slave controllers.
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## Table of inputs and outputs ports:

‎example/comp/btn_debounce.vhd

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--------------------------------------------------------------------------------
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-- PROJECT: FPGA MISC
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--------------------------------------------------------------------------------
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-- NAME: BTN_DEBOUNCE
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-- AUTHORS: Jakub Cabal <[email protected]>
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-- LICENSE: The MIT License
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-- WEBSITE: https://github.com/jakubcabal/fpga-misc
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity BTN_DEBOUNCE is
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Port (
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CLK : in std_logic; -- system clock
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CLK_EN_1K : in std_logic; -- clock enable 1 KHz
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ASYNC_RST : in std_logic; -- asynchrounous reset
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BTN_RAW : in std_logic; -- button raw signal
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BTN_DEB : out std_logic; -- button debounce signal
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BTN_DEB_EN : out std_logic -- button debounce rising edge enable
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);
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end BTN_DEBOUNCE;
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architecture RTL of BTN_DEBOUNCE is
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signal btn_raw_shreg : std_logic_vector(3 downto 0);
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signal btn_deb_comb : std_logic;
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signal btn_deb_reg : std_logic;
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signal btn_deb_en_reg : std_logic;
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begin
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-- -------------------------------------------------------------------------
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-- SHIFT REGISTER OF BUTTON RAW SIGNAL
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-- -------------------------------------------------------------------------
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btn_shreg_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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btn_raw_shreg <= (others => '0');
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elsif (rising_edge(CLK)) then
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if (CLK_EN_1K = '1') then
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btn_raw_shreg <= btn_raw_shreg(2 downto 0) & BTN_RAW;
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end if;
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end if;
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end process;
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-- -------------------------------------------------------------------------
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-- DEBOUNCE REGISTER OF BUTTON RAW SIGNAL
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-- -------------------------------------------------------------------------
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btn_deb_comb <= btn_raw_shreg(0) and btn_raw_shreg(1) and
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btn_raw_shreg(2) and btn_raw_shreg(3);
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btn_deb_reg_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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btn_deb_reg <= '0';
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elsif (rising_edge(CLK)) then
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btn_deb_reg <= btn_deb_comb;
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end if;
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end process;
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BTN_DEB <= btn_deb_reg;
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-- -------------------------------------------------------------------------
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-- RISING EDGE DETECTOR OF BUTTON DEBOUNCE SIGNAL
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-- -------------------------------------------------------------------------
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sseg_an_cnt_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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btn_deb_en_reg <= '0';
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elsif (rising_edge(CLK)) then
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btn_deb_en_reg <= btn_deb_comb and not btn_deb_reg;
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end if;
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end process;
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BTN_DEB_EN <= btn_deb_en_reg;
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end RTL;

‎example/comp/clk_en_gen.vhd

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--------------------------------------------------------------------------------
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-- PROJECT: FPGA MISC
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--------------------------------------------------------------------------------
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-- NAME: CLK_EN_GEN
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-- AUTHORS: Jakub Cabal <[email protected]>
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-- LICENSE: The MIT License
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-- WEBSITE: https://github.com/jakubcabal/fpga-misc
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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entity CLK_EN_GEN is
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Generic (
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CLK_FREQ : natural := 50e6 -- set system clock frequency in Hz
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);
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Port (
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CLK : in std_logic; -- system clock
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ASYNC_RST : in std_logic; -- asynchrounous reset
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CLK_EN_1K : out std_logic -- clock enable 1 KHz output
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);
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end CLK_EN_GEN;
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architecture RTL of CLK_EN_GEN is
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constant CLK_EN_1K_DIV : integer := CLK_FREQ/1e3;
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signal clk_en_1k_cnt : integer range 0 to CLK_EN_1K_DIV-1;
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signal clk_en_1k_comb : std_logic;
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signal clk_en_1k_reg : std_logic;
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begin
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-- -------------------------------------------------------------------------
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-- COUNTER OF CLOCK ENABLE (~1KHz)
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-- -------------------------------------------------------------------------
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clk_en_1k_cnt_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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clk_en_1k_cnt <= 0;
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elsif (rising_edge(CLK)) then
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if (clk_en_1k_cnt = CLK_EN_1K_DIV-1) then
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clk_en_1k_cnt <= 0;
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else
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clk_en_1k_cnt <= clk_en_1k_cnt + 1;
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end if;
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end if;
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end process;
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-- -------------------------------------------------------------------------
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-- GENERATOR OF CLOCK ENABLE (~1KHz)
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-- -------------------------------------------------------------------------
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clk_en_1k_comb <= '1' when (clk_en_1k_cnt = CLK_EN_1K_DIV-1) else '0';
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clk_en_1k_reg_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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clk_en_1k_reg <= '0';
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elsif (rising_edge(CLK)) then
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clk_en_1k_reg <= clk_en_1k_comb;
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end if;
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end process;
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CLK_EN_1K <= clk_en_1k_reg;
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end RTL;

‎example/comp/sseg_driver.vhd

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--------------------------------------------------------------------------------
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-- PROJECT: FPGA MISC
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--------------------------------------------------------------------------------
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-- NAME: SSEG_DRIVER
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-- AUTHORS: Jakub Cabal <[email protected]>
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-- LICENSE: The MIT License
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-- WEBSITE: https://github.com/jakubcabal/fpga-misc
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity SSEG_DRIVER is
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Port (
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CLK : in std_logic; -- system clock
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CLK_EN_1K : in std_logic; -- clock enable 1 KHz
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ASYNC_RST : in std_logic; -- asynchrounous reset
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-- USER INTERFACE
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DATA0 : in std_logic_vector(3 downto 0); -- BCD or HEX(4b)
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DATA1 : in std_logic_vector(3 downto 0); -- BCD or HEX(4b)
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DATA2 : in std_logic_vector(3 downto 0); -- BCD or HEX(4b)
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DATA3 : in std_logic_vector(3 downto 0); -- BCD or HEX(4b)
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DOTS : in std_logic_vector(3 downto 0); -- DP on/off
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-- SSEG INTERFACE
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SSEG : out std_logic_vector(7 downto 0); -- "dot" & "gfedcba"
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SSEG_AN : out std_logic_vector(3 downto 0) -- sseg anodes
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);
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end SSEG_DRIVER;
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architecture RTL of SSEG_DRIVER is
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signal sseg_anode_cnt : unsigned(1 downto 0);
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signal sseg_anode : std_logic_vector(3 downto 0);
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signal sseg_anode_reg : std_logic_vector(3 downto 0);
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signal sseg_bin : std_logic_vector(3 downto 0);
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signal sseg_code : std_logic_vector(6 downto 0);
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signal sseg_dp : std_logic;
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signal sseg_REG : std_logic_vector(7 downto 0);
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begin
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-- -------------------------------------------------------------------------
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-- SSEG ANODE MUXING
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-- -------------------------------------------------------------------------
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sseg_an_cnt_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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sseg_anode_cnt <= (others => '0');
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elsif (rising_edge(CLK)) then
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if (CLK_EN_1K = '1') then
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sseg_anode_cnt <= sseg_anode_cnt + 1;
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end if;
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end if;
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end process;
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process(sseg_anode_cnt, DATA0, DATA1, DATA2, DATA3, DOTS)
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begin
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case sseg_anode_cnt is
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when "00" =>
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sseg_bin <= DATA0;
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sseg_dp <= not DOTS(0);
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sseg_anode <= "1110";
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when "01" =>
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sseg_bin <= DATA1;
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sseg_dp <= not DOTS(1);
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sseg_anode <= "1101";
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when "10" =>
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sseg_bin <= DATA2;
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sseg_dp <= not DOTS(2);
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sseg_anode <= "1011";
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when "11" =>
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sseg_bin <= DATA3;
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sseg_dp <= not DOTS(3);
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sseg_anode <= "0111";
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when others =>
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sseg_bin <= DATA0;
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sseg_dp <= not DOTS(0);
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sseg_anode <= "1110";
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end case;
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end process;
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-- -------------------------------------------------------------------------
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-- SSEG ANODE REGISTER
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-- -------------------------------------------------------------------------
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sseg_anode_reg_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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sseg_anode_reg <= (others => '1');
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elsif (rising_edge(CLK)) then
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sseg_anode_reg <= sseg_anode;
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end if;
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end process;
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SSEG_AN <= sseg_anode_reg;
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-- -------------------------------------------------------------------------
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-- SSEG DECODER
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-- -------------------------------------------------------------------------
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with sseg_bin select
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sseg_code <= "1000000" when "0000", -- 0
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"1111001" when "0001", -- 1
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"0100100" when "0010", -- 2
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"0110000" when "0011", -- 3
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"0011001" when "0100", -- 4
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"0010010" when "0101", -- 5
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"0000010" when "0110", -- 6
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"1111000" when "0111", -- 7
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"0000000" when "1000", -- 8
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"0010000" when "1001", -- 9
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"0001000" when "1010", -- A
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"0000011" when "1011", -- B
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"1000110" when "1100", -- C
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"0100001" when "1101", -- D
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"0000110" when "1110", -- E
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"0001110" when "1111", -- F
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"1111111" when others; -- nic
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-- "gfedcba"
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-- -------------------------------------------------------------------------
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-- SSEG REGISTER
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-- -------------------------------------------------------------------------
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sseg_reg_p : process (CLK, ASYNC_RST)
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begin
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if (ASYNC_RST = '1') then
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sseg_reg <= (others => '1');
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elsif (rising_edge(CLK)) then
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sseg_reg <= sseg_dp & sseg_code;
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end if;
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end process;
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SSEG <= sseg_reg;
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end RTL;

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