STM32L0 configured

[MikeAtETI]

Hi,

Has anyone configured this for an STM32L0 - I thought I'd stepped through the changes to vUlpPreSleepProcessing and vUlpPostSleepProcessing but I can't get it working reliably:

void vUlpPreSleepProcessing(TickType_t* value)
{
   int useDeepSleep = pdFALSE;
   if (xDeepSleepForbiddenFlags == 0)
   {
      useDeepSleep = pdTRUE;
     // MODIFY_REG(PWR->CR, PWR_CR1_LPMS_Msk, PWR_CR1_LPMS_STOP2);
   }
   else if ((xDeepSleepForbiddenFlags & ~ulpPERIPHERALS_OK_IN_STOP1) == 0)
   {
      useDeepSleep = pdTRUE;
    //  MODIFY_REG(PWR->CR, PWR_CR1_LPMS_Msk, PWR_CR1_LPMS_STOP1);
   }

   if (useDeepSleep)
   {
	      uint32_t tmpreg = 0U;
	      uint32_t ulpbit, vrefinbit;
      rccCrSave = RCC->CR;
      rccCfgrSave = RCC->CFGR;

      HAL_PWREx_EnableUltraLowPower();
      HAL_PWREx_EnableFastWakeUp();

      /* It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
         in Stop mode or in Sleep/Low-power sleep mode */
      ulpbit = READ_BIT(PWR->CR, PWR_CR_ULP);
      vrefinbit = READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT);
      if((ulpbit != 0) && (vrefinbit != 0))
      {
        CLEAR_BIT(PWR->CR, PWR_CR_ULP);
      }

      /* Select the regulator state in Stop mode ---------------------------------*/
      tmpreg = PWR->CR;

      /* Clear PDDS and LPDS bits */
      CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));

     /* Set LPSDSR bit according to PWR_Regulator value */
      SET_BIT(tmpreg, PWR_LOWPOWERREGULATOR_ON);

      /* Store the new value */
      PWR->CR = tmpreg;

      /* Set SLEEPDEEP bit of Cortex System Control Register */
      SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);

      /* Select Stop mode entry --------------------------------------------------*/
        /* Request Wait For Interrupt */
        __WFI();

      /* Reset SLEEPDEEP bit of Cortex System Control Register */

        if((ulpbit != 0) && (vrefinbit != 0))
      {
        SET_BIT(PWR->CR, PWR_CR_ULP);
      }

      *value = 0;
      return;
      //SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
   }
   *value = 1;
}

void vUlpPostSleepProcessing(TickType_t value)
{
   if (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk)
   {
      #ifdef configMIN_RUN_BETWEEN_DEEP_SLEEPS    // Errata workaround
      {
         //     Start a new SysTick timer period.  We won't attempt to enter STOP mode until the timer period
         // ends.  Note that we do start a new period here unnecessarily if the CPU didn't actually enter stop
         // mode (due to a pending interrupt).  That's OK.
         //
         SysTick->VAL = 0;
         SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk;

         //      Mark the "min-run" peripheral as being now in use so that we won't attempt STOP mode until
         // it's no longer in use.  See SysTick_Handler() below.
         //
         xDeepSleepForbiddenFlags |= ulpPERIPHERAL_MIN_RUN;
      }
      #endif

      //      We may have been in deep sleep.  If we were, the hardware cleared several enable bits in the CR,
      // and it changed the selected system clock in CFGR.  Restore them now.  If we're restarting the PLL as
      // the CPU clock here, the CPU will not wait for it.  Instead, the CPU continues executing from the
      // wake-up clock (MSI in our case) until the PLL is stable and then the CPU starts using the PLL.
      //
      RCC->CR = rccCrSave;
      RCC->CFGR = rccCfgrSave;

      SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;

      //      This application bypasses the RTC shadow registers, so we don't need to clear the sync flag for
      // those registers.  They are always out of sync when coming out of deep sleep.
      //
      // RTC->ISR &= ~RTC_ISR_RSF;
   }
}

and

void vPortSetupTimerInterrupt( void )
{
   //      Enable the APB clock to the LPTIM.  Then select either LSE or LSI as the kernel clock for the
   // LPTIM.  Then be sure the LPTIM "freezes" when the debugger stops program execution.  Then reset the
   // LPTIM just in case it was already in use prior to this function.
   //
   //      Modify these statements as needed for your STM32.  See LPTIM Instance Selection (above) for
   // additional information.
   //
#ifdef STM32L0
   RCC->APB1ENR |= RCC_APB1ENR_LPTIM1EN;
   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMSEL_Val << RCC_CCIPR_LPTIM1SEL_Pos);
   DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_LPTIMER_STOP;
   RCC->APB1RSTR |= RCC_APB1RSTR_LPTIM1RST;   // Reset the LPTIM module per erratum 2.14.1.
   RCC->APB1RSTR &= ~RCC_APB1RSTR_LPTIM1RST;
#else
   RCC->APB1ENR1 |= RCC_APB1ENR1_LPTIM1EN;
   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMSEL_Val << RCC_CCIPR_LPTIM1SEL_Pos);
   DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_LPTIM1_STOP;
   RCC->APB1RSTR1 |= RCC_APB1RSTR1_LPTIM1RST;   // Reset the LPTIM module per erratum 2.14.1.
   RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_LPTIM1RST;
#endif
   #ifdef STM32WL   // <-- "Family" symbol is defined in the ST device header file, e.g., "stm32wlxx.h".
   {
      #define EXTI_IMR1_LPTIM1   (1UL << 29)
      #define EXTI_IMR1_LPTIM2   (1UL << 30)
      #define EXTI_IMR1_LPTIM3   (1UL << 31)

      //      Users of STM32WL must also change this next statement to match their LPTIM instance selection.
      // By default these MCU's disable wake-up from deep sleep via LPTIM.  An oversight by ST?
      //
      EXTI->IMR1 |= EXTI_IMR1_LPTIM1;
   }
   #endif

   //      Be sure the reference clock is ready.  If this assertion fails, be sure your application code
   // starts the reference clock (LSE or LSI) prior to starting FreeRTOS.
   //
   configASSERT(IS_REF_CLOCK_READY());

   //      Calculate the constants required to configure the tick interrupt.
   //
   ulTimerCountsForOneTick = ( LPTIM_CLOCK_HZ + ( configTICK_RATE_HZ / 2 ) ) / configTICK_RATE_HZ;
   configASSERT( ulTimerCountsForOneTick >= 4UL );  // CLOCK frequency must be at least 3.5x TICK frequency

   //      Calculate the maximum number of ticks we can suppress.  Give 1 OS tick of margin between clearly
   // future match events and clearly past match events.  Anything within the previous one tick is clearly
   // past, within one tick before that is in the margin between, which we call the past for convenience.
   // Everything else is in the future when isTickNowSuppressed is true and in the past otherwise.  And
   // set up a couple of other things for the precision feature, if enabled.

   #if ( configLPTIM_ENABLE_PRECISION == 0 )
   {
      xMaximumSuppressedTicks = 65536UL / ulTimerCountsForOneTick - 1 - 1;
   }
   #else
   {
      xMaximumSuppressedTicks = 65536UL * configTICK_RATE_HZ / LPTIM_CLOCK_HZ - 1 - 1;

      //      For convenience, the code above rounded *up* if the ideal number of counts per tick is exactly
      // X.5.  So we might calculate lSubcountErrorPerTick to be -(configTICK_RATE_HZ/2) but never
      // +(configTICK_RATE_HZ/2).  If you get a build error on this line, be sure configTICK_RATE_HZ is a
      // simple numeric literal (eg, 1000UL) with no C typecasting (eg, (TickType_t)1000).
      //
      #if ( LPTIM_CLOCK_HZ % configTICK_RATE_HZ < configTICK_RATE_HZ/2 )
         #define IS_SUBCOUNT_EPT_POSITIVE 1
      #else
         #define IS_SUBCOUNT_EPT_POSITIVE 0
      #endif

      lSubcountErrorPerTick = LPTIM_CLOCK_HZ - ( ulTimerCountsForOneTick * configTICK_RATE_HZ );
      configASSERT( lSubcountErrorPerTick != configTICK_RATE_HZ / 2 );
   }
   #endif // configLPTIM_ENABLE_PRECISION


   //      Configure and start LPTIM.
   //
   LPTIM->IER = LPTIM_IER_CMPMIE | LPTIM_IER_CMPOKIE;   // Modify this register only when LPTIM is disabled.
   LPTIM->CFGR = (0 << LPTIM_CFGR_PRESC_Pos);           // Modify this register only when LPTIM is disabled.
   LPTIM->CR = LPTIM_CR_ENABLE;
   LPTIM->ARR = 0xFFFF;        // timer period = ARR + 1.  Modify this register only when LPTIM is enabled.
   LPTIM->CMP = ulTimerCountsForOneTick;                // Modify this register only when LPTIM is enabled.
   isCmpWriteInProgress = pdTRUE;
   usIdealCmp = ulTimerCountsForOneTick;
   #if ( configLPTIM_ENABLE_PRECISION != 0 )
   {
      lRunningSubcountError = lSubcountErrorPerTick;
   }
   #endif // configLPTIM_ENABLE_PRECISION
   LPTIM->CR |= LPTIM_CR_CNTSTRT;

   //      Enable the timer interrupt at the configured priority.  See configTICK_INTERRUPT_PRIORITY for
   // important details.
   //
   NVIC_SetPriority( LPTIM_IRQn, configTICK_INTERRUPT_PRIORITY );
   NVIC_EnableIRQ( LPTIM_IRQn );
}

[Scarittagle]

I know this post is old but if you are using MXCube to generate code base, STM32L0 uses FreeRTOS Version 10.2.1 instead of other MCUs use newer 10.3.1 (as of July 2024). And in 10.2.1, the Setup Timer Interrupt function is defined as void prvSetupTimerInterrupt( void ) instead of __attribute__(( weak )) void vPortSetupTimerInterrupt( void ), that's why it wouldn't work: it is not calling the function at all.

You will need to modify it in port.c in order to get it to work.

[jefftenney]

Thanks @Scarittagle, that is useful information for users of CubeMX. On STM32L0, CubeMX generates FreeRTOS kernel files too old for lptimTick.c.

For perspective, all users of lptimTick.c should be using FreeRTOS kernel v10.4 or newer, as noted in this comment.

If you are developing a project today using STM32L0 and CubeMX, I would suggest integrating the newest version of FreeRTOS "manually". That means you would not tell CubeMX that you are using FreeRTOS. Just add the kernel and port files manually into your project, and then create your tasks and start the OS from a "User Code" section in main(). See LPTIM-Tick-U5 as an example. (Heads up - that example uses the port files for Cortex M33 not Cortex M0.)

[Scarittagle]

Yes, I was trying to integrate it with 10.2.1 and it does not work quite well even with the modified function. It will throw me into the hard fault when ever osDelay() related function is used.