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Copy file name to clipboardExpand all lines: chapters/appendices.tex
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@@ -186,13 +186,11 @@ \section*{Memory}
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One type of computer memory, called \emph{static RAM}, uses at least six transistors per bit. The main computer RAM is called dynamic RAM, or DRAM, and uses only one transistor and one capacitor per bit. To store one bit with 6 or more transistors is also more expensive, so SRAM is mostly used for very important memory, like the memory very close to the core of the computer processor. Have a look at Figure \ref{fig:sram}\footnote{Diagram and supporting information adapted from {\color{webblue}\href{https://en.wikipedia.org/wiki/Static_random-access_memory}{Wikipedia}} and {\color{webblue}\href{https://www.entner.net/sites/default/files/diss-entner-final-v1.pdf}{Robert Entner's dissertation}}.},
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which is pretty complicated, but if you understand how the two types of transistors are turned on and off, it will make sense. To keep this diagram simple, no resistors are shown. If you look closely at the $Q_1$/$Q_2$ and $Q_3$/$Q_4$ transistors, you can see that they are acting like inverters (that is, each pair makes a NOT gate). When WL (the ``word line") goes high, $Q_5$ and $Q_6$ open up, allowing access to the single bit stored in $BL$ and the inverse of that bit in $\overline{BL}$. Whether the word line is active (that is, whether or not you can write to the memory bit), it is possible to read the value of the bit--making SRAM very fast, because the system does not wait on the word line to activate.
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% TODO Replace this section with a complementary NOR gate flip-flop or a JK flip-flop: https://www.electronics-tutorials.ws/sequential/seq_2.html.
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% Flip-flop storage using NOR gates is better than this attempt with NOT gates. I've had trouble with the word/line controller circuit resistor values for positive clearing and setting of the gate states.
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\begin{figure}[h!]
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\begin{center}
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\input{./include/sramcell.tex}
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\caption{A static ram cell. The bit line ($BL$) on the right is the value of the bit, and the bit line on the left ($\low{BL}$) is the complement (NOT) the value of that bit.With a bit of careful circuitry, it is possible to write using only one of the bit lines, but it is safer to have two inputs (one positive, and one complement) to ensure the gates both change and lock in the value of the bit. }
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\caption{A static ram cell. The bit line ($BL$) on the right is the value of the bit, and the bit line on the left ($\low{BL}$) is the complement (NOT) the value of that bit.} %With a bit of careful circuitry, it is possible to write using only one of the bit lines, but it is safer to have two inputs (one positive, and one complement) to ensure the gates both change and lock in the value of the bit.
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\label{fig:sram}
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\end{center}
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\end{figure}
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circuit, and see how it works. As a bonus, you can construct a bit of SRAM with
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opposing NOT gates, making it fairly easy to see what is happening.
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We are going to make some SRAM using a \emph{flip-flop} circuit, made of NAND gates.
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\begin{figure}
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\begin{center}
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\input{./include/JK-flip-flop.tex}
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\caption{A gate-level schematic of one bit of memory, using a JK flip-flop circuit. Note that the two left-most NAND gates have \emph{three} inputs.}
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\end{center}
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\end{figure}
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% JK flip-flop:
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% Flip-flop storage using NOR gates is better than my previous attempt using NOT gates.
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% I had trouble with the word/line controller circuit resistor values for positive
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% clearing and setting of the gate states.
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We are going to make some SRAM using a {\color{webblue}\href{https://www.electronics-tutorials.ws/sequential/seq_2.html}{\emph{flip-flop}}} circuit, made of NAND gates.
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It uses more transistors, but it's simpler to create and this workshop already
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includes plenty of NAND gates for use. Notably, this ``JK Flip-Flip" circuit uses
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both two input NAND gates and \emph{three}-input NAND gates. It operates mostly
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the same way as a regular ``set/reset (SR) flip-flop''.
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includes plenty of NAND gates for use. Notably, this ``JK Flip-Flop" circuit uses
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two input NAND gates and also \emph{three}-input NAND gates. 3-input NAND operates mostly
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the same way as a regular NAND gate, except that the inputs
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also include the value of the Q and not-Q output lines, required to determine the output state of the gate.
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Therefore, the set- and reset- functions
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only activate when the clock signal is also high (has positive voltage on the line).
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This extra feature allows for certainty of reads and writes: it helps
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avoid rapid oscillation / instability or lock-ups should a circuit (or a third
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grader!) try to both set and reset the
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flip-flop at the same time. Furthermore, when powering up a simple SR flip-flop,
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there is no inherent guarantee of what the value would be (of course, it's
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possible to put a pull-up or pull-down resistor on the signal lines to create
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a natural ``base level'' of a set of inputs, though care must be taken to
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not accidentally create incompatible base conditions (such as accidentally setting
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both set and reset to high).
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%---------------------------
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\clearpage
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\newpage
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\section*{Why NAND Gates and NOR Gates are ``Universal"}
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%---------------------------
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It turns out that it is possible to make \emph{any} gate from NAND gates. The same is true for NOR gates. A very simple example can be seen, where we can create a NOT gate from two NOR gates.
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\input{./include/nor-to-or-gate.tex}
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%---------------------------
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\clearpage
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\newpage
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\section*{Resistor Chart}
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%---------------------------
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Resistors are marked with colored bands to make it easy to determine what resistance value they have, and how close each individual part's value is guaranteed to be to that stated value.
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Resistors are marked with colored bands to make it easy to determine what
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resistance value they have, and how close each individual part's value is
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