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Commit 8f7a15a 1 parent 353c7f1 commit 8f7a15a Copy full SHA for 8f7a15a
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src/main/scala/ee/hrzn/chryse/platform
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lines changed Original file line number Diff line number Diff line change @@ -20,5 +20,5 @@ package ee.hrzn.chryse.platform
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trait Platform {
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val id : String
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- val clockHz : Int
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+ val clockHz : BigInt
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}
Original file line number Diff line number Diff line change @@ -99,7 +99,7 @@ class ICE40Top[Top <: Module](
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clk_gb.PACKAGE_PIN := clki
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private val clk = clk_gb.GLOBAL_BUFFER_OUTPUT
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- private val timerLimit = (15e-6 * platform.clockHz).toInt
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+ private val timerLimit = (15 * platform.clockHz / 1_000_000 ).toInt
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private val resetTimerReg =
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withClock(clk)(Reg (UInt (unsignedBitLength(timerLimit).W )))
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private val reset = Wire (Bool ())
Original file line number Diff line number Diff line change @@ -20,8 +20,8 @@ package ee.hrzn.chryse.platform.resource
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import chisel3 ._
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- case class ClockSource (hz : Int ) extends ResourceData (Input (Clock ())) {}
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+ case class ClockSource (hz : BigInt ) extends ResourceData (Input (Clock ())) {}
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object ClockSource {
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- def apply (hz : Int ) = new ClockSource (hz)
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+ def apply (hz : BigInt ) = new ClockSource (hz)
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}
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