|
| 1 | +/* |
| 2 | + * QEMU RX CPU |
| 3 | + * |
| 4 | + * Copyright (c) 2019 Yoshinori Sato |
| 5 | + * |
| 6 | + * This program is free software; you can redistribute it and/or modify it |
| 7 | + * under the terms and conditions of the GNU General Public License, |
| 8 | + * version 2 or later, as published by the Free Software Foundation. |
| 9 | + * |
| 10 | + * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | + * more details. |
| 14 | + * |
| 15 | + * You should have received a copy of the GNU General Public License along with |
| 16 | + * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | + */ |
| 18 | + |
| 19 | +#include "qemu/osdep.h" |
| 20 | +#include "qemu/qemu-print.h" |
| 21 | +#include "qapi/error.h" |
| 22 | +#include "cpu.h" |
| 23 | +#include "qemu-common.h" |
| 24 | +#include "migration/vmstate.h" |
| 25 | +#include "exec/exec-all.h" |
| 26 | +#include "hw/loader.h" |
| 27 | +#include "fpu/softfloat.h" |
| 28 | + |
| 29 | +static void rx_cpu_set_pc(CPUState *cs, vaddr value) |
| 30 | +{ |
| 31 | + RXCPU *cpu = RXCPU(cs); |
| 32 | + |
| 33 | + cpu->env.pc = value; |
| 34 | +} |
| 35 | + |
| 36 | +static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
| 37 | +{ |
| 38 | + RXCPU *cpu = RXCPU(cs); |
| 39 | + |
| 40 | + cpu->env.pc = tb->pc; |
| 41 | +} |
| 42 | + |
| 43 | +static bool rx_cpu_has_work(CPUState *cs) |
| 44 | +{ |
| 45 | + return cs->interrupt_request & |
| 46 | + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); |
| 47 | +} |
| 48 | + |
| 49 | +static void rx_cpu_reset(DeviceState *dev) |
| 50 | +{ |
| 51 | + RXCPU *cpu = RXCPU(dev); |
| 52 | + RXCPUClass *rcc = RXCPU_GET_CLASS(cpu); |
| 53 | + CPURXState *env = &cpu->env; |
| 54 | + uint32_t *resetvec; |
| 55 | + |
| 56 | + rcc->parent_reset(dev); |
| 57 | + |
| 58 | + memset(env, 0, offsetof(CPURXState, end_reset_fields)); |
| 59 | + |
| 60 | + resetvec = rom_ptr(0xfffffffc, 4); |
| 61 | + if (resetvec) { |
| 62 | + /* In the case of kernel, it is ignored because it is not set. */ |
| 63 | + env->pc = ldl_p(resetvec); |
| 64 | + } |
| 65 | + rx_cpu_unpack_psw(env, 0, 1); |
| 66 | + env->regs[0] = env->isp = env->usp = 0; |
| 67 | + env->fpsw = 0; |
| 68 | + set_flush_to_zero(1, &env->fp_status); |
| 69 | + set_flush_inputs_to_zero(1, &env->fp_status); |
| 70 | +} |
| 71 | + |
| 72 | +static void rx_cpu_list_entry(gpointer data, gpointer user_data) |
| 73 | +{ |
| 74 | + ObjectClass *oc = data; |
| 75 | + |
| 76 | + qemu_printf(" %s\n", object_class_get_name(oc)); |
| 77 | +} |
| 78 | + |
| 79 | +void rx_cpu_list(void) |
| 80 | +{ |
| 81 | + GSList *list; |
| 82 | + list = object_class_get_list_sorted(TYPE_RX_CPU, false); |
| 83 | + qemu_printf("Available CPUs:\n"); |
| 84 | + g_slist_foreach(list, rx_cpu_list_entry, NULL); |
| 85 | + g_slist_free(list); |
| 86 | +} |
| 87 | + |
| 88 | +static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) |
| 89 | +{ |
| 90 | + ObjectClass *oc; |
| 91 | + char *typename; |
| 92 | + |
| 93 | + oc = object_class_by_name(cpu_model); |
| 94 | + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL && |
| 95 | + !object_class_is_abstract(oc)) { |
| 96 | + return oc; |
| 97 | + } |
| 98 | + typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); |
| 99 | + oc = object_class_by_name(typename); |
| 100 | + g_free(typename); |
| 101 | + if (oc != NULL && object_class_is_abstract(oc)) { |
| 102 | + oc = NULL; |
| 103 | + } |
| 104 | + |
| 105 | + return oc; |
| 106 | +} |
| 107 | + |
| 108 | +static void rx_cpu_realize(DeviceState *dev, Error **errp) |
| 109 | +{ |
| 110 | + CPUState *cs = CPU(dev); |
| 111 | + RXCPUClass *rcc = RXCPU_GET_CLASS(dev); |
| 112 | + Error *local_err = NULL; |
| 113 | + |
| 114 | + cpu_exec_realizefn(cs, &local_err); |
| 115 | + if (local_err != NULL) { |
| 116 | + error_propagate(errp, local_err); |
| 117 | + return; |
| 118 | + } |
| 119 | + |
| 120 | + qemu_init_vcpu(cs); |
| 121 | + cpu_reset(cs); |
| 122 | + |
| 123 | + rcc->parent_realize(dev, errp); |
| 124 | +} |
| 125 | + |
| 126 | +static void rx_cpu_set_irq(void *opaque, int no, int request) |
| 127 | +{ |
| 128 | + RXCPU *cpu = opaque; |
| 129 | + CPUState *cs = CPU(cpu); |
| 130 | + int irq = request & 0xff; |
| 131 | + |
| 132 | + static const int mask[] = { |
| 133 | + [RX_CPU_IRQ] = CPU_INTERRUPT_HARD, |
| 134 | + [RX_CPU_FIR] = CPU_INTERRUPT_FIR, |
| 135 | + }; |
| 136 | + if (irq) { |
| 137 | + cpu->env.req_irq = irq; |
| 138 | + cpu->env.req_ipl = (request >> 8) & 0x0f; |
| 139 | + cpu_interrupt(cs, mask[no]); |
| 140 | + } else { |
| 141 | + cpu_reset_interrupt(cs, mask[no]); |
| 142 | + } |
| 143 | +} |
| 144 | + |
| 145 | +static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
| 146 | +{ |
| 147 | + info->mach = bfd_mach_rx; |
| 148 | + info->print_insn = print_insn_rx; |
| 149 | +} |
| 150 | + |
| 151 | +static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, |
| 152 | + MMUAccessType access_type, int mmu_idx, |
| 153 | + bool probe, uintptr_t retaddr) |
| 154 | +{ |
| 155 | + uint32_t address, physical, prot; |
| 156 | + |
| 157 | + /* Linear mapping */ |
| 158 | + address = physical = addr & TARGET_PAGE_MASK; |
| 159 | + prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 160 | + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); |
| 161 | + return true; |
| 162 | +} |
| 163 | + |
| 164 | +static void rx_cpu_init(Object *obj) |
| 165 | +{ |
| 166 | + CPUState *cs = CPU(obj); |
| 167 | + RXCPU *cpu = RXCPU(obj); |
| 168 | + CPURXState *env = &cpu->env; |
| 169 | + |
| 170 | + cpu_set_cpustate_pointers(cpu); |
| 171 | + cs->env_ptr = env; |
| 172 | + qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); |
| 173 | +} |
| 174 | + |
| 175 | +static void rx_cpu_class_init(ObjectClass *klass, void *data) |
| 176 | +{ |
| 177 | + DeviceClass *dc = DEVICE_CLASS(klass); |
| 178 | + CPUClass *cc = CPU_CLASS(klass); |
| 179 | + RXCPUClass *rcc = RXCPU_CLASS(klass); |
| 180 | + |
| 181 | + device_class_set_parent_realize(dc, rx_cpu_realize, |
| 182 | + &rcc->parent_realize); |
| 183 | + device_class_set_parent_reset(dc, rx_cpu_reset, |
| 184 | + &rcc->parent_reset); |
| 185 | + |
| 186 | + cc->class_by_name = rx_cpu_class_by_name; |
| 187 | + cc->has_work = rx_cpu_has_work; |
| 188 | + cc->do_interrupt = rx_cpu_do_interrupt; |
| 189 | + cc->cpu_exec_interrupt = rx_cpu_exec_interrupt; |
| 190 | + cc->dump_state = rx_cpu_dump_state; |
| 191 | + cc->set_pc = rx_cpu_set_pc; |
| 192 | + cc->synchronize_from_tb = rx_cpu_synchronize_from_tb; |
| 193 | + cc->gdb_read_register = rx_cpu_gdb_read_register; |
| 194 | + cc->gdb_write_register = rx_cpu_gdb_write_register; |
| 195 | + cc->get_phys_page_debug = rx_cpu_get_phys_page_debug; |
| 196 | + cc->disas_set_info = rx_cpu_disas_set_info; |
| 197 | + cc->tcg_initialize = rx_translate_init; |
| 198 | + cc->tlb_fill = rx_cpu_tlb_fill; |
| 199 | + |
| 200 | + cc->gdb_num_core_regs = 26; |
| 201 | + cc->gdb_core_xml_file = "rx-core.xml"; |
| 202 | +} |
| 203 | + |
| 204 | +static const TypeInfo rx_cpu_info = { |
| 205 | + .name = TYPE_RX_CPU, |
| 206 | + .parent = TYPE_CPU, |
| 207 | + .instance_size = sizeof(RXCPU), |
| 208 | + .instance_init = rx_cpu_init, |
| 209 | + .abstract = true, |
| 210 | + .class_size = sizeof(RXCPUClass), |
| 211 | + .class_init = rx_cpu_class_init, |
| 212 | +}; |
| 213 | + |
| 214 | +static const TypeInfo rx62n_rx_cpu_info = { |
| 215 | + .name = TYPE_RX62N_CPU, |
| 216 | + .parent = TYPE_RX_CPU, |
| 217 | +}; |
| 218 | + |
| 219 | +static void rx_cpu_register_types(void) |
| 220 | +{ |
| 221 | + type_register_static(&rx_cpu_info); |
| 222 | + type_register_static(&rx62n_rx_cpu_info); |
| 223 | +} |
| 224 | + |
| 225 | +type_init(rx_cpu_register_types) |
0 commit comments