Merge pull request #1696 from Bastian-Krause/bst/waveshare-fixes

WaveShare Modbus Fixes

Author: Emantor

doc/configuration.rst

@@ -446,14 +446,15 @@ A :any:`WaveshareModbusTCPCoil` describes a Waveshare branded coil accessible vi
    WaveshareModbusTCPCoil:
      host: '192.168.23.42'
      coil: 1
-     coil_count: 8 
+     coil_count: 8
 
 The example describes the coil ``1`` (zero indexed) of ``8`` on the Waveshare Modbus TCP relay
 module ``192.168.23.42``.
 
 Arguments:
   - host (str): hostname of the Modbus TCP server e.g. ``192.168.23.42:502``
   - coil (int): index of the coil, e.g. ``3``
+  - coil_count (int, default=8): total number of coils on this module
   - invert (bool, default=False): whether the logic level is inverted
     (active-low)
   - write_multiple_coils (bool, default=False): whether to perform write
@@ -462,7 +463,6 @@ Arguments:
 Used by:
   - `WaveShareModbusCoilDriver`_
 
-
 DeditecRelais8
 ++++++++++++++
 A :any:`DeditecRelais8` describes a *Deditec USB GPO module* with 8 relays.

labgrid/driver/__init__.py

@@ -21,7 +21,7 @@
 from .usbsdwiredriver import USBSDWireDriver
 from .common import Driver
 from .qemudriver import QEMUDriver
-from .modbusdriver import ModbusCoilDriver
+from .modbusdriver import ModbusCoilDriver, WaveShareModbusCoilDriver
 from .modbusrtudriver import ModbusRTUDriver
 from .sigrokdriver import SigrokDriver, SigrokPowerDriver, SigrokDmmDriver
 from .usbstoragedriver import USBStorageDriver, Mode