From f9d3705c876ece9bbbc9ea48a191426b9ee2ddde Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 25 Aug 2025 13:58:19 +0000 Subject: [PATCH 1/2] fel: add support for Allwinner A733 The Allwinner A733 is built on a 12nm process and features a dual-core ARM Cortex-A76 combined with a hexa-core ARM Cortex-A55 using the big.LITTLE architecture. The chip has 16K + 192K of SRAM-A2, with first 16K used only by CPUS domain, later it follows by 512K of SHARED-SRAM with no gaps. SRAM_A2 0x40000 - 0x73FFF SHARED_SRAM 0x74000 - 0xF3FFF The BootROM SRAM usage is similar to other SoCs: there is the IRQ stack growing down from around 34K offset in SRAM-A2, and probably some buffers located towards the end of the SRAM. In this setup, we've only tried to use the 192K block of SRAM-A2, which should be enough for SPL setup. It's possible to use more SRAM, for example, the SHARED-SRAM, but we leave it for now. This setup is known to boot the WIP mainline U-Boot setup, including some placeholder TF-A port for now. SPL execution, including returning back to the BROM, works, also the 64-bit switch, as well as the SID dump. Signed-off-by: Yixun Lan --- soc_info.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/soc_info.c b/soc_info.c index 4cb6bcc44..c2ec5c7b5 100644 --- a/soc_info.c +++ b/soc_info.c @@ -189,6 +189,12 @@ sram_swap_buffers a523_sram_swap_buffers[] = { { .buf1 = 0x45000, .buf2 = 0x40200, .size = 0x0400 }, { .size = 0 } /* End of the table */ }; + +sram_swap_buffers a733_sram_swap_buffers[] = { + { .buf1 = 0x47000, .buf2 = 0x72400, .size = 0x1C00 }, + { .size = 0 } /* End of the table */ +}; + /* * Some SoCs put both stacks, BSS and data segments at the end of a comparably * large SRAM, so we don't need to move anything around. @@ -642,6 +648,20 @@ soc_info_t soc_info_table[] = { .rvbar_reg = 0x08100040, .needs_smc_workaround_if_zero_word_at_addr = 0x100004, .watchdog = &wd_h6_compat, + },{ + .soc_id = 0x1903, /* Allwinner A733 */ + .name = "A733", + .spl_addr = 0x47000, + .scratch_addr = 0x71000, + .thunk_addr = 0x72000, .thunk_size = 0x200, + .swap_buffers = a733_sram_swap_buffers, + .sram_size = 180 * 1024, + .sid_base = 0x03006000, + .sid_offset = 0x200, + .sid_sections = generic_2k_sid_maps, + .rvbar_reg = 0x08001004, + .icache_fix = true, + .watchdog = &wd_a523_compat, },{ .swap_buffers = NULL /* End of the table */ } From 5d996736a41f975245bd6a22d8d4c3cf044fb38a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 25 Aug 2025 14:37:53 +0000 Subject: [PATCH 2/2] uart0-helloworld-sdboot: add support for Allwinner A733 Enable UART's pinctrl and clock settings. The clock and pio offset for UART controller is changed in A733. Signed-off-by: Yixun Lan --- uart0-helloworld-sdboot.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c index f6440184c..f11c800f5 100644 --- a/uart0-helloworld-sdboot.c +++ b/uart0-helloworld-sdboot.c @@ -80,6 +80,7 @@ typedef unsigned char u8; #define R329_UART0_BASE 0x02500000 #define R329_PIO_BASE 0x02000400 #define R329_CCM_BASE 0x02001000 +#define A733_CCM_BASE 0x02002000 #define V853_PIO_BASE 0x02000000 @@ -175,8 +176,11 @@ enum sunxi_gpio_number { #define FLAG_NEW_CLOCK BIT(3) #define FLAG_UART_ON_APB1 BIT(4) #define FLAG_A80_CLOCK BIT(5) +#define FLAG_A733_GPIO BIT(6) +#define FLAG_A733_CLOCK BIT(7) #define FLAG_NCAT2 FLAG_NEW_GPIO | FLAG_NEW_CLOCK +#define FLAG_NCAT3 FLAG_A733_GPIO | FLAG_A733_CLOCK static const struct soc_info { u16 soc_id; @@ -239,6 +243,8 @@ static const struct soc_info { R329_UART0_BASE, SUNXI_GPH(9), MUX_5, FLAG_NCAT2 }, { 0x1890, "A523", V853_PIO_BASE, R329_CCM_BASE, SRAM_A1_ADDR_20000, R329_UART0_BASE, SUNXI_GPB(9), MUX_2, FLAG_NCAT2 }, + { 0x1903, "A733", V853_PIO_BASE, A733_CCM_BASE, SRAM_A1_ADDR_20000, + R329_UART0_BASE, SUNXI_GPB(9), MUX_2, FLAG_NCAT3 }, }; #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) @@ -259,6 +265,7 @@ static const struct soc_info *find_soc_info(int soc_id, int variant) } static u32 pio_base; +static u32 pio_bank_a_offset; static u32 pio_bank_size, pio_dat_off, pio_pull_off; static int sunxi_gpio_set_cfgpin(u32 pin, u32 val) @@ -411,6 +418,9 @@ static void clock_init_uart(const struct soc_info *soc) if (soc->flags & FLAG_NEW_CLOCK) { set_wbit(soc->ccu_base + 0x90c, 0x10001 << (CONFIG_CONS_INDEX - 1)); + } else if (soc->flags & FLAG_A733_CLOCK) { + set_wbit(soc->ccu_base + 0xe00 + (CONFIG_CONS_INDEX - 1) * 4, + 0x10001); } else { int bit = 16 + CONFIG_CONS_INDEX - 1; int gate_ofs = 0x06c; @@ -439,13 +449,17 @@ static void clock_init_uart(const struct soc_info *soc) static void gpio_init(const struct soc_info *soc) { - pio_base = soc->pio_base; - if (soc->flags & FLAG_NEW_GPIO) { /* GPIO V2 */ pio_bank_size = 0x30; pio_dat_off = 0x10; pio_pull_off = 0x24; + } else if (soc->flags & FLAG_A733_GPIO) { + /* Bank A Offset = 0x80 */ + pio_bank_a_offset = 0x80; + pio_bank_size = 0x80; + pio_dat_off = 0x10; + pio_pull_off = 0x30; } else { /* GPIO V1 */ pio_bank_size = 0x24; @@ -453,6 +467,8 @@ static void gpio_init(const struct soc_info *soc) pio_pull_off = 0x1c; } + pio_base = soc->pio_base + pio_bank_a_offset; + if (soc->flags & FLAG_UART_ON_PORTF) { /* Disable normal UART0 pins to avoid conflict */ sunxi_gpio_set_cfgpin(soc->uart0_tx_pin, MUX_GPIO_INPUT);