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Merge tag 'char-misc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH: "Here is the big set of new char/misc driver drivers and features for 4.12-rc1. There's lots of new drivers added this time around, new firmware drivers from Google, more auxdisplay drivers, extcon drivers, fpga drivers, and a bunch of other driver updates. Nothing major, except if you happen to have the hardware for these drivers, and then you will be happy :) All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (136 commits) firmware: google memconsole: Fix return value check in platform_memconsole_init() firmware: Google VPD: Fix return value check in vpd_platform_init() goldfish_pipe: fix build warning about using too much stack. goldfish_pipe: An implementation of more parallel pipe fpga fr br: update supported version numbers fpga: region: release FPGA region reference in error path fpga altera-hps2fpga: disable/unprepare clock on error in alt_fpga_bridge_probe() mei: drop the TODO from samples firmware: Google VPD sysfs driver firmware: Google VPD: import lib_vpd source files misc: lkdtm: Add volatile to intentional NULL pointer reference eeprom: idt_89hpesx: Add OF device ID table misc: ds1682: Add OF device ID table misc: tsl2550: Add OF device ID table w1: Remove unneeded use of assert() and remove w1_log.h w1: Use kernel common min() implementation uio_mf624: Align memory regions to page size and set correct offsets uio_mf624: Refactor memory info initialization uio: Allow handling of non page-aligned memory regions hangcheck-timer: Fix typo in comment ...
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‎Documentation/DocBook/rapidio.tmpl

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@@ -128,9 +128,6 @@
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</sect1>
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<sect1 id="Device_model_support"><title>Device model support</title>
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!Idrivers/rapidio/rio-driver.c
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</sect1>
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<sect1 id="Sysfs_support"><title>Sysfs support</title>
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!Idrivers/rapidio/rio-sysfs.c
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</sect1>
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<sect1 id="PPC32_support"><title>PPC32 support</title>
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!Iarch/powerpc/sysdev/fsl_rio.c

‎Documentation/devicetree/bindings/auxdisplay/hit,hd44780.txt

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DT bindings for the Hitachi HD44780 Character LCD Controller
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The Hitachi HD44780 Character LCD Controller is commonly used on character LCDs
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that can display one or more lines of text. It exposes an M6800 bus interface,
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which can be used in either 4-bit or 8-bit mode.
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Required properties:
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- compatible: Must contain "hit,hd44780",
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- data-gpios: Must contain an array of either 4 or 8 GPIO specifiers,
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referring to the GPIO pins connected to the data signal lines DB0-DB7
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(8-bit mode) or DB4-DB7 (4-bit mode) of the LCD Controller's bus interface,
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- enable-gpios: Must contain a GPIO specifier, referring to the GPIO pin
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connected to the "E" (Enable) signal line of the LCD Controller's bus
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interface,
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- rs-gpios: Must contain a GPIO specifier, referring to the GPIO pin
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connected to the "RS" (Register Select) signal line of the LCD Controller's
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bus interface,
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- display-height-chars: Height of the display, in character cells,
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- display-width-chars: Width of the display, in character cells.
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Optional properties:
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- rw-gpios: Must contain a GPIO specifier, referring to the GPIO pin
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connected to the "RW" (Read/Write) signal line of the LCD Controller's bus
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interface,
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- backlight-gpios: Must contain a GPIO specifier, referring to the GPIO pin
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used for enabling the LCD's backlight,
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- internal-buffer-width: Internal buffer width (default is 40 for displays
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with 1 or 2 lines, and display-width-chars for displays with more than 2
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lines).
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Example:
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auxdisplay {
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compatible = "hit,hd44780";
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data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
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<&hc595 1 GPIO_ACTIVE_HIGH>,
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<&hc595 2 GPIO_ACTIVE_HIGH>,
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<&hc595 3 GPIO_ACTIVE_HIGH>;
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enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
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rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
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display-height-chars = <2>;
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display-width-chars = <16>;
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};

‎Documentation/devicetree/bindings/firmware/coreboot.txt

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COREBOOT firmware information
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The device tree node to communicate the location of coreboot's memory-resident
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bookkeeping structures to the kernel. Since coreboot itself cannot boot a
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device-tree-based kernel (yet), this node needs to be inserted by a
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second-stage bootloader (a coreboot "payload").
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Required properties:
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- compatible: Should be "coreboot"
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- reg: Address and length of the following two memory regions, in order:
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1.) The coreboot table. This is a list of variable-sized descriptors
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that contain various compile- and run-time generated firmware
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parameters. It is identified by the magic string "LBIO" in its first
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four bytes.
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See coreboot's src/commonlib/include/commonlib/coreboot_tables.h for
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details.
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2.) The CBMEM area. This is a downward-growing memory region used by
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coreboot to dynamically allocate data structures that remain resident.
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It may or may not include the coreboot table as one of its members. It
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is identified by a root node descriptor with the magic number
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0xc0389481 that resides in the topmost 8 bytes of the area.
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See coreboot's src/include/imd.h for details.
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Example:
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firmware {
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ranges;
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coreboot {
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compatible = "coreboot";
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reg = <0xfdfea000 0x264>,
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<0xfdfea000 0x16000>;
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}
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};

‎Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

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Altera Arria10 Partial Reconfiguration IP
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Required properties:
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- compatible : should contain "altr,a10-pr-ip"
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- reg : base address and size for memory mapped io.
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Example:
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fpga_mgr: fpga-mgr@ff20c000 {
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compatible = "altr,a10-pr-ip";
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reg = <0xff20c000 0x10>;
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};

‎Documentation/devicetree/bindings/fpga/fpga-region.txt

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@@ -186,6 +186,7 @@ Optional properties:
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otherwise full reconfiguration is done.
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- external-fpga-config : boolean, set if the FPGA has already been configured
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prior to OS boot up.
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- encrypted-fpga-config : boolean, set if the bitstream is encrypted
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- region-unfreeze-timeout-us : The maximum time in microseconds to wait for
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bridges to successfully become enabled after the region has been
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programmed.

‎Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt

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Lattice iCE40 FPGA Manager
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Required properties:
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- compatible: Should contain "lattice,ice40-fpga-mgr"
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- reg: SPI chip select
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- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
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- cdone-gpios: GPIO input connected to CDONE pin
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- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
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that unless the GPIO is held low during startup, the
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FPGA will enter Master SPI mode and drive SCK with a
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clock signal potentially jamming other devices on the
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bus until the firmware is loaded.
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Example:
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fpga: fpga@0 {
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compatible = "lattice,ice40-fpga-mgr";
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reg = <0>;
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spi-max-frequency = <1000000>;
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cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
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};

‎Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt

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Xilinx Slave Serial SPI FPGA Manager
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Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
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what is referred to as "slave serial" interface.
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The slave serial link is not technically SPI, and might require extra
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circuits in order to play nicely with other SPI slaves on the same bus.
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See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
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Required properties:
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- compatible: should contain "xlnx,fpga-slave-serial"
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- reg: spi chip select of the FPGA
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- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
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- done-gpios: config status pin (referred to as DONE in the manual)
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Example for full FPGA configuration:
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fpga-region0 {
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compatible = "fpga-region";
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fpga-mgr = <&fpga_mgr_spi>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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};
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spi1: spi@10680 {
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compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "okay";
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fpga_mgr_spi: fpga-mgr@0 {
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compatible = "xlnx,fpga-slave-serial";
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spi-max-frequency = <60000000>;
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spi-cpha;
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reg = <0>;
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done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
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};
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};

‎Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt

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Allwinner sunxi-sid
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Required properties:
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- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid"
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- compatible: Should be one of the following:
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"allwinner,sun4i-a10-sid"
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"allwinner,sun7i-a20-sid"
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"allwinner,sun8i-h3-sid"
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- reg: Should contain registers location and length
610

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= Data cells =

‎Documentation/devicetree/bindings/nvmem/imx-iim.txt

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Freescale i.MX IC Identification Module (IIM) device tree bindings
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This binding represents the IC Identification Module (IIM) found on
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i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs.
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Required properties:
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- compatible: should be one of
8+
"fsl,imx25-iim", "fsl,imx27-iim",
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"fsl,imx31-iim", "fsl,imx35-iim",
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"fsl,imx51-iim", "fsl,imx53-iim",
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- reg: Should contain the register base and length.
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- interrupts: Should contain the interrupt for the IIM
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- clocks: Should contain a phandle pointing to the gated peripheral clock.
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Example:
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iim: iim@63f98000 {
18+
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
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reg = <0x63f98000 0x4000>;
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interrupts = <69>;
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clocks = <&clks IMX5_CLK_IIM_GATE>;
22+
};

‎Documentation/devicetree/bindings/nvmem/imx-ocotp.txt

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"fsl,imx6sl-ocotp" (i.MX6SL), or
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"fsl,imx6sx-ocotp" (i.MX6SX),
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"fsl,imx6ul-ocotp" (i.MX6UL),
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"fsl,imx7d-ocotp" (i.MX7D/S),
1213
followed by "syscon".
1314
- reg: Should contain the register base and length.
1415
- clocks: Should contain a phandle pointing to the gated peripheral clock.
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17+
Optional properties:
18+
- read-only: disable write access
19+
1620
Example:
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1822
ocotp: ocotp@021bc000 {
1923
compatible = "fsl,imx6q-ocotp", "syscon";
2024
reg = <0x021bc000 0x4000>;
2125
clocks = <&clks IMX6QDL_CLK_IIM>;
26+
read-only;
2227
};

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