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harlanhaskinsharlanhaskins
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Changed OpCode to use an explicit initializer rather than using raw values from the enum (#68)
1 parent 01505c7 commit 1eeef5a

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2 files changed

+137
-69
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‎Sources/LLVM/Instruction.swift

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ public struct Instruction: IRValue {
1818

1919
/// Retrieves the opcode associated with this `Instruction`.
2020
public var opCode: OpCode {
21-
return OpCode(rawValue: LLVMGetInstructionOpcode(llvm).rawValue)!
21+
return OpCode(rawValue: LLVMGetInstructionOpcode(llvm))
2222
}
2323

2424
/// Obtain the instruction that occurs before this one, if it exists.

‎Sources/LLVM/OpCode.swift

Lines changed: 136 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -3,159 +3,227 @@ import cllvm
33
#endif
44

55
/// Enumerates the opcodes of instructions available in the LLVM IR language.
6-
///
7-
/// The raw values of this enumeration *must* match those in
8-
/// [llvm-c/Core.h](https://github.com/llvm-mirror/llvm/blob/master/include/llvm-c/Core.h)
9-
public enum OpCode: UInt32 {
6+
public enum OpCode {
107
// MARK: Terminator Instructions
118

129
/// The opcode for the `ret` instruction.
13-
case ret = 1
10+
case ret
1411
/// The opcode for the `br` instruction.
15-
case br = 2
12+
case br
1613
/// The opcode for the `switch` instruction.
17-
case `switch` = 3
14+
case `switch`
1815
/// The opcode for the `indirectBr` instruction.
19-
case indirectBr = 4
16+
case indirectBr
2017
/// The opcode for the `invoke` instruction.
21-
case invoke = 5
18+
case invoke
2219
/// The opcode for the `unreachable` instruction.
23-
case unreachable = 7
20+
case unreachable
2421

2522
// MARK: Standard Binary Operators
2623

2724
/// The opcode for the `add` instruction.
28-
case add = 8
25+
case add
2926
/// The opcode for the `fadd` instruction.
30-
case fadd = 9
27+
case fadd
3128
/// The opcode for the `sub` instruction.
32-
case sub = 10
29+
case sub
3330
/// The opcode for the `fsub` instruction.
34-
case fsub = 11
31+
case fsub
3532
/// The opcode for the `mul` instruction.
36-
case mul = 12
33+
case mul
3734
/// The opcode for the `fmul` instruction.
38-
case fmul = 13
35+
case fmul
3936
/// The opcode for the `udiv` instruction.
40-
case udiv = 14
37+
case udiv
4138
/// The opcode for the `sdiv` instruction.
42-
case sdiv = 15
39+
case sdiv
4340
/// The opcode for the `fdiv` instruction.
44-
case fdiv = 16
41+
case fdiv
4542
/// The opcode for the `urem` instruction.
46-
case urem = 17
43+
case urem
4744
/// The opcode for the `srem` instruction.
48-
case srem = 18
45+
case srem
4946
/// The opcode for the `frem` instruction.
50-
case frem = 19
47+
case frem
5148

5249
// MARK: Logical Operators
5350

5451
/// The opcode for the `shl` instruction.
55-
case shl = 20
52+
case shl
5653
/// The opcode for the `lshr` instruction.
57-
case lshr = 21
54+
case lshr
5855
/// The opcode for the `ashr` instruction.
59-
case ashr = 22
56+
case ashr
6057
/// The opcode for the `and` instruction.
61-
case and = 23
58+
case and
6259
/// The opcode for the `or` instruction.
63-
case or = 24
60+
case or
6461
/// The opcode for the `xor` instruction.
65-
case xor = 25
62+
case xor
6663

6764
// MARK: Memory Operators
6865

6966
/// The opcode for the `alloca` instruction.
70-
case alloca = 26
67+
case alloca
7168
/// The opcode for the `load` instruction.
72-
case load = 27
69+
case load
7370
/// The opcode for the `store` instruction.
74-
case store = 28
71+
case store
7572
/// The opcode for the `getElementPtr` instruction.
76-
case getElementPtr = 29
73+
case getElementPtr
7774

7875
// MARK: Cast Operators
7976

8077
/// The opcode for the `trunc` instruction.
81-
case trunc = 30
78+
case trunc
8279
/// The opcode for the `zext` instruction.
83-
case zext = 31
80+
case zext
8481
/// The opcode for the `sext` instruction.
85-
case sext = 32
82+
case sext
8683
/// The opcode for the `fpToUI` instruction.
87-
case fpToUI = 33
84+
case fpToUI
8885
/// The opcode for the `fpToSI` instruction.
89-
case fpToSI = 34
86+
case fpToSI
9087
/// The opcode for the `uiToFP` instruction.
91-
case uiToFP = 35
88+
case uiToFP
9289
/// The opcode for the `siToFP` instruction.
93-
case siToFP = 36
90+
case siToFP
9491
/// The opcode for the `fpTrunc` instruction.
95-
case fpTrunc = 37
92+
case fpTrunc
9693
/// The opcode for the `fpExt` instruction.
97-
case fpExt = 38
94+
case fpExt
9895
/// The opcode for the `ptrToInt` instruction.
99-
case ptrToInt = 39
96+
case ptrToInt
10097
/// The opcode for the `intToPtr` instruction.
101-
case intToPtr = 40
98+
case intToPtr
10299
/// The opcode for the `bitCast` instruction.
103-
case bitCast = 41
100+
case bitCast
104101
/// The opcode for the `addrSpaceCast` instruction.
105-
case addrSpaceCast = 60
102+
case addrSpaceCast
106103

107104
// MARK: Other Operators
108105

109106
/// The opcode for the `icmp` instruction.
110-
case icmp = 42
107+
case icmp
111108
/// The opcode for the `fcmp` instruction.
112-
case fcmp = 43
109+
case fcmp
113110
/// The opcode for the `PHI` instruction.
114-
case PHI = 44
111+
case phi
115112
/// The opcode for the `call` instruction.
116-
case call = 45
113+
case call
117114
/// The opcode for the `select` instruction.
118-
case select = 46
115+
case select
119116
/// The opcode for the `userOp1` instruction.
120-
case userOp1 = 47
117+
case userOp1
121118
/// The opcode for the `userOp2` instruction.
122-
case userOp2 = 48
119+
case userOp2
123120
/// The opcode for the `vaArg` instruction.
124-
case vaArg = 49
121+
case vaArg
125122
/// The opcode for the `extractElement` instruction.
126-
case extractElement = 50
123+
case extractElement
127124
/// The opcode for the `insertElement` instruction.
128-
case insertElement = 51
125+
case insertElement
129126
/// The opcode for the `shuffleVector` instruction.
130-
case shuffleVector = 52
127+
case shuffleVector
131128
/// The opcode for the `extractValue` instruction.
132-
case extractValue = 53
129+
case extractValue
133130
/// The opcode for the `insertValue` instruction.
134-
case insertValue = 54
131+
case insertValue
135132

136133
// MARK: Atomic operators
137134

138135
/// The opcode for the `fence` instruction.
139-
case fence = 55
136+
case fence
140137
/// The opcode for the `atomicCmpXchg` instruction.
141-
case atomicCmpXchg = 56
138+
case atomicCmpXchg
142139
/// The opcode for the `atomicRMW` instruction.
143-
case atomicRMW = 57
140+
case atomicRMW
144141

145142
// MARK: Exception Handling Operators
146143

147144
/// The opcode for the `resume` instruction.
148-
case resume = 58
145+
case resume
149146
/// The opcode for the `landingPad` instruction.
150-
case landingPad = 59
147+
case landingPad
151148
/// The opcode for the `cleanupRet` instruction.
152-
case cleanupRet = 61
149+
case cleanupRet
153150
/// The opcode for the `catchRet` instruction.
154-
case catchRet = 62
151+
case catchRet
155152
/// The opcode for the `catchPad` instruction.
156-
case catchPad = 63
153+
case catchPad
157154
/// The opcode for the `cleanupPad` instruction.
158-
case cleanupPad = 64
155+
case cleanupPad
159156
/// The opcode for the `catchSwitch` instruction.
160-
case catchSwitch = 65
157+
case catchSwitch
158+
159+
/// Creates an `OpCode` from an `LLVMOpcode`
160+
init(rawValue: LLVMOpcode) {
161+
switch rawValue {
162+
case LLVMRet: self = .ret
163+
case LLVMBr: self = .br
164+
case LLVMSwitch: self = .switch
165+
case LLVMIndirectBr: self = .indirectBr
166+
case LLVMInvoke: self = .invoke
167+
case LLVMUnreachable: self = .unreachable
168+
case LLVMAdd: self = .add
169+
case LLVMFAdd: self = .fadd
170+
case LLVMSub: self = .sub
171+
case LLVMFSub: self = .fsub
172+
case LLVMMul: self = .mul
173+
case LLVMFMul: self = .fmul
174+
case LLVMUDiv: self = .udiv
175+
case LLVMSDiv: self = .sdiv
176+
case LLVMFDiv: self = .fdiv
177+
case LLVMURem: self = .urem
178+
case LLVMSRem: self = .srem
179+
case LLVMFRem: self = .frem
180+
case LLVMShl: self = .shl
181+
case LLVMLShr: self = .lshr
182+
case LLVMAShr: self = .ashr
183+
case LLVMAnd: self = .and
184+
case LLVMOr: self = .or
185+
case LLVMXor: self = .xor
186+
case LLVMAlloca: self = .alloca
187+
case LLVMLoad: self = .load
188+
case LLVMStore: self = .store
189+
case LLVMGetElementPtr: self = .getElementPtr
190+
case LLVMTrunc: self = .trunc
191+
case LLVMZExt: self = .zext
192+
case LLVMSExt: self = .sext
193+
case LLVMFPToUI: self = .fpToUI
194+
case LLVMFPToSI: self = .fpToSI
195+
case LLVMUIToFP: self = .uiToFP
196+
case LLVMSIToFP: self = .siToFP
197+
case LLVMFPTrunc: self = .fpTrunc
198+
case LLVMFPExt: self = .fpExt
199+
case LLVMPtrToInt: self = .ptrToInt
200+
case LLVMIntToPtr: self = .intToPtr
201+
case LLVMBitCast: self = .bitCast
202+
case LLVMAddrSpaceCast: self = .addrSpaceCast
203+
case LLVMICmp: self = .icmp
204+
case LLVMFCmp: self = .fcmp
205+
case LLVMPHI: self = .phi
206+
case LLVMCall: self = .call
207+
case LLVMSelect: self = .select
208+
case LLVMUserOp1: self = .userOp1
209+
case LLVMUserOp2: self = .userOp2
210+
case LLVMVAArg: self = .vaArg
211+
case LLVMExtractElement: self = .extractElement
212+
case LLVMInsertElement: self = .insertElement
213+
case LLVMShuffleVector: self = .shuffleVector
214+
case LLVMExtractValue: self = .extractValue
215+
case LLVMInsertValue: self = .insertValue
216+
case LLVMFence: self = .fence
217+
case LLVMAtomicCmpXchg: self = .atomicCmpXchg
218+
case LLVMAtomicRMW: self = .atomicRMW
219+
case LLVMResume: self = .resume
220+
case LLVMLandingPad: self = .landingPad
221+
case LLVMCleanupRet: self = .cleanupRet
222+
case LLVMCatchRet: self = .catchRet
223+
case LLVMCatchPad: self = .catchPad
224+
case LLVMCleanupPad: self = .cleanupPad
225+
case LLVMCatchSwitch: self = .catchSwitch
226+
default: fatalError("invalid LLVMOpcode \(rawValue)")
227+
}
228+
}
161229
}

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