Skip to content

Commit d00a8cd

Browse files
wizardengineerwizardengineer
committed
[CIR] Added support for psrldqi
1 parent c0f9f45 commit d00a8cd

File tree

2 files changed

+220
-1
lines changed

2 files changed

+220
-1
lines changed

‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp‎

Lines changed: 42 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,47 @@ static mlir::Value emitX86PSLLDQIByteShift(CIRGenFunction &cgf,
201201
return builder.createBitcast(shuffleResult, resultType);
202202
}
203203

204+
static mlir::Value emitX86PSRLDQIByteShift(CIRGenFunction &cgf,
205+
const CallExpr *E,
206+
ArrayRef<mlir::Value> Ops) {
207+
auto &builder = cgf.getBuilder();
208+
auto resultType = cast<cir::VectorType>(Ops[0].getType());
209+
auto loc = cgf.getLoc(E->getExprLoc());
210+
unsigned shiftVal = getIntValueFromConstOp(Ops[1]) & 0xff;
211+
212+
// If psrldq is shifting the vector more than 15 bytes, emit zero.
213+
if (shiftVal >= 16)
214+
return builder.getZero(loc, resultType);
215+
216+
auto numElts = resultType.getSize() * 8;
217+
assert(numElts % 16 == 0 && "Expected a multiple of 16");
218+
219+
llvm::SmallVector<int64_t, 64> indices;
220+
221+
// This correlates to the OG CodeGen
222+
// As stated in the OG, 256/512-bit psrldq operates on 128-bit lanes.
223+
// So we have to make sure we handle it.
224+
for (unsigned l = 0; l < numElts; l += 16) {
225+
for (unsigned i = 0; i < 16; ++i) {
226+
unsigned idx = i + shiftVal;
227+
if (idx >= 16)
228+
idx += numElts - 16;
229+
indices.push_back(idx + l);
230+
}
231+
}
232+
233+
auto byteVecTy = cir::VectorType::get(builder.getSInt8Ty(), numElts);
234+
mlir::Value byteCast = builder.createBitcast(Ops[0], byteVecTy);
235+
mlir::Value zero = builder.getZero(loc, byteVecTy);
236+
237+
// Perform the shuffle (right shift by inserting zeros from the left)
238+
mlir::Value shuffleResult =
239+
builder.createVecShuffle(loc, byteCast, zero, indices);
240+
241+
// Cast back to original type
242+
return builder.createBitcast(shuffleResult, resultType);
243+
}
244+
204245
static mlir::Value emitX86MaskedCompareResult(CIRGenFunction &cgf,
205246
mlir::Value cmp, unsigned numElts,
206247
mlir::Value maskIn,
@@ -1381,7 +1422,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
13811422
case X86::BI__builtin_ia32_psrldqi128_byteshift:
13821423
case X86::BI__builtin_ia32_psrldqi256_byteshift:
13831424
case X86::BI__builtin_ia32_psrldqi512_byteshift:
1384-
llvm_unreachable("psrldqi NYI");
1425+
return emitX86PSRLDQIByteShift(*this, E, Ops);
13851426
case X86::BI__builtin_ia32_kshiftliqi:
13861427
case X86::BI__builtin_ia32_kshiftlihi:
13871428
case X86::BI__builtin_ia32_kshiftlisi:

‎clang/test/CIR/CodeGen/builtin-x86-psrldqi.cpp‎

Lines changed: 178 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,178 @@
1+
// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir -target-feature +avx512f -target-feature +avx512bw
2+
// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR
3+
// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll -target-feature +avx512f -target-feature +avx512bw
4+
// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM
5+
// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.og.ll -target-feature +avx512f -target-feature +avx512bw
6+
// RUN: FileCheck --input-file=%t.og.ll %s -check-prefix=OGCG
7+
8+
// Tests PSRLDQI byte shift intrinsics implementation in ClangIR
9+
// Compares CIR emission, LLVM lowering, and original CodeGen output
10+
11+
typedef long long __m128i __attribute__((__vector_size__(16)));
12+
typedef long long __m256i __attribute__((__vector_size__(32)));
13+
typedef long long __m512i __attribute__((__vector_size__(64)));
14+
15+
// Declare the builtins directly
16+
extern __m128i __builtin_ia32_psrldqi128_byteshift(__m128i, int);
17+
extern __m256i __builtin_ia32_psrldqi256_byteshift(__m256i, int);
18+
extern __m512i __builtin_ia32_psrldqi512_byteshift(__m512i, int);
19+
20+
// ============================================================================
21+
// Core Functionality Tests
22+
// ============================================================================
23+
24+
// CIR-LABEL: @_Z22test_psrldqi128_shift4Dv2_x
25+
// LLVM-LABEL: @_Z22test_psrldqi128_shift4Dv2_x
26+
// OGCG-LABEL: @_Z22test_psrldqi128_shift4Dv2_x
27+
__m128i test_psrldqi128_shift4(__m128i a) {
28+
// Should shift right by 4 bytes, filling with zeros from the left
29+
// CIR: %{{.*}} = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i] : !cir.vector<!s8i x 16>
30+
// LLVM: %{{.*}} = shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
31+
// OGCG: %{{.*}} = shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
32+
return __builtin_ia32_psrldqi128_byteshift(a, 4);
33+
}
34+
35+
// CIR-LABEL: @_Z22test_psrldqi128_shift0Dv2_x
36+
// LLVM-LABEL: @_Z22test_psrldqi128_shift0Dv2_x
37+
// OGCG-LABEL: @_Z22test_psrldqi128_shift0Dv2_x
38+
__m128i test_psrldqi128_shift0(__m128i a) {
39+
// Should return input unchanged (shift by 0)
40+
// CIR: %{{.*}} = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<!s8i x 16>
41+
// LLVM: %{{.*}} = shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
42+
// OGCG: %{{.*}} = shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
43+
return __builtin_ia32_psrldqi128_byteshift(a, 0);
44+
}
45+
46+
// CIR-LABEL: @_Z23test_psrldqi128_shift16Dv2_x
47+
// LLVM-LABEL: @_Z23test_psrldqi128_shift16Dv2_x
48+
// OGCG-LABEL: @_Z23test_psrldqi128_shift16Dv2_x
49+
__m128i test_psrldqi128_shift16(__m128i a) {
50+
// Entire vector shifted out, should return zero
51+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 2>
52+
// LLVM: store <2 x i64> zeroinitializer, ptr %{{.*}}, align 16
53+
// OGCG: ret <2 x i64> zeroinitializer
54+
return __builtin_ia32_psrldqi128_byteshift(a, 16);
55+
}
56+
57+
// ============================================================================
58+
// 256-bit Tests (Two Independent 128-bit Lanes)
59+
// ============================================================================
60+
61+
// CIR-LABEL: @_Z22test_psrldqi256_shift8Dv4_x
62+
// LLVM-LABEL: @_Z22test_psrldqi256_shift8Dv4_x
63+
// OGCG-LABEL: @_Z22test_psrldqi256_shift8Dv4_x
64+
__m256i test_psrldqi256_shift8(__m256i a) {
65+
// Each 128-bit lane shifts independently by 8 bytes
66+
// CIR: %{{.*}} = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 32>) [#cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<32> : !s32i, #cir.int<33> : !s32i, #cir.int<34> : !s32i, #cir.int<35> : !s32i, #cir.int<36> : !s32i, #cir.int<37> : !s32i, #cir.int<38> : !s32i, #cir.int<39> : !s32i, #cir.int<24> : !s32i, #cir.int<25> : !s32i, #cir.int<26> : !s32i, #cir.int<27> : !s32i, #cir.int<28> : !s32i, #cir.int<29> : !s32i, #cir.int<30> : !s32i, #cir.int<31> : !s32i, #cir.int<48> : !s32i, #cir.int<49> : !s32i, #cir.int<50> : !s32i, #cir.int<51> : !s32i, #cir.int<52> : !s32i, #cir.int<53> : !s32i, #cir.int<54> : !s32i, #cir.int<55> : !s32i] : !cir.vector<!s8i x 32>
67+
// LLVM: %{{.*}} = shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
68+
// OGCG: %{{.*}} = shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
69+
return __builtin_ia32_psrldqi256_byteshift(a, 8);
70+
}
71+
72+
// CIR-LABEL: @_Z23test_psrldqi256_shift16Dv4_x
73+
// LLVM-LABEL: @_Z23test_psrldqi256_shift16Dv4_x
74+
// OGCG-LABEL: @_Z23test_psrldqi256_shift16Dv4_x
75+
__m256i test_psrldqi256_shift16(__m256i a) {
76+
// Both lanes completely shifted out, returns zero
77+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 4>
78+
// LLVM: store <4 x i64> zeroinitializer, ptr %{{.*}}, align 32
79+
// OGCG: ret <4 x i64> zeroinitializer
80+
return __builtin_ia32_psrldqi256_byteshift(a, 16);
81+
}
82+
83+
// ============================================================================
84+
// 512-bit Tests (Four Independent 128-bit Lanes)
85+
// ============================================================================
86+
87+
// CIR-LABEL: @_Z22test_psrldqi512_shift4Dv8_x
88+
// LLVM-LABEL: @_Z22test_psrldqi512_shift4Dv8_x
89+
// OGCG-LABEL: @_Z22test_psrldqi512_shift4Dv8_x
90+
__m512i test_psrldqi512_shift4(__m512i a) {
91+
// All 4 lanes shift independently by 4 bytes
92+
// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 64>)
93+
// LLVM: shufflevector <64 x i8> %{{.*}}, <64 x i8> zeroinitializer, <64 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 64, i32 65, i32 66, i32 67, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 80, i32 81, i32 82, i32 83, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 96, i32 97, i32 98, i32 99, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 112, i32 113, i32 114, i32 115>
94+
// OGCG: shufflevector <64 x i8> %{{.*}}, <64 x i8> zeroinitializer, <64 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 64, i32 65, i32 66, i32 67, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 80, i32 81, i32 82, i32 83, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 96, i32 97, i32 98, i32 99, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 112, i32 113, i32 114, i32 115>
95+
return __builtin_ia32_psrldqi512_byteshift(a, 4);
96+
}
97+
98+
// CIR-LABEL: @_Z23test_psrldqi512_shift16Dv8_x
99+
// LLVM-LABEL: @_Z23test_psrldqi512_shift16Dv8_x
100+
// OGCG-LABEL: @_Z23test_psrldqi512_shift16Dv8_x
101+
__m512i test_psrldqi512_shift16(__m512i a) {
102+
// All 4 lanes completely cleared
103+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 8>
104+
// LLVM: store <8 x i64> zeroinitializer, ptr %{{.*}}, align 64
105+
// OGCG: ret <8 x i64> zeroinitializer
106+
return __builtin_ia32_psrldqi512_byteshift(a, 16);
107+
}
108+
109+
// ============================================================================
110+
// Input-Output Verification Tests
111+
// ============================================================================
112+
113+
// Test with specific input values to verify correct data transformation
114+
// CIR-LABEL: @_Z26test_input_output_shift4_1Dv2_x
115+
// LLVM-LABEL: @_Z26test_input_output_shift4_1Dv2_x
116+
// OGCG-LABEL: @_Z26test_input_output_shift4_1Dv2_x
117+
__m128i test_input_output_shift4_1(__m128i a) {
118+
// Input: [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] (bytes)
119+
// Shift right by 4 bytes (insert 4 zeros at end)
120+
// Output: [11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0] (bytes)
121+
// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i] : !cir.vector<!s8i x 16>
122+
// LLVM: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
123+
// OGCG: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
124+
return __builtin_ia32_psrldqi128_byteshift(a, 4);
125+
}
126+
127+
// Test 256-bit lane independence with specific input pattern
128+
// CIR-LABEL: @_Z34test_input_output_256_independenceDv4_x
129+
// LLVM-LABEL: @_Z34test_input_output_256_independenceDv4_x
130+
// OGCG-LABEL: @_Z34test_input_output_256_independenceDv4_x
131+
__m256i test_input_output_256_independence(__m256i a) {
132+
// Input: Two 128-bit lanes, each with pattern [15,14,13,...,2,1,0]
133+
// Lane 0: [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
134+
// Lane 1: [31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16]
135+
// After shift by 8 bytes:
136+
// Lane 0: [7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0]
137+
// Lane 1: [23, 22, 21, 20, 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0]
138+
// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 32>)
139+
// LLVM: shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
140+
// OGCG: shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
141+
return __builtin_ia32_psrldqi256_byteshift(a, 8);
142+
}
143+
144+
// ============================================================================
145+
// Edge Cases
146+
// ============================================================================
147+
148+
// Test with concrete constant values to verify exact transformation
149+
// CIR-LABEL: @_Z28test_concrete_input_constantv
150+
// LLVM-LABEL: @_Z28test_concrete_input_constantv
151+
// OGCG-LABEL: @_Z28test_concrete_input_constantv
152+
__m128i test_concrete_input_constant() {
153+
// Create a known input pattern: 0x0F0E0D0C0B0A09080706050403020100
154+
// This represents bytes [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
155+
__m128i input = (__m128i){0x0706050403020100LL, 0x0F0E0D0C0B0A0908LL};
156+
157+
// Shift right by 4 bytes - should produce: 0x00000000000000000F0E0D0C0B0A0908
158+
// This represents bytes [11,10,9,8,7,6,5,4,3,2,1,0,0,0,0,0]
159+
__m128i result = __builtin_ia32_psrldqi128_byteshift(input, 4);
160+
161+
// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i] : !cir.vector<!s8i x 16>
162+
// LLVM: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
163+
// OGCG: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
164+
165+
return result;
166+
}
167+
168+
// CIR-LABEL: @_Z22test_large_shift_valueDv2_x
169+
// LLVM-LABEL: @_Z22test_large_shift_valueDv2_x
170+
// OGCG-LABEL: @_Z22test_large_shift_valueDv2_x
171+
__m128i test_large_shift_value(__m128i a) {
172+
// 240 & 0xFF = 240, so this should return zero (240 > 16)
173+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 2>
174+
// LLVM: store <2 x i64> zeroinitializer, ptr %{{.*}}, align 16
175+
// OGCG: ret <2 x i64> zeroinitializer
176+
return __builtin_ia32_psrldqi128_byteshift(a, 240);
177+
}
178+

0 commit comments

Comments
 (0)