From e8b9fa08646212e1ec202c2dc80de7fc011065aa Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Fri, 28 Mar 2025 17:41:43 +0000 Subject: [PATCH 1/6] DRAFT: Top-level DV: connect JTAG This commit connects the JTAG agent, monitor and other UVM components to get going with RV_DM top-level DV. Currently this commit is marked as draft because I'm getting the following error when running any top-level test ``` UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:75) [cfg] Looking for image for memory ChipMemSRAM with plus arg ChipMemSRAM_image_file=%s UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:80) [cfg] Got image file /home/mvdmaas/repos/chip-sunburst/scratch_sw/bare_metal/build/checks/chip_check.vmem for memory ChipMemSRAM UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:75) [cfg] Looking for image for memory ChipMemROM with plus arg ChipMemROM_image_file=%s UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:75) [cfg] Looking for image for memory ChipMemUsbdevBuf with plus arg ChipMemUsbdevBuf_image_file=%s UVM_FATAL @ 0: (uvm_reg_block.svh:1093) [RegModel] Register model requires that UVM_REG_DATA_WIDTH be defined as 41 or greater. Currently defined as 32 ``` --- hw/top_chip/dv/env/top_chip_dv_env.sv | 9 ++++++++- hw/top_chip/dv/env/top_chip_dv_env_cfg.sv | 4 ++++ hw/top_chip/dv/env/top_chip_dv_env_pkg.sv | 3 ++- hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv | 3 +++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/top_chip/dv/env/top_chip_dv_env.sv b/hw/top_chip/dv/env/top_chip_dv_env.sv index c8ae7cc0..72224dbf 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env.sv @@ -15,6 +15,7 @@ class top_chip_dv_env extends uvm_env; // Agents i2c_agent m_i2c_agents[NI2cs]; + jtag_agent m_jtag_agent; pattgen_agent m_pattgen_agent; spi_agent m_spi_device_agents[NSpis]; uart_agent m_uart_agents[NUarts]; @@ -64,9 +65,13 @@ class top_chip_dv_env extends uvm_env; // Instantiate I^2C agents foreach (m_i2c_agents[i]) begin m_i2c_agents[i] = i2c_agent::type_id::create($sformatf("m_i2c_agent%0d", i), this); - uvm_config_db#(i2c_agent_cfg)::set(this, $sformatf("m_i2c_agent%0d*", i), "cfg",cfg.m_i2c_agent_cfgs[i]); + uvm_config_db#(i2c_agent_cfg)::set(this, $sformatf("m_i2c_agent%0d*", i), "cfg", cfg.m_i2c_agent_cfgs[i]); end + // Instantiate JTAG agent + m_jtag_agent = jtag_agent::type_id::create("m_jtag_agent", this); + uvm_config_db#(jtag_agent_cfg)::set(this, "m_jtag_agent*", "cfg", cfg.m_jtag_agent_cfg); + // Instantiate pattgen agent m_pattgen_agent = pattgen_agent::type_id::create("m_pattgen_agent", this); uvm_config_db#(pattgen_agent_cfg)::set(this, "m_pattgen_agent*", "cfg", cfg.m_pattgen_agent_cfg); @@ -100,6 +105,7 @@ class top_chip_dv_env extends uvm_env; foreach (m_i2c_agents[i]) begin virtual_sequencer.i2c_sequencer_hs[i] = m_i2c_agents[i].sequencer; end + virtual_sequencer.jtag_sequencer_hs = m_jtag_agent.sequencer; foreach (m_spi_device_agents[i]) begin virtual_sequencer.spi_device_sequencer_hs[i] = m_spi_device_agents[i].sequencer; end @@ -112,6 +118,7 @@ class top_chip_dv_env extends uvm_env; foreach (m_i2c_agents[i]) begin m_i2c_agents[i].monitor.controller_mode_rd_item_port.connect(virtual_sequencer.i2c_rd_fifos[i].analysis_export); end + m_jtag_agent.monitor.analysis_port.connect(virtual_sequencer.jtag_rx_fifo.analysis_export); for (int i = 0; i < NUM_PATTGEN_CHANNELS; i++) begin m_pattgen_agent.monitor.item_port[i].connect(virtual_sequencer.pattgen_rx_fifo[i].analysis_export); end diff --git a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv index f0d35ee0..708c85e0 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv @@ -16,6 +16,7 @@ class top_chip_dv_env_cfg extends uvm_object; // External interface agent configs rand i2c_agent_cfg m_i2c_agent_cfgs[NI2cs]; + rand jtag_agent_cfg m_jtag_agent_cfg; rand pattgen_agent_cfg m_pattgen_agent_cfg; rand spi_agent_cfg m_spi_device_agent_cfgs[NSpis]; rand uart_agent_cfg m_uart_agent_cfgs[NUarts]; @@ -37,6 +38,9 @@ class top_chip_dv_env_cfg extends uvm_object; m_i2c_agent_cfgs[i].en_monitor = 1'b0; end + // create jtag agent config obj + m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg"); + // create pattgen agent config obj m_pattgen_agent_cfg = pattgen_agent_cfg::type_id::create("m_pattgen_agent_cfg"); m_pattgen_agent_cfg.if_mode = Device; diff --git a/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv b/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv index 2fb4cd41..7a33b783 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv @@ -7,8 +7,9 @@ package top_chip_dv_env_pkg; import dv_utils_pkg::*; import mem_bkdr_util_pkg::*; import i2c_agent_pkg::*; - import spi_agent_pkg::*; + import jtag_agent_pkg::*; import pattgen_agent_pkg::*; + import spi_agent_pkg::*; import uart_agent_pkg::*; // macro includes diff --git a/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv b/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv index 0a598dc5..9c691ca3 100644 --- a/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv +++ b/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv @@ -14,12 +14,14 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer; // Handles to specific interface agent sequencers. Used by some virtual // sequences to drive RX (to-chip) items. i2c_sequencer i2c_sequencer_hs[NI2cs]; + jtag_sequencer jtag_sequencer_hs; spi_sequencer spi_device_sequencer_hs[NSpis]; uart_sequencer uart_sequencer_hs[NUarts]; // FIFOs for monitor output. Used by some virtual sequences to check // TX (from-chip) items. uvm_tlm_analysis_fifo #(i2c_item) i2c_rd_fifos[NI2cs]; + uvm_tlm_analysis_fifo #(jtag_item) jtag_rx_fifo; uvm_tlm_analysis_fifo #(pattgen_item) pattgen_rx_fifo[NUM_PATTGEN_CHANNELS]; uvm_tlm_analysis_fifo #(uart_item) uart_tx_fifos[NUarts]; @@ -27,6 +29,7 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer; super.build_phase(phase); // Construct monitor output FIFOs foreach (i2c_rd_fifos[i]) i2c_rd_fifos[i] = new($sformatf("i2c_rd_fifo%0d", i), this); + jtag_rx_fifo = new("jtag_rx_fifo", this); foreach (pattgen_rx_fifo[i]) pattgen_rx_fifo[i] = new($sformatf("pattgen_rx_fifo%0d", i), this); foreach (uart_tx_fifos[i]) uart_tx_fifos[i] = new($sformatf("uart_tx_fifo%0d", i), this); endfunction From f23061b78a1efb5c18a6dd9d9c893d6c79b78d87 Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Mon, 31 Mar 2025 10:44:59 +0100 Subject: [PATCH 2/6] Draft: still working --- hw/top_chip/dv/env/top_chip_dv_env.sv | 8 ++++---- hw/top_chip/dv/env/top_chip_dv_env_cfg.sv | 4 ++-- hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv | 4 ++-- hw/top_chip/dv/tb/tb.sv | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/top_chip/dv/env/top_chip_dv_env.sv b/hw/top_chip/dv/env/top_chip_dv_env.sv index 72224dbf..4edb9f2d 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env.sv @@ -69,8 +69,8 @@ class top_chip_dv_env extends uvm_env; end // Instantiate JTAG agent - m_jtag_agent = jtag_agent::type_id::create("m_jtag_agent", this); - uvm_config_db#(jtag_agent_cfg)::set(this, "m_jtag_agent*", "cfg", cfg.m_jtag_agent_cfg); + //m_jtag_agent = jtag_agent::type_id::create("m_jtag_agent", this); + //uvm_config_db#(jtag_agent_cfg)::set(this, "m_jtag_agent*", "cfg", cfg.m_jtag_agent_cfg); // Instantiate pattgen agent m_pattgen_agent = pattgen_agent::type_id::create("m_pattgen_agent", this); @@ -105,7 +105,7 @@ class top_chip_dv_env extends uvm_env; foreach (m_i2c_agents[i]) begin virtual_sequencer.i2c_sequencer_hs[i] = m_i2c_agents[i].sequencer; end - virtual_sequencer.jtag_sequencer_hs = m_jtag_agent.sequencer; + //virtual_sequencer.jtag_sequencer_hs = m_jtag_agent.sequencer; foreach (m_spi_device_agents[i]) begin virtual_sequencer.spi_device_sequencer_hs[i] = m_spi_device_agents[i].sequencer; end @@ -118,7 +118,7 @@ class top_chip_dv_env extends uvm_env; foreach (m_i2c_agents[i]) begin m_i2c_agents[i].monitor.controller_mode_rd_item_port.connect(virtual_sequencer.i2c_rd_fifos[i].analysis_export); end - m_jtag_agent.monitor.analysis_port.connect(virtual_sequencer.jtag_rx_fifo.analysis_export); + //m_jtag_agent.monitor.analysis_port.connect(virtual_sequencer.jtag_rx_fifo.analysis_export); for (int i = 0; i < NUM_PATTGEN_CHANNELS; i++) begin m_pattgen_agent.monitor.item_port[i].connect(virtual_sequencer.pattgen_rx_fifo[i].analysis_export); end diff --git a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv index 708c85e0..7cd36e76 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv @@ -16,7 +16,7 @@ class top_chip_dv_env_cfg extends uvm_object; // External interface agent configs rand i2c_agent_cfg m_i2c_agent_cfgs[NI2cs]; - rand jtag_agent_cfg m_jtag_agent_cfg; + //rand jtag_agent_cfg m_jtag_agent_cfg; rand pattgen_agent_cfg m_pattgen_agent_cfg; rand spi_agent_cfg m_spi_device_agent_cfgs[NSpis]; rand uart_agent_cfg m_uart_agent_cfgs[NUarts]; @@ -39,7 +39,7 @@ class top_chip_dv_env_cfg extends uvm_object; end // create jtag agent config obj - m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg"); + //m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg"); // create pattgen agent config obj m_pattgen_agent_cfg = pattgen_agent_cfg::type_id::create("m_pattgen_agent_cfg"); diff --git a/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv b/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv index 9c691ca3..2d928127 100644 --- a/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv +++ b/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv @@ -21,7 +21,7 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer; // FIFOs for monitor output. Used by some virtual sequences to check // TX (from-chip) items. uvm_tlm_analysis_fifo #(i2c_item) i2c_rd_fifos[NI2cs]; - uvm_tlm_analysis_fifo #(jtag_item) jtag_rx_fifo; + //um_tlm_analysis_fifo #(jtag_item) jtag_rx_fifo; uvm_tlm_analysis_fifo #(pattgen_item) pattgen_rx_fifo[NUM_PATTGEN_CHANNELS]; uvm_tlm_analysis_fifo #(uart_item) uart_tx_fifos[NUarts]; @@ -29,7 +29,7 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer; super.build_phase(phase); // Construct monitor output FIFOs foreach (i2c_rd_fifos[i]) i2c_rd_fifos[i] = new($sformatf("i2c_rd_fifo%0d", i), this); - jtag_rx_fifo = new("jtag_rx_fifo", this); + //jtag_rx_fifo = new("jtag_rx_fifo", this); foreach (pattgen_rx_fifo[i]) pattgen_rx_fifo[i] = new($sformatf("pattgen_rx_fifo%0d", i), this); foreach (uart_tx_fifos[i]) uart_tx_fifos[i] = new($sformatf("uart_tx_fifo%0d", i), this); endfunction diff --git a/hw/top_chip/dv/tb/tb.sv b/hw/top_chip/dv/tb/tb.sv index 5ac06ce9..ac85bd55 100644 --- a/hw/top_chip/dv/tb/tb.sv +++ b/hw/top_chip/dv/tb/tb.sv @@ -358,7 +358,7 @@ module top_chip_asic_tb; // Feed certain I/O signals to matching agents for vseq-specific driving/checking uvm_config_db#(virtual pins_if#(NGpioPins))::set(null, "*", "gpio_pins_vif", gpio_pins_if); uvm_config_db#(virtual pattgen_if)::set(null, "*.env.m_pattgen_agent*", "vif", pattgen_if); - uvm_config_db#(virtual jtag_if)::set(null, "*.env.m_jtag_agent*", "vif", jtag_if); + //uvm_config_db#(virtual jtag_if)::set(null, "*.env.m_jtag_agent*", "vif", jtag_if); run_test(); end From 542b8c7890942bc5e241933c5c17731316a552ce Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Mon, 31 Mar 2025 10:53:31 +0100 Subject: [PATCH 3/6] Draft: Still working --- hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv b/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv index 2d928127..9c691ca3 100644 --- a/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv +++ b/hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv @@ -21,7 +21,7 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer; // FIFOs for monitor output. Used by some virtual sequences to check // TX (from-chip) items. uvm_tlm_analysis_fifo #(i2c_item) i2c_rd_fifos[NI2cs]; - //um_tlm_analysis_fifo #(jtag_item) jtag_rx_fifo; + uvm_tlm_analysis_fifo #(jtag_item) jtag_rx_fifo; uvm_tlm_analysis_fifo #(pattgen_item) pattgen_rx_fifo[NUM_PATTGEN_CHANNELS]; uvm_tlm_analysis_fifo #(uart_item) uart_tx_fifos[NUarts]; @@ -29,7 +29,7 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer; super.build_phase(phase); // Construct monitor output FIFOs foreach (i2c_rd_fifos[i]) i2c_rd_fifos[i] = new($sformatf("i2c_rd_fifo%0d", i), this); - //jtag_rx_fifo = new("jtag_rx_fifo", this); + jtag_rx_fifo = new("jtag_rx_fifo", this); foreach (pattgen_rx_fifo[i]) pattgen_rx_fifo[i] = new($sformatf("pattgen_rx_fifo%0d", i), this); foreach (uart_tx_fifos[i]) uart_tx_fifos[i] = new($sformatf("uart_tx_fifo%0d", i), this); endfunction From 9c20a3b8d18ba5969291212f2eeec01e80d0c58e Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Mon, 31 Mar 2025 11:53:13 +0100 Subject: [PATCH 4/6] Minimal failure with print statements --- hw/top_chip/dv/env/top_chip_dv_env.core | 2 +- hw/top_chip/dv/env/top_chip_dv_env_cfg.sv | 11 +++++++++-- .../lowrisc_ip/dv/sv/jtag_agent/jtag_agent_cfg.sv | 7 +++++++ .../lowrisc_ip/dv/sv/jtag_agent/jtag_dtm_reg_block.sv | 1 + 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/hw/top_chip/dv/env/top_chip_dv_env.core b/hw/top_chip/dv/env/top_chip_dv_env.core index 7d830466..1358e4e4 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env.core +++ b/hw/top_chip/dv/env/top_chip_dv_env.core @@ -14,10 +14,10 @@ filesets: - lowrisc:dv:sw_logger_if - lowrisc:dv:mem_bkdr_util - lowrisc:dv:i2c_agent + - lowrisc:dv:jtag_agent - lowrisc:dv:spi_agent - lowrisc:dv:pattgen_agent - lowrisc:dv:uart_agent - - lowrisc:dv:jtag_agent - lowrisc:dv:pins_if - lowrisc:dv:common_ifs files: diff --git a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv index 7cd36e76..cbe6d1e8 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv @@ -16,7 +16,7 @@ class top_chip_dv_env_cfg extends uvm_object; // External interface agent configs rand i2c_agent_cfg m_i2c_agent_cfgs[NI2cs]; - //rand jtag_agent_cfg m_jtag_agent_cfg; + rand jtag_agent_cfg m_jtag_agent_cfg; rand pattgen_agent_cfg m_pattgen_agent_cfg; rand spi_agent_cfg m_spi_device_agent_cfgs[NSpis]; rand uart_agent_cfg m_uart_agent_cfgs[NUarts]; @@ -29,6 +29,7 @@ class top_chip_dv_env_cfg extends uvm_object; endfunction virtual function void initialize(); + `uvm_info(`gfn, "top_chip_env_cfg.initialize() start", UVM_LOW); get_mem_image_files_from_plusargs(); // create i2c agent config obj @@ -38,8 +39,12 @@ class top_chip_dv_env_cfg extends uvm_object; m_i2c_agent_cfgs[i].en_monitor = 1'b0; end + `uvm_info(`gfn, "m_jtag_agent_cfg::create() start", UVM_LOW); // create jtag agent config obj - //m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg"); + m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg"); + m_jtag_agent_cfg.if_mode = dv_utils_pkg::Host; + m_jtag_agent_cfg.is_active = 1'b1; + `uvm_info(`gfn, "m_jtag_agent_cfg::create() end", UVM_LOW); // create pattgen agent config obj m_pattgen_agent_cfg = pattgen_agent_cfg::type_id::create("m_pattgen_agent_cfg"); @@ -63,6 +68,8 @@ class top_chip_dv_env_cfg extends uvm_object; m_uart_agent_cfgs[i].en_tx_monitor = 0; m_uart_agent_cfgs[i].en_rx_monitor = 0; end + + `uvm_info(`gfn, "top_chip_env_cfg.initialize() end", UVM_LOW); endfunction function void get_mem_image_files_from_plusargs(); diff --git a/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_agent_cfg.sv b/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_agent_cfg.sv index a7c91f31..6f00609c 100644 --- a/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_agent_cfg.sv +++ b/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_agent_cfg.sv @@ -41,15 +41,22 @@ class jtag_agent_cfg extends dv_base_agent_cfg; function new (string name = ""); super.new(name); + `uvm_info(`gfn, "jtag_agent_cfg.new() start", UVM_LOW); jtag_if_connected = new(); // Create the JTAG DTM RAL. + `uvm_info(`gfn, "jtag_dtm_reg_block::create()", UVM_LOW); jtag_dtm_ral = jtag_dtm_reg_block::type_id::create("jtag_dtm_ral"); + `uvm_info(`gfn, "jtag_dtm_ral.build()", UVM_LOW); jtag_dtm_ral.build(.base_addr(0), .csr_excl(null)); jtag_dtm_ral.set_supports_byte_enable(1'b0); + `uvm_info(`gfn, "jtag_dtm_ral.lock_model()", UVM_LOW); jtag_dtm_ral.lock_model(); + `uvm_info(`gfn, "jtag_dtm_ral.compute_mapped_addr_ranges()", UVM_LOW); jtag_dtm_ral.compute_mapped_addr_ranges(); + `uvm_info(`gfn, "jtag_dtm_ral.compute_unmapped_addr_ranges()", UVM_LOW); jtag_dtm_ral.compute_unmapped_addr_ranges(); // TODO: fix the computation of mapped and unmapped ranges. + `uvm_info(`gfn, "jtag_agent_cfg.new() end", UVM_LOW); endfunction : new endclass diff --git a/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_dtm_reg_block.sv b/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_dtm_reg_block.sv index 53fea09b..5fa8b478 100644 --- a/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_dtm_reg_block.sv +++ b/hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_dtm_reg_block.sv @@ -372,6 +372,7 @@ class jtag_dtm_reg_block extends dv_base_reg_block; virtual function void build(uvm_reg_addr_t base_addr, csr_excl_item csr_excl = null); + `uvm_info(`gfn, $sformatf("jtag_dtm_reg_block::build() JTAG_DRW %d", JTAG_DRW), UVM_LOW); // create default map this.default_map = create_map(.name("default_map"), .base_addr(base_addr), From e9dcee209089fab147b2e763e581e6f1e6c20574 Mon Sep 17 00:00:00 2001 From: Elliot Baptist Date: Mon, 31 Mar 2025 13:44:50 +0100 Subject: [PATCH 5/6] Override `UVM_REG_DATA_WIDTH` (via `tl_dw`) The `jtag_dtm_reg_dmi` register is 41 bits wide, so we need a wider `UVM_REG_DATA_WIDTH` than the 32 specified in *common_sim_cfg.hjson*. OpenTitan currently takes the approach of overriding `tl_dw` in the chip-level sim cfg HJSON file to achieve this, which we shall replicate. --- hw/top_chip/dv/top_chip_sim_cfg.hjson | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/top_chip/dv/top_chip_sim_cfg.hjson b/hw/top_chip/dv/top_chip_sim_cfg.hjson index 136dc87a..afd061dc 100644 --- a/hw/top_chip/dv/top_chip_sim_cfg.hjson +++ b/hw/top_chip/dv/top_chip_sim_cfg.hjson @@ -26,6 +26,19 @@ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson" ] + // Override existing project defaults to supply chip-specific values. + overrides: [ + // The jtag agent requires the data and bytenable widths to be increased. + { + name: tl_dw + value: 64 + } + { + name: tl_dbw + value: 8 + } + ] + sim_tops: [""] build_opts: ["+define+RVFI=1"] From 9fcf60c6e205e6c9be6e61e560b544584aeaf391 Mon Sep 17 00:00:00 2001 From: Elliot Baptist Date: Mon, 31 Mar 2025 13:45:10 +0100 Subject: [PATCH 6/6] Draft: Re-enable jtag_agent --- hw/top_chip/dv/env/top_chip_dv_env.sv | 8 ++++---- hw/top_chip/dv/tb/tb.sv | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/top_chip/dv/env/top_chip_dv_env.sv b/hw/top_chip/dv/env/top_chip_dv_env.sv index 4edb9f2d..72224dbf 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env.sv @@ -69,8 +69,8 @@ class top_chip_dv_env extends uvm_env; end // Instantiate JTAG agent - //m_jtag_agent = jtag_agent::type_id::create("m_jtag_agent", this); - //uvm_config_db#(jtag_agent_cfg)::set(this, "m_jtag_agent*", "cfg", cfg.m_jtag_agent_cfg); + m_jtag_agent = jtag_agent::type_id::create("m_jtag_agent", this); + uvm_config_db#(jtag_agent_cfg)::set(this, "m_jtag_agent*", "cfg", cfg.m_jtag_agent_cfg); // Instantiate pattgen agent m_pattgen_agent = pattgen_agent::type_id::create("m_pattgen_agent", this); @@ -105,7 +105,7 @@ class top_chip_dv_env extends uvm_env; foreach (m_i2c_agents[i]) begin virtual_sequencer.i2c_sequencer_hs[i] = m_i2c_agents[i].sequencer; end - //virtual_sequencer.jtag_sequencer_hs = m_jtag_agent.sequencer; + virtual_sequencer.jtag_sequencer_hs = m_jtag_agent.sequencer; foreach (m_spi_device_agents[i]) begin virtual_sequencer.spi_device_sequencer_hs[i] = m_spi_device_agents[i].sequencer; end @@ -118,7 +118,7 @@ class top_chip_dv_env extends uvm_env; foreach (m_i2c_agents[i]) begin m_i2c_agents[i].monitor.controller_mode_rd_item_port.connect(virtual_sequencer.i2c_rd_fifos[i].analysis_export); end - //m_jtag_agent.monitor.analysis_port.connect(virtual_sequencer.jtag_rx_fifo.analysis_export); + m_jtag_agent.monitor.analysis_port.connect(virtual_sequencer.jtag_rx_fifo.analysis_export); for (int i = 0; i < NUM_PATTGEN_CHANNELS; i++) begin m_pattgen_agent.monitor.item_port[i].connect(virtual_sequencer.pattgen_rx_fifo[i].analysis_export); end diff --git a/hw/top_chip/dv/tb/tb.sv b/hw/top_chip/dv/tb/tb.sv index ac85bd55..5ac06ce9 100644 --- a/hw/top_chip/dv/tb/tb.sv +++ b/hw/top_chip/dv/tb/tb.sv @@ -358,7 +358,7 @@ module top_chip_asic_tb; // Feed certain I/O signals to matching agents for vseq-specific driving/checking uvm_config_db#(virtual pins_if#(NGpioPins))::set(null, "*", "gpio_pins_vif", gpio_pins_if); uvm_config_db#(virtual pattgen_if)::set(null, "*.env.m_pattgen_agent*", "vif", pattgen_if); - //uvm_config_db#(virtual jtag_if)::set(null, "*.env.m_jtag_agent*", "vif", jtag_if); + uvm_config_db#(virtual jtag_if)::set(null, "*.env.m_jtag_agent*", "vif", jtag_if); run_test(); end