From 80f2a1439280ffcd09d3bf2f12ae6b763ed283ae Mon Sep 17 00:00:00 2001 From: Daniel Kucera Date: Sun, 29 Jul 2018 16:30:17 +0200 Subject: [PATCH] added 1-bit mode to spi flash --- misoc/cores/spi_flash.py | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/misoc/cores/spi_flash.py b/misoc/cores/spi_flash.py index dbc0c566a..18081248d 100644 --- a/misoc/cores/spi_flash.py +++ b/misoc/cores/spi_flash.py @@ -24,6 +24,11 @@ def _format_cmd(cmd, spi_width): c &= ~(1<<(b*spi_width)) return c +class SpiIF(object): + def __init__(self, i, o, oe): + self.i = i + self.o = o + self.oe = oe class SpiFlash(Module, AutoCSR): def __init__(self, pads, dummy=15, div=2, with_bitbang=True): @@ -35,7 +40,12 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True): Optionally supports software bitbanging (for write, erase, or other commands). """ self.bus = bus = wishbone.Interface() - spi_width = len(pads.dq) + + if hasattr(pads, "mosi"): + spi_width = 1 + else: + spi_width = len(pads.dq) + if with_bitbang: self.bitbang = CSRStorage(4) self.miso = CSRStatus() @@ -59,8 +69,13 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True): pads.cs_n.reset = 1 - dq = TSTriple(spi_width) - self.specials.dq = dq.get_tristate(pads.dq) + if spi_width > 1: + dq = TSTriple(spi_width) + self.specials.dq = dq.get_tristate(pads.dq) + else: + dq = SpiIF(pads.miso, pads.mosi, Signal()) + assert with_bitbang == False, \ + "Bitbang not supported with 1-bit SPI flash." sr = Signal(max(cmd_width, addr_width, wbone_width)) self.comb += bus.dat_r.eq(sr)