From 88bcc8130307e3cd91d473cb40312e3542ce11e8 Mon Sep 17 00:00:00 2001 From: Wessel Nieboer Date: Sun, 8 Feb 2026 16:31:59 +0100 Subject: [PATCH 1/3] Apply SX1262 register 0x8B5 patch for improved GC1109 RX sensitivity Sets the LSB of undocumented SX1262 register 0x8B5 on Heltec V4 and Wireless Tracker V2 boards with the GC1109 FEM. This patch was recommended by Heltec/Semtech and tested in MeshCore PR #1398, where it significantly reduced packet loss on the Heltec V4. --- src/mesh/SX126xInterface.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mesh/SX126xInterface.cpp b/src/mesh/SX126xInterface.cpp index d6f1ac4081d..e3076cb86ea 100644 --- a/src/mesh/SX126xInterface.cpp +++ b/src/mesh/SX126xInterface.cpp @@ -194,6 +194,19 @@ template bool SX126xInterface::init() LOG_INFO("Set RX gain to power saving mode (boosted mode off); result: %d", result); } +#ifdef USE_GC1109_PA + // Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity + // on boards with the GC1109 FEM. Sets LSB of register 0x8B5. + // Reference: https://github.com/meshcore-dev/MeshCore/pull/1398 + { + uint8_t regVal = 0; + lora.readRegister(0x8B5, ®Val, 1); + regVal |= 0x01; + lora.writeRegister(0x8B5, ®Val, 1); + LOG_INFO("Applied SX1262 register 0x8B5 patch for GC1109 RX improvement"); + } +#endif + #if 0 // Read/write a register we are not using (only used for FSK mode) to test SPI comms uint8_t crcLSB = 0; From 2a30e63e38dac95def4e70a09961e632eb439994 Mon Sep 17 00:00:00 2001 From: Wessel Nieboer Date: Wed, 11 Feb 2026 03:09:09 +0100 Subject: [PATCH 2/3] Use higher level function --- src/mesh/SX126xInterface.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/mesh/SX126xInterface.cpp b/src/mesh/SX126xInterface.cpp index e3076cb86ea..5b2fb3ac3ed 100644 --- a/src/mesh/SX126xInterface.cpp +++ b/src/mesh/SX126xInterface.cpp @@ -196,14 +196,12 @@ template bool SX126xInterface::init() #ifdef USE_GC1109_PA // Undocumented SX1262 register patch recommended by Heltec/Semtech for improved RX sensitivity - // on boards with the GC1109 FEM. Sets LSB of register 0x8B5. + // on boards with the GC1109 FEM. Sets bit 0 of register 0x8B5. // Reference: https://github.com/meshcore-dev/MeshCore/pull/1398 - { - uint8_t regVal = 0; - lora.readRegister(0x8B5, ®Val, 1); - regVal |= 0x01; - lora.writeRegister(0x8B5, ®Val, 1); + if (module.SPIsetRegValue(0x8B5, 0x01, 0, 0) == RADIOLIB_ERR_NONE) { LOG_INFO("Applied SX1262 register 0x8B5 patch for GC1109 RX improvement"); + } else { + LOG_WARN("Failed to apply SX1262 register 0x8B5 patch for GC1109"); } #endif From b0a638ccea23577ed71a75b7a7ce6576ff5bca9c Mon Sep 17 00:00:00 2001 From: Wessel Nieboer Date: Wed, 11 Feb 2026 03:09:19 +0100 Subject: [PATCH 3/3] Add .venv/ to .gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index d6d97c6c488..43cee78db73 100644 --- a/.gitignore +++ b/.gitignore @@ -33,6 +33,7 @@ __pycache__ *~ venv/ +.venv/ release/ .vscode/extensions.json /compile_commands.json