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katharosadamithro
katharosada
authored and
mithro
committed
lm32: Update generated headers
Updated to use mimasv2 using headers from HDMI2USB build at commit cbd1e31b3a9f88e0d1ecb682b51f6d41454766de
1 parent b4ea4ba commit 89863dc

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4 files changed

+232
-61
lines changed

4 files changed

+232
-61
lines changed

‎lm32/generated/csr.h

Lines changed: 200 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
#ifndef __GENERATED_CSR_H
22
#define __GENERATED_CSR_H
3-
#include "hw/common.h"
3+
#include <hw/common.h>
44

5-
/* dna */
6-
#define CSR_DNA_BASE 0xe0006000
7-
#define CSR_DNA_ID_ADDR 0xe0006000
8-
#define CSR_DNA_ID_SIZE 8
9-
static inline unsigned long long int dna_id_read(void) {
5+
/* info */
6+
#define CSR_INFO_BASE 0xe0006000
7+
#define CSR_INFO_DNA_ID_ADDR 0xe0006000
8+
#define CSR_INFO_DNA_ID_SIZE 8
9+
static inline unsigned long long int info_dna_id_read(void) {
1010
unsigned long long int r = MMPTR(0xe0006000);
1111
r <<= 8;
1212
r |= MMPTR(0xe0006004);
@@ -24,6 +24,48 @@ static inline unsigned long long int dna_id_read(void) {
2424
r |= MMPTR(0xe000601c);
2525
return r;
2626
}
27+
#define CSR_INFO_GIT_COMMIT_ADDR 0xe0006020
28+
#define CSR_INFO_GIT_COMMIT_SIZE 20
29+
#define CSR_INFO_PLATFORM_PLATFORM_ADDR 0xe0006070
30+
#define CSR_INFO_PLATFORM_PLATFORM_SIZE 8
31+
static inline unsigned long long int info_platform_platform_read(void) {
32+
unsigned long long int r = MMPTR(0xe0006070);
33+
r <<= 8;
34+
r |= MMPTR(0xe0006074);
35+
r <<= 8;
36+
r |= MMPTR(0xe0006078);
37+
r <<= 8;
38+
r |= MMPTR(0xe000607c);
39+
r <<= 8;
40+
r |= MMPTR(0xe0006080);
41+
r <<= 8;
42+
r |= MMPTR(0xe0006084);
43+
r <<= 8;
44+
r |= MMPTR(0xe0006088);
45+
r <<= 8;
46+
r |= MMPTR(0xe000608c);
47+
return r;
48+
}
49+
#define CSR_INFO_PLATFORM_TARGET_ADDR 0xe0006090
50+
#define CSR_INFO_PLATFORM_TARGET_SIZE 8
51+
static inline unsigned long long int info_platform_target_read(void) {
52+
unsigned long long int r = MMPTR(0xe0006090);
53+
r <<= 8;
54+
r |= MMPTR(0xe0006094);
55+
r <<= 8;
56+
r |= MMPTR(0xe0006098);
57+
r <<= 8;
58+
r |= MMPTR(0xe000609c);
59+
r <<= 8;
60+
r |= MMPTR(0xe00060a0);
61+
r <<= 8;
62+
r |= MMPTR(0xe00060a4);
63+
r <<= 8;
64+
r |= MMPTR(0xe00060a8);
65+
r <<= 8;
66+
r |= MMPTR(0xe00060ac);
67+
return r;
68+
}
2769

2870
/* sdram */
2971
#define CSR_SDRAM_BASE 0xe0004000
@@ -76,51 +118,138 @@ static inline void sdram_dfii_pi0_baddress_write(unsigned char value) {
76118
MMPTR(0xe0004014) = value;
77119
}
78120
#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018
79-
#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2
80-
static inline unsigned short int sdram_dfii_pi0_wrdata_read(void) {
81-
unsigned short int r = MMPTR(0xe0004018);
121+
#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 4
122+
static inline unsigned int sdram_dfii_pi0_wrdata_read(void) {
123+
unsigned int r = MMPTR(0xe0004018);
82124
r <<= 8;
83125
r |= MMPTR(0xe000401c);
126+
r <<= 8;
127+
r |= MMPTR(0xe0004020);
128+
r <<= 8;
129+
r |= MMPTR(0xe0004024);
84130
return r;
85131
}
86-
static inline void sdram_dfii_pi0_wrdata_write(unsigned short int value) {
87-
MMPTR(0xe0004018) = value >> 8;
88-
MMPTR(0xe000401c) = value;
132+
static inline void sdram_dfii_pi0_wrdata_write(unsigned int value) {
133+
MMPTR(0xe0004018) = value >> 24;
134+
MMPTR(0xe000401c) = value >> 16;
135+
MMPTR(0xe0004020) = value >> 8;
136+
MMPTR(0xe0004024) = value;
89137
}
90-
#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004020
91-
#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2
92-
static inline unsigned short int sdram_dfii_pi0_rddata_read(void) {
93-
unsigned short int r = MMPTR(0xe0004020);
138+
#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004028
139+
#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 4
140+
static inline unsigned int sdram_dfii_pi0_rddata_read(void) {
141+
unsigned int r = MMPTR(0xe0004028);
94142
r <<= 8;
95-
r |= MMPTR(0xe0004024);
143+
r |= MMPTR(0xe000402c);
144+
r <<= 8;
145+
r |= MMPTR(0xe0004030);
146+
r <<= 8;
147+
r |= MMPTR(0xe0004034);
96148
return r;
97149
}
98-
99-
/* spiflash */
100-
#define CSR_SPIFLASH_BASE 0xe0005000
101-
#define CSR_SPIFLASH_BITBANG_ADDR 0xe0005000
102-
#define CSR_SPIFLASH_BITBANG_SIZE 1
103-
static inline unsigned char spiflash_bitbang_read(void) {
104-
unsigned char r = MMPTR(0xe0005000);
150+
#define CSR_SDRAM_DFII_PI1_COMMAND_ADDR 0xe0004038
151+
#define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1
152+
static inline unsigned char sdram_dfii_pi1_command_read(void) {
153+
unsigned char r = MMPTR(0xe0004038);
154+
return r;
155+
}
156+
static inline void sdram_dfii_pi1_command_write(unsigned char value) {
157+
MMPTR(0xe0004038) = value;
158+
}
159+
#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR 0xe000403c
160+
#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1
161+
static inline unsigned char sdram_dfii_pi1_command_issue_read(void) {
162+
unsigned char r = MMPTR(0xe000403c);
163+
return r;
164+
}
165+
static inline void sdram_dfii_pi1_command_issue_write(unsigned char value) {
166+
MMPTR(0xe000403c) = value;
167+
}
168+
#define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR 0xe0004040
169+
#define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 2
170+
static inline unsigned short int sdram_dfii_pi1_address_read(void) {
171+
unsigned short int r = MMPTR(0xe0004040);
172+
r <<= 8;
173+
r |= MMPTR(0xe0004044);
105174
return r;
106175
}
107-
static inline void spiflash_bitbang_write(unsigned char value) {
108-
MMPTR(0xe0005000) = value;
176+
static inline void sdram_dfii_pi1_address_write(unsigned short int value) {
177+
MMPTR(0xe0004040) = value >> 8;
178+
MMPTR(0xe0004044) = value;
109179
}
110-
#define CSR_SPIFLASH_MISO_ADDR 0xe0005004
111-
#define CSR_SPIFLASH_MISO_SIZE 1
112-
static inline unsigned char spiflash_miso_read(void) {
113-
unsigned char r = MMPTR(0xe0005004);
180+
#define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR 0xe0004048
181+
#define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1
182+
static inline unsigned char sdram_dfii_pi1_baddress_read(void) {
183+
unsigned char r = MMPTR(0xe0004048);
114184
return r;
115185
}
116-
#define CSR_SPIFLASH_BITBANG_EN_ADDR 0xe0005008
117-
#define CSR_SPIFLASH_BITBANG_EN_SIZE 1
118-
static inline unsigned char spiflash_bitbang_en_read(void) {
119-
unsigned char r = MMPTR(0xe0005008);
186+
static inline void sdram_dfii_pi1_baddress_write(unsigned char value) {
187+
MMPTR(0xe0004048) = value;
188+
}
189+
#define CSR_SDRAM_DFII_PI1_WRDATA_ADDR 0xe000404c
190+
#define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 4
191+
static inline unsigned int sdram_dfii_pi1_wrdata_read(void) {
192+
unsigned int r = MMPTR(0xe000404c);
193+
r <<= 8;
194+
r |= MMPTR(0xe0004050);
195+
r <<= 8;
196+
r |= MMPTR(0xe0004054);
197+
r <<= 8;
198+
r |= MMPTR(0xe0004058);
199+
return r;
200+
}
201+
static inline void sdram_dfii_pi1_wrdata_write(unsigned int value) {
202+
MMPTR(0xe000404c) = value >> 24;
203+
MMPTR(0xe0004050) = value >> 16;
204+
MMPTR(0xe0004054) = value >> 8;
205+
MMPTR(0xe0004058) = value;
206+
}
207+
#define CSR_SDRAM_DFII_PI1_RDDATA_ADDR 0xe000405c
208+
#define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 4
209+
static inline unsigned int sdram_dfii_pi1_rddata_read(void) {
210+
unsigned int r = MMPTR(0xe000405c);
211+
r <<= 8;
212+
r |= MMPTR(0xe0004060);
213+
r <<= 8;
214+
r |= MMPTR(0xe0004064);
215+
r <<= 8;
216+
r |= MMPTR(0xe0004068);
217+
return r;
218+
}
219+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_UPDATE_ADDR 0xe000406c
220+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_UPDATE_SIZE 1
221+
static inline unsigned char sdram_controller_bandwidth_update_read(void) {
222+
unsigned char r = MMPTR(0xe000406c);
223+
return r;
224+
}
225+
static inline void sdram_controller_bandwidth_update_write(unsigned char value) {
226+
MMPTR(0xe000406c) = value;
227+
}
228+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_NREADS_ADDR 0xe0004070
229+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_NREADS_SIZE 3
230+
static inline unsigned int sdram_controller_bandwidth_nreads_read(void) {
231+
unsigned int r = MMPTR(0xe0004070);
232+
r <<= 8;
233+
r |= MMPTR(0xe0004074);
234+
r <<= 8;
235+
r |= MMPTR(0xe0004078);
236+
return r;
237+
}
238+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_NWRITES_ADDR 0xe000407c
239+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_NWRITES_SIZE 3
240+
static inline unsigned int sdram_controller_bandwidth_nwrites_read(void) {
241+
unsigned int r = MMPTR(0xe000407c);
242+
r <<= 8;
243+
r |= MMPTR(0xe0004080);
244+
r <<= 8;
245+
r |= MMPTR(0xe0004084);
120246
return r;
121247
}
122-
static inline void spiflash_bitbang_en_write(unsigned char value) {
123-
MMPTR(0xe0005008) = value;
248+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_DATA_WIDTH_ADDR 0xe0004088
249+
#define CSR_SDRAM_CONTROLLER_BANDWIDTH_DATA_WIDTH_SIZE 1
250+
static inline unsigned char sdram_controller_bandwidth_data_width_read(void) {
251+
unsigned char r = MMPTR(0xe0004088);
252+
return r;
124253
}
125254

126255
/* timer0 */
@@ -293,10 +422,44 @@ static inline void uart_phy_tuning_word_write(unsigned int value) {
293422

294423
/* constants */
295424
#define UART_INTERRUPT 0
425+
static inline int uart_interrupt_read(void) {
426+
return 0;
427+
}
296428
#define TIMER0_INTERRUPT 1
297-
#define SYSTEM_CLOCK_FREQUENCY 80000000
429+
static inline int timer0_interrupt_read(void) {
430+
return 1;
431+
}
432+
#define CSR_DATA_WIDTH 8
433+
static inline int csr_data_width_read(void) {
434+
return 8;
435+
}
436+
#define SYSTEM_CLOCK_FREQUENCY 83333333
437+
static inline int system_clock_frequency_read(void) {
438+
return 83333333;
439+
}
298440
#define SPIFLASH_PAGE_SIZE 256
441+
static inline int spiflash_page_size_read(void) {
442+
return 256;
443+
}
299444
#define SPIFLASH_SECTOR_SIZE 65536
445+
static inline int spiflash_sector_size_read(void) {
446+
return 65536;
447+
}
300448
#define L2_SIZE 8192
449+
static inline int l2_size_read(void) {
450+
return 8192;
451+
}
452+
#define CONFIG_CLOCK_FREQUENCY 83333333
453+
static inline int config_clock_frequency_read(void) {
454+
return 83333333;
455+
}
456+
#define CONFIG_CPU_TYPE "LM32"
457+
static inline const char * config_cpu_type_read(void) {
458+
return "LM32";
459+
}
460+
#define CONFIG_CSR_DATA_WIDTH 8
461+
static inline int config_csr_data_width_read(void) {
462+
return 8;
463+
}
301464

302465
#endif

‎lm32/generated/mem.h

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,15 @@
11
#ifndef __GENERATED_MEM_H
22
#define __GENERATED_MEM_H
33

4-
#define ROM_BASE 0x00000000
5-
#define ROM_SIZE 0x00008000
6-
74
#define SRAM_BASE 0x10000000
8-
#define SRAM_SIZE 0x00008000
5+
#define SRAM_SIZE 0x00004000
96

10-
#define SPIFLASH_BASE 0x20000000
11-
#define SPIFLASH_SIZE 0x00180000
7+
#define ROM_BASE 0x00080000
8+
#define ROM_SIZE 0x00200000
129

1310
#define MAIN_RAM_BASE 0x40000000
14-
#define MAIN_RAM_SIZE 0x02000000
11+
#define MAIN_RAM_SIZE 0x04000000
1512

16-
#define FLASH_BOOT_ADDRESS 0x20180000
13+
#define FLASH_BOOT_ADDRESS 0x00088000
1714

1815
#endif

‎lm32/generated/regions.ld

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
MEMORY {
2-
rom : ORIGIN = 0x00000000, LENGTH = 0x00008000
3-
sram : ORIGIN = 0x10000000, LENGTH = 0x00008000
4-
spiflash : ORIGIN = 0x20000000, LENGTH = 0x00180000
5-
main_ram : ORIGIN = 0x40000000, LENGTH = 0x02000000
2+
sram : ORIGIN = 0x10000000, LENGTH = 0x00004000
3+
rom : ORIGIN = 0x00080000, LENGTH = 0x00200000
4+
main_ram : ORIGIN = 0x40000000, LENGTH = 0x04000000
65
}

‎lm32/generated/sdram_phy.h

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#include <generated/csr.h>
55
#include <hw/flags.h>
66

7-
#define DFII_NPHASES 1
7+
#define DFII_NPHASES 2
88

99
static void cdelay(int i);
1010

@@ -13,25 +13,32 @@ static void command_p0(int cmd)
1313
sdram_dfii_pi0_command_write(cmd);
1414
sdram_dfii_pi0_command_issue_write(1);
1515
}
16+
static void command_p1(int cmd)
17+
{
18+
sdram_dfii_pi1_command_write(cmd);
19+
sdram_dfii_pi1_command_issue_write(1);
20+
}
1621

1722

1823
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
19-
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X)
24+
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi1_address_write(X)
2025

2126
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
22-
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
27+
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
2328

2429
#define command_prd(X) command_p0(X)
25-
#define command_pwr(X) command_p0(X)
30+
#define command_pwr(X) command_p1(X)
2631

2732
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
2833

29-
const unsigned int sdram_dfii_pix_wrdata_addr[1] = {
30-
CSR_SDRAM_DFII_PI0_WRDATA_ADDR
34+
const unsigned int sdram_dfii_pix_wrdata_addr[2] = {
35+
CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
36+
CSR_SDRAM_DFII_PI1_WRDATA_ADDR
3137
};
3238

33-
const unsigned int sdram_dfii_pix_rddata_addr[1] = {
34-
CSR_SDRAM_DFII_PI0_RDDATA_ADDR
39+
const unsigned int sdram_dfii_pix_rddata_addr[2] = {
40+
CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
41+
CSR_SDRAM_DFII_PI1_RDDATA_ADDR
3542
};
3643

3744
static void init_sequence(void)
@@ -47,8 +54,13 @@ static void init_sequence(void)
4754
sdram_dfii_pi0_baddress_write(0);
4855
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
4956

50-
/* Load Mode Register / Reset DLL, CL=2, BL=1 */
51-
sdram_dfii_pi0_address_write(0x120);
57+
/* Load Extended Mode Register */
58+
sdram_dfii_pi0_address_write(0x0);
59+
sdram_dfii_pi0_baddress_write(2);
60+
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
61+
62+
/* Load Mode Register / Reset DLL, CL=3, BL=4 */
63+
sdram_dfii_pi0_address_write(0x132);
5264
sdram_dfii_pi0_baddress_write(0);
5365
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
5466
cdelay(200);
@@ -70,8 +82,8 @@ static void init_sequence(void)
7082
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
7183
cdelay(4);
7284

73-
/* Load Mode Register / CL=2, BL=1 */
74-
sdram_dfii_pi0_address_write(0x20);
85+
/* Load Mode Register / CL=3, BL=4 */
86+
sdram_dfii_pi0_address_write(0x32);
7587
sdram_dfii_pi0_baddress_write(0);
7688
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
7789
cdelay(200);

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