digital systems

Table of Contents Courses, Websites Finite State Machines Specifying FSM's transition behavior STEP #1: Declare two states STEP #2: Create state F/F STEP #3: Compute next state STEP #4: Outputs Design Components Interfacing FIFO interface AXI Interface Xilinx Tools

Courses, Websites

• Berkeley CS150 Components and Design Techniques for Digital Systems
  • FSM Design: shows some VLOG synthesis
• Design & Reuse
• EE Times

Finite State Machines

• Moore machines (output dependent only on states) require more states but safer

Specifying FSM's transition behavior

STEP #1: Declare two states

• • state: current state
  • next_state: F(state, inputs) computed in combinational logic; will be updated on the next rising edge

STEP #2: Create state F/F

• Create physical means of transitioing from curr_state to the next state

always @(posedge clk) begin
  if (rst) state <= init_state;
  else state <= next_state;
end

STEP #3: Compute next state

• Implement conditional-transitioning mechanism thta will choose what the next state should be and under what conditions a transition should be made
  • Create always @* (combinational) process which will compute next_state

always @* begin
  // to avoid latch inference over next_state, assign default value first
  //   - this also allows to save code (no full if-else blocks)
  next_state = state;
  case (state) 
  s0: ...
  s1: ...
  default: next_state = initial_state;
  endcase
end

STEP #4: Outputs

• Output values based on current state, either in contasgn or combo logic

assign out0 = FUNC(state)

always @* begin
  out1 = <default_value>;
  case (state) 
  S0: out1 = ...
  S1: out1 = ...
  endcase
end

Design Components

Interfacing

• Interfacing: http://www-inst.eecs.berkeley.edu/~cs150/fa13/agenda/lec/lec10-interfacing.pdf

FIFO interface

• FIFO Interfaces (good)
• FIFO slides #1: http://www-inst.eecs.berkeley.edu/~cs150/fa13/agenda/lec/lec10-interfacing.pdf
• FIFO slides #2: http://www-inst.eecs.berkeley.edu/~cs150/fa13/agenda/lec/lec14-sift-v2.pdf
• Why:
  • "Decouple" producer and consumer (which is not synchronized for many reasons)
• Usages:
  • Interfacing I/O devices (e.g. network interface): data bursts from network, then processor bursts to memory buffer (or reads one word at a time from interface). Operations not synchronized
  • receive data from a high speed serial interface
  • buffer data for transmitting UART to host (e.g. RTL generates faster than host can receive at 9600 baud)
  • align data in time for math operations
  • buffer data to/from SDRAM interface
  • crossing the clock domains: two clocks -- one for read, the other for write

AXI Interface

• AXI Interfacing (good)

Xilinx Tools

• Xilinx XST User Guide
• Xilinx FIFO generator
• Xilinx ISE Handbook