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Added things for 100D_V2 hardware variant
1 parent 812f530 commit 422e348

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4 files changed

+80
-6
lines changed

4 files changed

+80
-6
lines changed

build_all/rebuild_all

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -409,6 +409,25 @@ make -j8 build_args='-DDISABLE_HW_LIMITS -DHW_SOURCE=\"hw_stormcore_100d.c\" -DH
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cd $DIR
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cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default_no_hw_limits.bin
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#################### STORMCORE_100D_V2 ########################
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COPYDIR=STORMCORE_100D_V2
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rm -f $COPYDIR/*
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# default
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cd $FWPATH
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touch conf_general.h
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make -j8 build_args='-DHW_SOURCE=\"hw_stormcore_100d.c\" -DHW_HEADER=\"hw_stormcore_100d.h\" -DHW_VER_IS_100D_V2' USE_VERBOSE_COMPILE=no
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cd $DIR
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cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default.bin
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# default with HW limits disabled
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cd $FWPATH
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touch conf_general.h
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make -j8 build_args='-DDISABLE_HW_LIMITS -DHW_SOURCE=\"hw_stormcore_100d.c\" -DHW_HEADER=\"hw_stormcore_100d.h\" -DHW_VER_IS_100D_V2' USE_VERBOSE_COMPILE=no
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cd $DIR
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cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default_no_hw_limits.bin
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#################### STORMCORE_100S ########################
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COPYDIR=STORMCORE_100S

conf_general.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,7 @@
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//#define HW_HEADER "hw_uxv_sr.h"
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//#define HW_DUAL_CONFIG_PARALLEL
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//#define HW_VER_IS_100D_V2
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//#define HW_SOURCE "hw_stormcore_100d.c"
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//#define HW_HEADER "hw_stormcore_100d.h"
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hwconf/hw_stormcore_100d.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,17 @@ void hw_init_gpio(void) {
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
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63+
#ifdef HW_VER_IS_100D_V2
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palSetPadMode(PHASE_FILTER_GPIO, PHASE_FILTER_PIN,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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PHASE_FILTER_OFF();
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palSetPadMode(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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PHASE_FILTER_OFF_M2();
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#endif
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hwconf/hw_stormcore_100d.h

Lines changed: 49 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
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#ifdef HW_HAS_DUAL_PARALLEL
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#define HW_NAME "STORMCORE_100D_PARALLEL"
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#elif defined(HW_VER_IS_100D_V2)
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#define HW_NAME "STORMCORE_100D_V2"
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#else
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#define HW_NAME "STORMCORE_100D"
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#endif
@@ -69,6 +71,18 @@
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#define SMART_SWITCH_MSECS_PRESSED_OFF 2000
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74+
#ifdef HW_VER_IS_100D_V2
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#define HW_HAS_PHASE_FILTERS
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#define PHASE_FILTER_GPIO GPIOE
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#define PHASE_FILTER_PIN 1
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#define PHASE_FILTER_GPIO_M2 GPIOE
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#define PHASE_FILTER_PIN_M2 4
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#define PHASE_FILTER_ON() palSetPad(PHASE_FILTER_GPIO, PHASE_FILTER_PIN)
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#define PHASE_FILTER_OFF() palClearPad(PHASE_FILTER_GPIO, PHASE_FILTER_PIN)
82+
#define PHASE_FILTER_ON_M2() palSetPad(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2)
83+
#define PHASE_FILTER_OFF_M2() palClearPad(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2)
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#endif
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#define HW_SHUTDOWN_HOLD_ON();
@@ -96,6 +110,17 @@
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#define HW_UART_P_RX_PORT GPIOA
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#define HW_UART_P_RX_PIN 10
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#ifdef HW_VER_IS_100D_V2
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//Pins for Third UART
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#define HW_UART_3_BAUD 115200
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#define HW_UART_3_DEV SD2
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#define HW_UART_3_GPIO_AF GPIO_AF_USART2
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#define HW_UART_3_TX_PORT GPIOD
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#define HW_UART_3_TX_PIN 6
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#define HW_UART_3_RX_PORT GPIOD
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#define HW_UART_3_RX_PIN 5
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#endif
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99124
// SPI for DRV8301
100125
#define DRV8323S_MOSI_GPIO GPIOC
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#define DRV8323S_MOSI_PIN 12
@@ -226,11 +251,22 @@
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#ifndef VIN_R2
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#define VIN_R2 2200.0
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#endif
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#ifdef HW_VER_IS_100D_V2
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#ifndef CURRENT_AMP_GAIN
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#define CURRENT_AMP_GAIN 20.0
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#endif
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#ifndef CURRENT_SHUNT_RES
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#define CURRENT_SHUNT_RES 0.0005
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#endif
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#else
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#ifndef CURRENT_AMP_GAIN
230-
#define CURRENT_AMP_GAIN 10.0
265+
#define CURRENT_AMP_GAIN 10.0
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#endif
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#ifndef CURRENT_SHUNT_RES
233-
#define CURRENT_SHUNT_RES 0.001
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#define CURRENT_SHUNT_RES 0.001
269+
#endif
234270
#endif
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#define VBATT_R1 360000.0
@@ -334,10 +370,17 @@
334370
#define NRF_PIN_MISO 10
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// NRF SWD
337-
#define NRF5x_SWDIO_GPIO GPIOD
338-
#define NRF5x_SWDIO_PIN 6
339-
#define NRF5x_SWCLK_GPIO GPIOD
340-
#define NRF5x_SWCLK_PIN 5
373+
#ifdef HW_VER_IS_100D_V2
374+
#define NRF5x_SWDIO_GPIO GPIOD
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#define NRF5x_SWDIO_PIN 9
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#define NRF5x_SWCLK_GPIO GPIOD
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#define NRF5x_SWCLK_PIN 8
378+
#else
379+
#define NRF5x_SWDIO_GPIO GPIOD
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#define NRF5x_SWDIO_PIN 6
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#define NRF5x_SWCLK_GPIO GPIOD
382+
#define NRF5x_SWCLK_PIN 5
383+
#endif
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342385
#ifndef MCCONF_DEFAULT_MOTOR_TYPE
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#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC

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