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LTX-2.5 full-model DiT forward measured at ~162 s on GB10; 60 forwards will not fit a 4 h lease #1375

Description

@localai-bot

First measured DiT forward cost for LTX-2.5 on the full 21.004 B model: ~162 s per forward on GB10. At the structural 60 forwards that is ~2.7 h of denoise alone, which does not fit a 4 h lease once load and tail are included.

This is also the first run in which a DiT forward is known to have executed at all. Nine prior attempts never reached one.

Provenance

Run 20260819T150230Z, job d985d423, dgx:gpu0 (GB10, 20 cores, 119.631 GiB).
binary_sha256=0a43a750deb3457520fb10ed44ee0cb62db8740dca65cc4e2d7c33864ae456b2, built_from=7b9e207b1 (carries #1252).
Config: one_stage --device cuda, 1024x576/25f, full/dev transformer, STG off and modality 1.0 (the device arm refuses a perturbed forward, #1092), real CFG live.

The measurement

[t=2417s] governor[gpu-edge(no-stacks)]: first_dit=481s observed_forward_starts=3
          per_forward~69.1s projected_total=5225s budget=7153s
[t=3251s] ABORT[92] PROJECTED OVERRUN: first_dit=481s per_forward~162.0s x 60
          + tail 600s = 10803s > budget 7153s
[t=3256s] memory: baseline_used=4.752GiB peak_used=79.658GiB OWN_DEMAND=74.907GiB
          min_avail=39.97GiB
          child exit=-15 samples=3192 gpu_busy_idle_edges=7

Note the estimate's own trajectory: per_forward read 69.1 s at three observed starts and 162.0 s by the abort. An early projection from few samples understated it by 2.3×. Anyone re-measuring should let the observation count grow before quoting a figure.

What is NOT established

  • Attribution. phase=OTHER throughout — eu-stack unwinds zero frames in the rc worker container, so no stack-based attribution was possible. 162 s is a wall-clock interval between GPU busy→idle edges, not a profile. Whether the time is GPU compute, host-side glue, or transfer is unknown.
  • dit_runs=0 is the stack-based counter and is not evidence of absence; gpu_busy_idle_edges=7 is the counter that worked.
  • No comparison against vLLM/vLLM-Omni on the same workload. Without that, 162 s is a fact about this port, not a parity gap.
  • Nothing about smaller geometries; the fallback rung had not reported when this was filed.

Why it matters

one_stage is currently the only full-model arm that reaches generation, and at 162 s/forward it needs ~3 h of denoise for a 25-frame 1024x576 clip. Every full-model render is therefore blocked on a bounded lease unless the per-forward cost comes down or the geometry shrinks.

The obvious next step is attribution: get a working profile inside the lease (an in-process phase marker, since eu-stack is blind there — #1010's territory), then compare against the pinned oracle on an identical workload.

Related: #1252 and #1259 (the two GEMM-seam fixes that made reaching this point possible), #1254, #1092 (the perturbation refusal that forces STG off on the device arm).

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