diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_3D_bot.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_3D_bot.png new file mode 100644 index 0000000..0080297 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_3D_bot.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_3D_top.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_3D_top.png new file mode 100644 index 0000000..05629ad Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_3D_top.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_BBloopback.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_BBloopback.png new file mode 100644 index 0000000..9cc29d0 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_BBloopback.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_GPIOs.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_GPIOs.png new file mode 100644 index 0000000..65464fc Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_GPIOs.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_HW_VER.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_HW_VER.png new file mode 100644 index 0000000..080fe20 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_HW_VER.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_J2.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_J2.png new file mode 100644 index 0000000..99ba554 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_J2.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_LMS.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_LMS.png new file mode 100644 index 0000000..68f227b Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_LMS.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_M.2.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_M.2.png new file mode 100644 index 0000000..b6a25ff Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_M.2.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_RXBB.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_RXBB.png new file mode 100644 index 0000000..ac00efc Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_RXBB.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_ioexp.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_ioexp.png new file mode 100644 index 0000000..f2707cd Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_ioexp.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_laconfig.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_laconfig.png new file mode 100644 index 0000000..d6a8a81 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_changes_laconfig.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_LEDs.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_LEDs.png new file mode 100644 index 0000000..c1e34ca Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_LEDs.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_bot.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_bot.png new file mode 100644 index 0000000..76d9138 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_bot.png differ diff --git a/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_top.png b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_top.png new file mode 100644 index 0000000..15df858 Binary files /dev/null and b/docs/images/LimeSDR-Micro_M.2_2280_v1.2_components_top.png differ diff --git a/docs/reference/M.2/changelog.rst b/docs/reference/M.2/changelog.rst index 8cb2ec3..29532f9 100644 --- a/docs/reference/M.2/changelog.rst +++ b/docs/reference/M.2/changelog.rst @@ -3,6 +3,120 @@ Changelog The first production LimeSDR Micro M.2 2280 was revision v1.0 and so this changelog starts with changes from that point. +v1.2 +**** + +LimeSDR-Micro M.2 2280 v1.2 board is designed using LimeSDR Micro M.2 2280 v1.1 project as base with the schematic and PCB Layout changes described in this document. + +The major changes are: + +* Added SMBUS interface for M.2 (disconnected by default). +* Moved M.2 pins that now are used for SMBUS to other M.2 pins. +* Added TH jumper (NF) for LA_CFG_BOOT_SRC0. +* Changed default BOOT_SRC to EEPROM. +* Connected LMS RBB to ADCIN (Ch 1, 2 I/Q). +* Connected LMS_TSTAO, LMS_TSTDO0, LMS_TSTDO1 via 0R NF to J2 (PA_EN) for test signals measurement as option. +* Changed LMS VDD_TBB (P4) power from VCC1P25_LMS to VCC1P4_LMS + +M.2 Connector +============= + +In earlier M.2 specification there was no SMBUS interface. In later SMBUS interface was added for Socket 3 PCIe (Key M) and Socket 2 (Key B-M): + +* Pin 40 - GPIO_0 (I/O)/SMB_CLK (I/O) (0/1.8V*) +* Pin 42 - GPIO_1 (I/O)/SMB_DATA (I/O) (0/1.8V*) +* 44 GPIO_2 (I/O)/ALERT# (I) (0/1.8V*) + +Following changes for M.2 pins were implemented. + +* Disconnected M.2_GPIO_1 from pin 42 +* Connected M.2_GPIO_1 via 0R (as it was) to M.2 pin 58 (MFG_CLOCK). +* Renamed M.2_GPIO_1 to M.2_MFG. +* Disconnected M.2_TRX1 from pin 40 +* Connected M.2_TRX1 via 0R (as it was) to M.2 pin 56 (MFG_DATA). +* Connected LA_I2C_SDA_LS via 0R NF to M.2 pin 42 (SMB_DATA). +* Connected LA_I2C_SCL_LS via 0R NF to M.2 pin 40 (SMB_CLK). +* M.2 pin 44 (SMBUS ALERT) that was connected to M.2_GPIO_2 net via 0R (R142) was changed to 0R NF. + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_M.2.png + + Figure 1. M.2 Pins + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_GPIOs.png + + Figure 2. GPIOs + +BB processor boot configuration +=============================== + +After board firmware development and discussions decision was made that default boot mode must be EEPROM. In production for initial firmware programming and in case of firmware corruption simple method of changing boot to PCIe host memory was required. To temporarily change boot mode top PCIe 0.05” pitch header was added (not fitted). + +Following changes for BB processor was implemented: + +* Added TH jumper (NF) for LA_CFG_BOOT_SRC0, removed TP6. +* Changed default BOOT_SRC to EEPROM (R121 NF, R130 fit). +* TP6 (testpoint) for LA_CFG_BOOT_SRC0 line was removed. + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_laconfig.png + + Figure 3. LA9310 configuration + +RF transceiver (LMS) changes +============================ + +* Connected LA_PA_EN via 0R fit to J2 instead direct connection. +* Connected LMS_TSTAO, LMS_TSTDO0, LMS_TSTDO1 via 0R NF to J2 (PA_EN) for test signals measurement (PLL optimization etc.). + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_J2.png + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_LMS.png + + Figure 4. J2 connections + +* Removed series 0R on RX BB path: C8, C12, C13, C17, C18, C22, C23, C27 +* Removed series 0R on RX BB path: R28, R34, R37, R42, R44, R49, R51, R58 + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_RXBB.png + + Figure 5. LMS RX BB + +Connected LMS RBB to ADCIN (Ch 1, 2 I/Q). This will help to utilize internal BB ADC for DC offset and RSSI calibration: + +Y6 -> V4, AB2 -> U5, AB4 -> Y2, AA5 -> W3, AD2-> AA1, AC3 -> V6, AC5 -> AA3, AB6 ->Y4 + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_BBloopback.png + + Figure 6. LMS RX BB loopback + +Miscellaneous +============= + +Minor changes: + +* Cosmetic changes (LA9310 boot notes etc.) +* Removed series 0R resistors on RX BB path. + +Changed from HW_VER = 1 [0 1] to HW_VER = 2 [1 0] + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_ioexp.png + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_changes_HW_VER.png + + Figure 7. HW_VER bits + +PCB changes +=========== + +LimeSDR-Micro_M.2_2280 v1.2 is based on LimeSDR-Micro_M.2_2280 v1.1 layout. LimeSDR-Micro_M.2_2280 v1.2 complies with D3 height requirement (less or equal to 1.35 mm) from the bottom side. LimeSDR-Micro_M.2_2280 v1.2 doesn't comply with any allowed height requirement (1.5 mm maximum allowed) from the top side because of the height of VCTCXO, RF baluns and RF shield, which are up to 4.5mm. + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_3D_top.png + + Figure 8. LimeSDR-Micro M.2 2280 v1.2 3D view (top) + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_3D_bot.png + + Figure 9. LimeSDR-Micro M.2 2280 v1.2 3D view (bottom) + v1.1 **** The major changes are: @@ -34,7 +148,7 @@ Changed level converter LA_CFG_BOOT_SRC0 -> LA_TRX0 connections to LA_CFG_BOOT_S .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_txcontrol2.png :width: 300 - Figure 1. TX control + Figure 10. TX control Changed M.2 LA_CFG_BOOT_SRC0 net to LA_CFG_BOOT_SRC1 and M.2_TRX0 to M.2_TRX1 @@ -44,14 +158,14 @@ Changed M.2 LA_CFG_BOOT_SRC0 net to LA_CFG_BOOT_SRC1 and M.2_TRX0 to M.2_TRX1 .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_trxcontrol2.png :width: 300 - Figure 2. M.2_TRX control + Figure 11. M.2_TRX control Added MHF4 connector for LA_PA_EN. Placed instead RX_AUX (X3) connector. .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_paen.png :width: 300 - Figure 3. PA_EN connector + Figure 12. PA_EN connector A_TRX1 and LA_PA_EN lines can operate from LA9310 timer independently. LA_TRX1 is dedicated for internal RF TX switch control and its polarity depends on selected active channel. LA_PA_EN is dedicated for external RFFE control and can always maintain same polarity. @@ -63,7 +177,7 @@ LA_CFG_TEST_PORT_DIS line via 1.8 -> 3.3V conversion disconnected from LA_LNA1_E .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_txencontrol2.png :width: 300 - Figure 4. LMS_TXEN control + Figure 13. LMS_TXEN control BB processor @@ -76,7 +190,7 @@ Changed LA_CFG_PCIE_GEN configuration to 1: PCIe interface will allow negotiatio .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_LAconfig.png :width: 300 - Figure 5. BB processor configuration + Figure 14. BB processor configuration Clock ===== @@ -96,7 +210,7 @@ Disabled M.2_CLK_IN clock in path by default (0R NF). .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_lmk.png :width: 300 - Figure 6. LMK00101 clock buffer + Figure 15. LMK00101 clock buffer Disconnected MHF4 connector J3 from EXT_PPS_IN. @@ -107,14 +221,14 @@ Connected MHF4 connector J5 to EXT_PPS mux for EXT_PPS_IN/EXT_PPS_OUT. .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_pps.png :width: 300 - Figure 7. PPS circuit + Figure 16. PPS circuit Added ESD (NF) for ADF_REF_IN. .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_adf.png :width: 300 - Figure 8. ADF_REG_IN ESD + Figure 17. ADF_REG_IN ESD Miscellaneous ============= @@ -124,7 +238,7 @@ X3 (RX AUX) circuit removed. .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_x3.png :width: 300 - Figure 9. RF connectors + Figure 18. RF connectors Changed HW_VER from 0 to 1. @@ -135,7 +249,7 @@ Renamed A1 line to EXP_GPA1 and connected to FPC connector pin 6 instead LA_LNA1 .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_exp.png :width: 300 - Figure 10. I2C expander + Figure 19. I2C expander Connected LA_I2C to FPC connector instead GND pins via 0R resistors. @@ -146,21 +260,21 @@ Renamed A1 line to EXP_GPA1 and connected to FPC connector pin 6 instead LA_LNA1 .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_rfctl.png :width: 300 - Figure 11. RFCTL GPIO connector + Figure 20. RFCTL GPIO connector Changed GNSS power rail from VCC3P3_CLK to VCC3P3 to minimize GNSS module spurs in RF TX. ESD fitted. .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_gnss.png :width: 300 - Figure 12. GNSS + Figure 21. GNSS Added secure key option (NF due to I2C address conflict with switching regulator). .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_seckey.png :width: 300 - Figure 13. I2C secure key storage + Figure 22. I2C secure key storage Fitted ESDs (TXA, RXA, RXB, GNSS_ANT) @@ -176,7 +290,7 @@ Fitted ESDs (TXA, RXA, RXB, GNSS_ANT) .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_changes_esd4.png :width: 300 - Figure 14. I2C secure key storage + Figure 23. I2C secure key storage v1.0 diff --git a/docs/reference/M.2/index.rst b/docs/reference/M.2/index.rst index fa30d3c..130df96 100644 --- a/docs/reference/M.2/index.rst +++ b/docs/reference/M.2/index.rst @@ -8,6 +8,7 @@ Please ensure to select the correct version for your hardware and see the change .. toctree:: :maxdepth: 1 + v1.2 v1.1 v1.0 changelog \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/BB_CON.rst b/docs/reference/M.2/v1.2/BB_CON.rst new file mode 100644 index 0000000..e4d8cb4 --- /dev/null +++ b/docs/reference/M.2/v1.2/BB_CON.rst @@ -0,0 +1,144 @@ +Baseband connectors +################### + +Baseband signals can be accessed +via 0.3mm pitch 15 pin FPC connectors. NXP base band processors RX observation external connector (X7) pinout is shown in Table 5. +LMS7002M TX ADC connector (X6) pinout is shown in Table 6. + + +.. list-table:: Table 5. Basedand processors RX obeservation external BB 15-pin FPC connector (X7) + :header-rows: 1 + :stub-columns: 1 + + * - Pin + - Schematic signal name + - Description + + * - 1 + - GND + - Ground + + * - 2 + - LA_RO0_EXT_I_P + - Channel 1 in-phase signal differential positive + + * - 3 + - LA_RO0_EXT_I_N + - Channel 1 in-phase signal differential negative + + * - 4 + - GND + - Ground + + * - 5 + - LA_RO0_EXT_Q_P + - Channel 1 quadrature signal differential positive + + * - 6 + - LA_RO0_EXT_Q_N + - Channel 1 quadrature signal differential negative + + * - 7 + - GND + - Ground + + * - 8 + - VCC3P3 + - Power (3.3 V) + + * - 9 + - GND + - Ground + + * - 10 + - LA_RO1_EXT_I_P + - Channel 2 in-phase signal differential positive + + * - 11 + - LA_RO1_EXT_I_N + - Channel 2 in-phase signal differential negative + + * - 12 + - GND + - Ground + + * - 13 + - LA_RO1_EXT_Q_P + - Channel 2 quadrature signal differential positive + + * - 14 + - LA_RO1_EXT_Q_N + - Channel 2 quadrature signal differential negative + + * - 15 + - GND + - Ground + + +.. list-table:: Table 6. LMS7002M TX BB ADC 15-pin FPC connector (X6) + :header-rows: 1 + :stub-columns: 1 + + * - Pin + - Schematic signal name + - Description + + * - 1 + - GND + - Ground + + * - 2 + - LMS_TX2_BB_I_P + - Channel 2 in-phase signal differential positive + + * - 3 + - LMS_TX2_BB_I_N + - Channel 2 in-phase signal differential negative + + * - 4 + - GND + - Ground + + * - 5 + - LMS_TX2_BB_Q_P + - Channel 2 quadrature signal differential positive + + * - 6 + - LMS_TX2_BB_Q_N + - Channel 2 quadrature signal differential negative + + * - 7 + - GND + - Ground + + * - 8 + - VCC3P3 + - Power (3.3 V) + + * - 9 + - GND + - Ground + + * - 10 + - NC + - No connection + + * - 11 + - NC + - No connection + + * - 12 + - GND + - Ground + + * - 13 + - NC + - No connection + + * - 14 + - NC + - No connection + + * - 15 + - GND + - Ground \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/M_2.rst b/docs/reference/M.2/v1.2/M_2.rst new file mode 100644 index 0000000..26c40a8 --- /dev/null +++ b/docs/reference/M.2/v1.2/M_2.rst @@ -0,0 +1,164 @@ +M.2 edge connector +################## + +LimeSDR Micro M.2 2280 v1.2 board communicates with the host system via M.2 edge connector. +It is configured to use PCIE-based SSD drive pinout when sloted into key M+B socket, +but is also compatible with key M and key B sockets. + +LimeSDR Micro M.2 2280 v1.0 connector pinout and signals according to the specification is given in Table 14. + +.. table:: Table 14. M.2 key M+B PCIe-based SSD edge connector pinout + + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | **Pin** | **M.2 PCIe Specification** | **LimeSDR Micro M.2 2280 Schematic signal name** | **Description** | + +=========+==============================+====================================================+===========================================================+ + | 1 | CONFIG_3 = GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 2 | 3.3 V | VCC3P3_M.2 | Main power input 3.3 V (VCC3P3_M.2) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 3 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 4 | 3.3 V | VCC3P3_M.2 | Main power input 3.3 V (VCC3P3_M.2) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 5 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 6 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 7 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 8 | PLN# (I)(0/1.8/3.3V) | PCIE_W_DISABLE1# | Wireless disable | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 9 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 10 | LED_1# (O)(OD) | M.2_LED1# | PCIe activity indication (can be routed to onboard LED) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 11 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 12 | | + +---------+ | + | 13 | | + +---------+ | + | 14 | | + +---------+ | + | 15 | | + +---------+ ADD-IN CARD KEY B | + | 16 | | + +---------+ | + | 17 | | + +---------+ | + | 18 | | + +---------+ | + | 19 | | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 20 | NC | M.2_LNA1_EN | Low-noise amplifier enable (output) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 21 | CONFIG_0 = GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 22 | NC | M.2_PA_EN | Power amplifier enable (output) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 23 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 24 | NC | M.2_CLK_OUT | Reference clock output | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 25 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 26 | NC | PCIE_W_DISABLE2# | Wireless disable | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 27 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 28 | PLA_S2# (O) (0/1.8V)) | M.2_CLK_IN | Reference clock input | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 29 | PETn1 | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 30 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 31 | PETp1 | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 32 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 33 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 34 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 35 | PERn1 | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 36 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 37 | PERp1 | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 38 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 39 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 40 | SMB_CLK (I/O)(0/1.8V) |M.2_SMB_CLK | SMBus clock signal (LA9310 I2C clock signal) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 41 | PETn0 | PCIE_PET0_N | PCIe data input | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 42 | SMB_DATA (I/O)(0/1.8V) | M.2_SMB_DATA | SMBus data signal (LA9310 I2C data signal) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 43 | PETp0 | PCIE_PET0_P | PCIe data input | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 44 | ALERT# (O)(0/1.8V) | M.2_GPIO_2 | BB processor general puprose I/O | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 45 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 46 | NC | M.2_PPS_IN | PPS input | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 47 | PERn0 | PCIE_PER0_N | PCIe data output | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 48 | NC | M.2_PPS_OUT | PPS output | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 49 | PERp0 | PCIE_PER0_P | PCIe data output | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 50 | PERST# (I)(0/1.8V/3.3V) | PCIE_PERST# | PCIE reset | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 51 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 52 | CLKREQ# (I/O)(0/1.8V/3.3V) | CLK_REQUEST# | PCIe clock request | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 53 | REFCLKn | PCIE_REF_CLK_N | PCIe reference clock | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 54 | PEWAKE# (I/O)(0/1.8V/3.3V) | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 55 | REFCLKp | PCIE_REF_CLK_P | PCIe reference clock | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 56 | Reserved for MFG_DATA |M.2_TRX1 | TDD control output | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 57 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 58 | Reserved for MFG_CLOCK | M.2_MFG | LA9310 processor general puprose I/O (GPIO_05) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 59 | | + +---------+ | + | 60 | | + +---------+ | + | 61 | | + +---------+ | + | 62 | | + +---------+ ADD-IN CARD KEY M | + | 63 | | + +---------+ | + | 64 | | + +---------+ | + | 65 | | + +---------+ | + | 66 | | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 67 | NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 68 | SUSCLK (I)(0/1.8V/3.3V) | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 69 | CONFIG_1 = NC | NC | No connection | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 70 | 3.3 V | VCC3P3_M.2 | Main power input 3.3 V (VCC3P3_M.2) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 71 | GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 72 | 3.3 V | VCC3P3_M.2 | Main power input 3.3 V (VCC3P3_M.2) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 73 | VIO_CFG (O) | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 74 | 3.3 V | VCC3P3_M.2 | Main power input 3.3 V (VCC3P3_M.2) | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ + | 75 | CONFIG_2 = GND | GND | Ground | + +---------+------------------------------+----------------------------------------------------+-----------------------------------------------------------+ diff --git a/docs/reference/M.2/v1.2/clock.rst b/docs/reference/M.2/v1.2/clock.rst new file mode 100644 index 0000000..89f4c07 --- /dev/null +++ b/docs/reference/M.2/v1.2/clock.rst @@ -0,0 +1,78 @@ +Clock Distribution +################## + +LimeSDR Micro M.2 2280 v1.2 board clock distribution block diagram is as shown in Figure 7. + +.. figure:: /images/LimeSDR-Micro_M.2_v1.1_diagrams_r0_clock.png + :width: 600 + + Figure 7. LimeSDR Micro M.2 2280 v1.2 board clock distribution block diagram + +LimeSDR Micro M.2 2280 v1.2 board features an on board 30.72 MHz VCTCXO as the reference clock for +LMS7002M RF transceiver. + +Rakon E6245LF 30.72 MHz voltage controlled temperature compensated crystal oscillator (VCTCXO) +is the clock source for the board. VCTCXO frequency may be tuned by using 16 bit DAC (IC18). +Main VCTCXO parameters are listed in Table 7. + +.. list-table:: Table 7. Rakon E7355LF VCTCXO main parameters + :header-rows: 1 + + * - Frequency parameter + - Value + * - Calibration (25°C ± 1°C) + - ± 1 ppm max + * - Stability (-40 to 85 °C) + - ± 50 ppb max + * - Long term stability (first year) + - ± 2 ppm max, ± 1.5 ppm max + * - Control voltage range + - 0.5 V .. 2.5 V + * - Frequency tuning + - ± 5 ppm + * - Slope + - +7.5 ppm/V + +Clock buffer (IC16) gives option to select clock source from +onboard VCTCXO clock XO1 (CLK_XO) and external MHF4 (J4)/M.2 (X9) sources (CLK_IN). Buffered clock signal +(LMK_CLKOUT1 and LMK_CLKOUT7) can also be fed to other board using MHF4 (XJ2)/M.2 (X9) connectors. + +The board clock lines and other related signals/information are listed in Table 8. + +.. table:: Table 8. Main clock lines + + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | **Source** | **Schematic signal name** | **I/O standard** | **Description** | + +======================+===========================+==================+=====================================================+ + | External (J4) | CLK_IN | 3.3V | External reference clock input (MHF4) | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | External (J6) | ADF_REF_IN | 3.3V | External phase detector input (MHF4) | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | Clock buffer (IC16) | LMK_CLKOUT1 | 3.3V | Reference clock output (MHF4) | + | +---------------------------+------------------+-----------------------------------------------------+ + | | LMK_CLKOUT7 | 1.8V | Reference clock output (M.2) | + | +---------------------------+------------------+-----------------------------------------------------+ + | | LMS_TxPLL_CLK | 1.8V | Reference clock connected to LMS (TX) | + | +---------------------------+------------------+-----------------------------------------------------+ + | | LMS_RxPLL_CLK | 1.8V | Reference clock connected to LMS (RX) | + | +---------------------------+------------------+-----------------------------------------------------+ + | | ADF_RF_IN | 3.3V | Reference clock connected to ADF (phase detector) | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | VCTCXO (XO1) | CLK_XO | 3.3V | Onboard reference clock | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | | PCIE_REF_CLK_P | | | + | External (X9) +---------------------------+ 1.8V (diff) | PCIe (M.2) reference clock | + | | PCIE_REF_CLK_N | | | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | RF tranceiver (IC1) | LMS_MCLK1 | 3.3V | Reference clock connected to BB processor | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | GNSS Receiver (IC11) | GNSS_1PPS | 3.3V | PPS output from GNSS receiver for BB processor | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | External (J5) | EXT_PPS_IN | 3.3V | External PPS input (MHF4) | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | External (x9) | M.2_PPS_IN | 3.3V | External PPS input (M.2) | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ + | BB processor (IC6) | M.2_PPS_OUT | 3.3V | M.2 PPS output | + | +---------------------------+------------------+-----------------------------------------------------+ + | | EXT_PPS_OUT | 3.3V | External PPS output (J5) | + +----------------------+---------------------------+------------------+-----------------------------------------------------+ diff --git a/docs/reference/M.2/v1.2/digital.rst b/docs/reference/M.2/v1.2/digital.rst new file mode 100644 index 0000000..9d6db93 --- /dev/null +++ b/docs/reference/M.2/v1.2/digital.rst @@ -0,0 +1,106 @@ +RF Transceiver Digital +###################### + +The `LMS7002M`_ digital interface and control signals are described below. + +Digital Interface +***************** + +LMS7002 is using baseband signals (I and Q) to transfer data to/from the NXP Baseband processor: + +* TX signals LMS_TX1_BB_I/Q_P/N where I/Q indicates in-phase and quadrature signals and P/N indicates differential positive and negative pairs. +* RX signals LMS_RX1/2_BB_I/Q_P/N where RX1/2 indicates RF channel 1 or 2, I/Q indicates I and Q signals and P/N indicates differential positive and negative pairs. + + +Control +******* + +These signals are used for the following functions within the LMS7002 RFIC: + +* LMS_RXEN,receiver enable/disable signal is not controlled and is connected to VDIO_LMS (3.3V) power rail. +* LMS_TXEN – transmitter enable/disable signal connected to BB processor pin M15 via level converter (3.3V). +* LMS_RESET – LMS7002M reset is connected to I2C GPIO expander (IC14) GPA0 pin. +* SPI Interface: LMS7002M transceiver is configured via 4-wire SPI interface: LA_SPI_SCLK, LA_SPI_MOSI, LA_SPI_MISO, LA_SPI_LMS_SS. The SPI interface is connected to BB processor via level converter IC8. +* LMS I2C Interface: can be used for LMS EEPROM content modification or debug purposes. The signals LMS_I2C_SCL and LMS_I2C_DATA are connected to EEPROM. They can be also connected to BB processors LA_I2C_SCL and LA_I2C_SDA. + + +LMS7002M Pins +************* + +.. table:: Table 2. LMS7002M RF transceiver signals + + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | **Chip pin (IC1)** | **Chip reference (IC1)** | **Schematic signal name** | | | **Comment** | + | | | | **BB processor** | **BB processor** | | + | | | | | | | + | | | | **pin (IC6)** | **reference (IC6)** | | + +======================+============================+=============================+=======================+==========================+==============================================+ + | AB34 | MCLK1 | LMS_MCLK1 | F1 | DCS_CLK_P | DCS_CLK_P | + | | | +-----------------------+--------------------------+----------------------------------------------+ + | | | | F2 | DCS_CLK_N | DCS_CLK_N | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | D28 | SEN | LA_SPI_LMS_SS | P7 | SPI_CS0_B | SPI signals connected via level translator | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | C29 | SCLK | LA_SPI_SCLK | P8 | SPI_CLK | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | F30 | SDIO | LA_SPI_MOSI | R9 | SPI_MOSI | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | F28 | SDO | LA_SPI_MISO | P8 | SPI_MISO | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | D26 | SDA | LMS_I2C_SDA | P6 (NC) | IIC1_SDA | | + | | | | | | BB processor and LMS7002M I2C signals | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | C27 | SCL | LMS_I2C_SCL | R6 (NC) | IIC1_SCL | are not connected by default | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | T4 | tbbip_pad_1 | LMS_TX1_BB_I_P | A7 | TX_I_P | RF channel 1 TX baseband I data | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | R5 | tbbin_pad_1 | LMS_TX1_BB_I_N | B7 | TX_I_N | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | R3 | tbbqp_pad_1 | LMS_TX1_BB_Q_P | A9 | TX_Q_P | RF channel 1 TX baseband Q data | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | P2 | tbbqn_pad_1 | LMS_TX1_BB_Q_N | B9 | TX_Q_N | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | V2 | tbbip_pad_2 | LMS_TX2_BB_I_P | | | Connected toX6 pin 2 (RF2 TX NC) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | T6 | tbbin_pad_2 | LMS_TX2_BB_I_N | | | Connected to X6 pin 3 (RF2 TX NC) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | U3 | tbbqp_pad_2 | LMS_TX2_BB_Q_P | | | Connected to X6 pin 5 (RF2 TX NC) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | U1 | tbbqn_pad_2 | LMS_TX2_BB_Q_N | | | Connected to X6 pin 6 (RF2 TX NC) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | Y6 | rbbip_pad_1 | LMS_RX1_BB_I_P | B4 | RX0_I_P | RF channel 1 RX baseband I data | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | AB2 | rbbin_pad_1 | LMS_RX1_BB_I_N | A4 | RX0_I_N | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | AB4 | rbbqp_pad_1 | LMS_RX1_BB_Q_P | A6 | RX0_Q_P | RF channel 1 RX baseband Q data | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | AA5 | rbbqn_pad_1 | LMS_RX1_BB_Q_N | B6 | RX0_Q_N | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | AD2 | rbbip_pad_2 | LMS_RX2_BB_I_P | A10 | RX1_I_P | RF channel 2 RX baseband I data | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | AC3 | rbbin_pad_2 | LMS_RX2_BB_I_N | B10 | RX1_I_N | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | AC5 | rbbqp_pad_2 | LMS_RX2_BB_Q_P | B12 | RX1_Q_P | RF channel 2 RX baseband Q data | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+ | + | AB6 | rbbqn_pad_2 | LMS_RX2_BB_Q_N | A12 | RX1_Q_N | | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | E5 | xoscin_tx | LMS_TX_CLK | | | Connected to 30.72 MHz clock | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | AM24 | xoscin_rx | LMS_RxPLL_CLK | | | Connected to 30.72 MHz clock | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | E27 | RESET | LMS_RESET | | | I/O expander GPA0 | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | U29 | TXEN | LMS_TXEN | | | Pulled-up by R11 | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | V34 | RXEN | LMS_RXEN | | | Pulled-up by R12 | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | U33 | CORE_LDO_EN | LMS_CORE_LDO_EN | | | Pulled-down by R15 | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | V30 | LOGIC_RESET | | | | GND | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | B22 | tstao | LMS_TSTAO | | | Test pin connected to J2 via R230 (NF) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | D22 | tstdo<0> | LMS_TSTDO0 | | | Test pin connected to J2 via R231 (NF) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ + | F22 | tstdo<1> | LMS_TSTDO1 | | | Test pin connected to J2 via R232 (NF) | + +----------------------+----------------------------+-----------------------------+-----------------------+--------------------------+----------------------------------------------+ \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/gpio.rst b/docs/reference/M.2/v1.2/gpio.rst new file mode 100644 index 0000000..4f1444c --- /dev/null +++ b/docs/reference/M.2/v1.2/gpio.rst @@ -0,0 +1,65 @@ +GPIO Connector +############## + +Three base band processors RF control/GPIOs and one I2C GPIO expander pin are connected +to 8 pin FPC connector (X8). Additionaly one pin is dedicated for power (3.3V) and every other pin +is ground as shown in table 13. + + +.. list-table:: Table 13. RFCTL/ GPIOs connector (X8) pins + :header-rows: 1 + :stub-columns: 1 + + * - Connector pin + - Schematic signal name + - BB processor pin + - I/O standard + - Comment + + * - 1 + - VCC3P3 + - + - 3.3V + - Power (3.3V) + + * - 2 + - LA_TRX1 + - M14 + - 3.3V + - TXRX1/GPIO8 + + * - 3 + - RF_I2C_SCL + - P6 + - 3.3V + - IIC1_SCL/GPIO_02 + + * - 4 + - LA_PA_EN + - P14 + - 3.3V + - PA_EN/GPIO12 + + * - 5 + - RF_I2C_SDA + - R6 + - 3.3V + - IIC1_SDA/GPIO_01 + + * - 6 + - EXP_GPA1 + - GPIO EXP (GPA1) + - 3.3V + - I2C GPIO expander + + * - 7 + - GND + - + - 3.3V + - Ground + + * - 8 + - EXP_GPA2 + - GPIO EXP (GPA2) + - 3.3V + - I2C GPIO expander \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/index.rst b/docs/reference/M.2/v1.2/index.rst new file mode 100644 index 0000000..8b83400 --- /dev/null +++ b/docs/reference/M.2/v1.2/index.rst @@ -0,0 +1,30 @@ +v1.2 +#### + +.. toctree:: + :maxdepth: 3 + :hidden: + + overview + digital + rfcontrol + BB_CON + clock + leds + peripheralinterfaces + jtag + gpio + M_2 + power + +This is the Reference Manual for LimeSDR Micro M.2 2280 v1.2 hardware. + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_3D_top.png + :width: 600 + + Figure 1: LimeSDR Micro M.2 2280 v1.2 board top view + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_3D_bot.png + :width: 600 + + Figure 2: LimeSDR Micro M.2 2280 v1.2 board bottom view diff --git a/docs/reference/M.2/v1.2/jtag.rst b/docs/reference/M.2/v1.2/jtag.rst new file mode 100644 index 0000000..a51a47a --- /dev/null +++ b/docs/reference/M.2/v1.2/jtag.rst @@ -0,0 +1,77 @@ +JTAG +#### + +To debug Baseband processors design 10-pin 0.05" pitch JTAG connector is used (J1). +It is located on the PCB top side (see :ref:`target-LimeSDR-Micro_M.2_2280_v1.2_components_top.png`) and is not populated by default. +JTAG connector pins, schematic signal names and I/O standards are listed +in Table 12. + +.. list-table:: Table 12. JTAG connector X9 pins + :header-rows: 1 + :stub-columns: 1 + + * - Connector pin + - Schematic signal name + - BB processor pin + - I/O standard + - Comment + + * - 1 + - VCC1P8 + - + - 1.8V + - Power (1.8V) + + * - 2 + - LA_TMS + - M12 + - 1.8V + - Test Mode Select + + * - 3 + - GND + - + - + - Ground + + * - 4 + - LA_TCK + - N10 + - 1.8V + - Test Clock + + * - 5 + - GND + - + - + - Ground + + * - 6 + - LA_TDO + - N12 + - 1.8V + - Test Data Output + + * - 7 + - NC + - + - + - No Connection + + * - 8 + - LA_TDI + - M10 + - 1.8V + - Test Data Input + + * - 9 + - GND + - + - + - Ground + + * - 10 + - JTAG_RST + - N8 + - 1.8V + - Reset \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/leds.rst b/docs/reference/M.2/v1.2/leds.rst new file mode 100644 index 0000000..61ffcf2 --- /dev/null +++ b/docs/reference/M.2/v1.2/leds.rst @@ -0,0 +1,31 @@ +LEDs +#### + +LimeSDR Micro Micro M.2 2280 v1.2 board comes with two green indicator LEDs. These LEDs are soldered on the top of the board near RF shield (right edge). + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_components_LEDs.png + :width: 600 + + Figure 8. LimeSDR Micro M.2 2280 v1.2 indication LEDs (top) + +LEDs are connected to baseband processors GPIOs hence their function may be programmed according to the user requirements. +Default LEDs configuration and description are shown in Table 9. + +.. list-table:: Table 9. Default LEDs configuration + :header-rows: 1 + + * - Board Reference + - Schematic Name + - Board Label + - BB Processor Pin + - Description + * - LED1 + - LA_LED1 + - LED1 + - R11 (GPIO_17) + - User defined + * - LED2 + - LA_LED2 + - LED2 + - P12 (GPIO_18) + - User defined diff --git a/docs/reference/M.2/v1.2/overview.rst b/docs/reference/M.2/v1.2/overview.rst new file mode 100644 index 0000000..c24ee35 --- /dev/null +++ b/docs/reference/M.2/v1.2/overview.rst @@ -0,0 +1,119 @@ +Overview +######## + +One of the key elements of LimeSDR Micro M.2 2280 board is NXP (`LA9310S7S11AA`_) base band processor. +It’s main function is to transfer digital data between LMS7002M RF transceiver and PC through a M.2 edge connector. +The block diagram for LimeSDR Micro M.2 2280 board is presented in the Figure 3. + +.. figure:: /images/LimeSDR-Micro_M.2_v1.1_diagrams_r0_BD.png + :width: 600 + + Figure 3: LimeSDR Micro M.2 2280 v1.2 board block diagram + +LimeSDR Micro M.2 2280 v1.2 board picture with highlighted connectors and main components are presented in Figure 4 and Figure 5, respectively. + +.. _target-LimeSDR-Micro_M.2_2280_v1.2_components_top.png: + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_components_top.png + :width: 600 + + Figure 4: LimeSDR Micro M.2 2280 v1.2 board top connectors and main components + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_components_bot.png + :width: 600 + + Figure 5: LimeSDR Micro M.2 2280 v1.2 board bottom connectors and main components + +Description of board components is given in the Table 1. + +.. table:: Table 1. Board components + + +----------------------------------------------------------------------------------------------------------------------------+ + | **Featured Devices** | + +=======================+================+===================================================================================+ + | **Board Reference** | **Type** | **Description** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC1 | RF transceiver | Lime Microsystems LMS7002M | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC6 | BB processor | NXP Semiconductors LA9310S7S11AA | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **Miscellaneous devices** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC10 | IC | Temperature sensor TMP1075NDRLR | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC14 | IC | I2C I/O expander MCP23017-E/ML | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **Configuration, Status and Setup Elements** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | J1 | JTAG header | BB processor programming ARM 10 pin 0.05" pitch header (not populated) | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | LED1, LED2 | Green LEDs | User defined BB processor indication green LEDs | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X8 | FPC connector | BB processor GPIOs/ RF controls | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **RF Circuitry** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC5 | IC | SPDT RF switch | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC3, IC4 | IC | SP4T RF switch | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X1, X2, X4 | MHF4 connector | RF connectors | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | J2 | MHF4 connector | RF control signal output (LA_PA_EN) | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X6 | FPC connector | LMS7002 base band TX DAC BB 15-pin FPC connector | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X7 | FPC connector | RX obeservation externa BB 15-pin FPC connector | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X8 | FPC connector | RF control connector | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **Memory Devices** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC2 | IC | I²C EEPROM Memory 128Kb (16K x 8), connected to LMS7002M RF transceiver I2C bus | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC13 | IC | I²C EEPROM Memory 512Kb (64K x 8), connected to BB processor I2C bus | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **Communication Ports** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X9 | M.2 connector | M.2 B+M key Edge connector (1x PCIe lane) | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **Clock Circuitry** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | XO1 | VCTCXO | 30.72 MHz Voltage Controlled Temperature Compensated Crystal Oscillator | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC21 | IC | Phase detector | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC16 | IC | Clock buffer | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC18 | IC | 16 bit DAC for VCTCXO (XO1) frequency tuning (default) | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC11 | IC | GNSS Receiver module | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC20, IC22 | IC | Logic level converters | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC17, IC19 | IC | Analogue switches | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | J4 | MHF4 connector | Reference clock input | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | J6 | MHF4 connector | Phase detector input | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | J3 | MHF4 connector | Reference clock output | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | J5 | MHF4 connector | 1PPS input / output | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | X5 | MHF4 connector | GNSS (active) antenna connector | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | **Power Supply** | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC26, IC30 | IC | Four-output switching regulator LP8758A1E0YFFR | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC23, IC27, IC28, IC29| IC | Linear regulator LD39100PUR | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + | IC31 | IC | Linear regulator AP7330 | + +-----------------------+----------------+-----------------------------------------------------------------------------------+ + +A more detailed description is provided in the following sections. + + + +.. _LA9310S7S11AA: https://www.nxp.com/part/LA9310S7S11AA \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/peripheralinterfaces.rst b/docs/reference/M.2/v1.2/peripheralinterfaces.rst new file mode 100644 index 0000000..140a65a --- /dev/null +++ b/docs/reference/M.2/v1.2/peripheralinterfaces.rst @@ -0,0 +1,80 @@ +Peripheral Interfaces +##################### + +Baseband processors SPI (LA_SPI) pins, schematic signal names and I/O standards/levels are shown in Table 10. + +.. list-table:: Table 10. LA_SPI interface pins + :header-rows: 1 + + * - Schematic signal name + - BB processor pin + - I/O standard + - Comment + + * - LA_SPI_SCLK + - P8 + - 3.3V + - Serial Clock (LA output) + + * - LA_SPI_MOSI + - R9 + - 3.3V + - Data (LA output) + + * - LA_SPI_MISO + - R8 + - 3.3V + - Data (LA input) + + * - LA_SPI_LMS_SS + - P7 + - 3.3V + - IC1 (LMS7002) SPI slave select (LA output) + + * - LA_SPI_ADF_SS_LS + - P11 + - 3.3V + - IC20 (ADF4002) SPI slave select (LA output) + +Baseband processors I2C (LA_I2C) +interface slave devices and related information are given in Table 11. + +.. list-table:: Table 11. LA_I2C interfaces pins + :header-rows: 1 + + * - I2C slave device + - Slave device + - I2C address + + * - IC10 + - Temperature sensor + - 1 0 0 1 0 1 1 RW + + * - IC13 + - EEPROM + - 1 0 1 0 0 0 0 RW + + * - IC14 + - I/O expander + - 0 1 0 0 0 0 0 RW + + * - IC18 + - XO DAC + - 1 0 0 1 1 0 0 RW + + * - IC25 + - Switching regulator + - 1 1 0 0 0 0 0 RW (I2C_SDA_SEL = 0) + + * - IC29 + - Switching regulator + - 1 1 0 0 0 0 0 RW (I2C_SDA_SEL = 1) + + * - IC15 (not populated) + - I2C secure key storage + - 1 1 0 0 0 0 0 RW + +Switching regulators (IC25 and IC29) share identical I2C address, switching between them +is done by I2C_SDA_SEL signal connected to I2C I/O expanders GPB3. + +Before populating I2C secure key storage (IC15) make sure to avoid identical address conflicts with switching regulators. \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/power.rst b/docs/reference/M.2/v1.2/power.rst new file mode 100644 index 0000000..85619f0 --- /dev/null +++ b/docs/reference/M.2/v1.2/power.rst @@ -0,0 +1,13 @@ +Power Distribution +################## + +LimeSDR Micro M.2 board is powered via M.2 edge connector (3.3V). +LimeSDR Micro M.2 board power delivery network consists of different power rails/voltages and +filters. + +LimeSDR Micro M.2 board power distribution block diagram is presented in Figure 10. + +.. figure:: /images/LimeSDR-Micro_M.2_v1.1_diagrams_r0_power.png + :width: 600 + + Figure 10. LimeSDR Micro M.2 2280 v1.2 board power distribution block diagram \ No newline at end of file diff --git a/docs/reference/M.2/v1.2/rfcontrol.rst b/docs/reference/M.2/v1.2/rfcontrol.rst new file mode 100644 index 0000000..828e189 --- /dev/null +++ b/docs/reference/M.2/v1.2/rfcontrol.rst @@ -0,0 +1,59 @@ +RF Network Control +################## + +RF network contains matching networks, RF switches and MHF4 connectors +(X1 - TX and X2, X4 - RX) as shown in Figure 6. + +.. figure:: /images/LimeSDR-Micro_M.2_v1.1_diagrams_r0_RF.png + :width: 600 + + Figure 6. LimeSDR Micro M.2 2280 v1.2 RF diagram + +LMS7002M RF transceiver TX and RX ports has dedicated matching network which determines the working frequency range. More detailed information on LMS7002M RF transceiver ports and matching network frequency ranges is listed in the Table 3. + +.. list-table:: Table 3. LMS7002M RF transceiver ports and matching networks frequency ranges + :header-rows: 1 + + * - RF transceiver port + - Frequency range + * - TX1_1 + - 3.3 GHz - 3.8 GHz + * - TX1_2 + - 0.03 GHz - 1.9 GHz + * - RX1_H, RX2_H + - 3.3 GHz - 3.8 GHz + * - RX1_W, RX2_W + - 0.7 GHz - 2.6 GHz + * - RX1_L, RX2_L + - 0.3 GHz - 2.2 GHz + +Onboard RF network switches are controlled via 2.4V logic signals. +This is achieved by resistor dividers connected between I2C GPIO expander (TX_SW, RX_SW2, RX_SW3) and switch +control pin (TX_SW_DIV, RX_SW2_DIV, RX_S3_DIV). + +Connectors X8 and J2 offers 3.3V logic control signals for external RF front end control. + +RF network control signals are described in the Table 4. + + +.. table:: Table 4. RF network control signals + + +-----------------------------+-----------------------------+------------------+-----------------+--------------------------------------------------------+ + | **Component** | **Schematic signal name** | **I/O standard** | **Pin** | **Description** | + +=============================+=============================+==================+=================+========================================================+ + | SKY13330-397LF(IC5) | TX_SW/TX_SW_DIV | 3.3V | P15 (LA) | 3.3V logic level signal divided to 2.4V logic level. | + +-----------------------------+-----------------------------+------------------+-----------------+--------------------------------------------------------+ + | SKY13414-485LF(IC3 and IC4) | RX_SW2/RX_SW2_DIV | 3.3V | GPB0 (expander) | 3.3V logic level signal divided to 2.4V logic level. | + | +-----------------------------+------------------+-----------------+--------------------------------------------------------+ + | | RX_SW3/RX_SW3_DIV | 3.3V | GPB2 (expander) | 3.3V logic level signal divided to 2.4V logic level. | + +-----------------------------+-----------------------------+------------------+-----------------+--------------------------------------------------------+ + | J2 | LA_PA_EN | 3.3V | P14 (LA) | RF control signal output | + +-----------------------------+-----------------------------+------------------+-----------------+--------------------------------------------------------+ + | X8 | LA_TRX1 | 3.3V | P15 (LA) | RF control signal output | + | +-----------------------------+------------------+-----------------+ | + | | LA_PA_EN | 3.3V | P14 (LA) | | + | +-----------------------------+------------------+-----------------+ | + | | EXP_GPA1 | 3.3V | GPA1 (expander) | | + | +-----------------------------+------------------+-----------------+ | + | | EXP_GPA2 | 3.3V | GPA2 (expander) | | + +-----------------------------+-----------------------------+------------------+-----------------+--------------------------------------------------------+ diff --git a/docs/user/M.2/clock.rst b/docs/user/M.2/clock.rst index 2f61d6a..cb4a7bd 100644 --- a/docs/user/M.2/clock.rst +++ b/docs/user/M.2/clock.rst @@ -1,7 +1,7 @@ Reference Clock ############### -The LimeSDR Micro M.2 clock system is based on a high stability 30.72 MHz VCTCXO (Voltage Controlled Temperature Compensated Crystal Oscillator) which can be tuned via an external 1PPS reference signal or GPSDO function. +The LimeSDR Micro M.2 2280 clock system is based on a high stability 30.72 MHz VCTCXO (Voltage Controlled Temperature Compensated Crystal Oscillator) which can be tuned via an external 1PPS reference signal or GPSDO function. The board provides reference clock and 1PPS input and output via M.2 connector, as well as dedicated MHF4 connectors for reference clock input (J4), output (J3) and 1PPS input/output (J5). @@ -33,9 +33,8 @@ The board provides reference clock and 1PPS input and output via M.2 connector, .. note:: By default 1PPS input source is onboard GNSS receiver. To change 1PPS input source: - For LimeSDR Micro M.2 v1.1 remove R176 and populate R173 (M.2) or R179 (MHF4 J5) with zero-ohm resistor. - - For LimeSDR Micro M.2 v1.0 remove R175 and populate R172 (M.2) or R178 (MHF4 J5) with zero-ohm resistor. + * For LimeSDR Micro M.2 v1.1 and v1.2 remove R176 and populate R173 (M.2) or R179 (MHF4 J5) with zero-ohm resistor. + * For LimeSDR Micro M.2 v1.0 remove R175 and populate R172 (M.2) or R178 (MHF4 J5) with zero-ohm resistor. .. warning:: When using external clock references, ensure signal levels and frequencies match specifications. diff --git a/docs/user/M.2/setup.rst b/docs/user/M.2/setup.rst index 0fb6082..b4a013b 100644 --- a/docs/user/M.2/setup.rst +++ b/docs/user/M.2/setup.rst @@ -4,9 +4,9 @@ Hardware Setup Host Interface ************** -LimeSDR Micro should be plugged into a M.2 slot with B, M or B+M key on the host device. +LimeSDR Micro can be plugged into a M.2 slot with B or M key on the host device. -The host must provide a PCIe Gen3 x1 interface and supply power via the M.2 connector. +The host must provide a PCIe Gen3 x1 interface and supply power (3.3 V) via the M.2 connector. Cooling ******* @@ -24,7 +24,7 @@ RF Connections .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_components_rfcon.png :width: 600 - Figure 4: LimeSDR Micro M.2 v1.x board top with RF connector positions + Figure 4: LimeSDR Micro M.2 2280 v1.x board top with RF connector positions .. table:: Table 1. RF Connectors @@ -49,7 +49,7 @@ RF Connections +--------------+----------------+---------+--------------------+-----------------------------------------+ .. note:: - TDD control signal (PA_EN) output (J2) is only available in LimeSDR Micro M.2 v1.1. + TDD control signal (PA_EN) output (J2) is only available in LimeSDR Micro M.2 v1.1 and v1.2. .. warning:: Care should be taken when connecting external RF signals to the RX inputs, to ensure that the maximum safe input power of +10 dBm is not exceeded, as this may cause permanent damage to the device. diff --git a/docs/user/M.2/software.rst b/docs/user/M.2/software.rst index 82b289d..8b56adc 100644 --- a/docs/user/M.2/software.rst +++ b/docs/user/M.2/software.rst @@ -1,7 +1,7 @@ Software ######## -LimeSDR Micro is supported by the :external+suiteng:ref:`Lime Suite NG software `, which provides drivers, command line utilities, plug-ins for popular ecosystem applications, and a graphical user interface (GUI) application for advanced engineering/debugging tasks. +LimeSDR Micro M.2 2280 is supported by the :external+suiteng:ref:`Lime Suite NG software `, which provides drivers, command line utilities, plug-ins for popular ecosystem applications, and a graphical user interface (GUI) application for advanced engineering/debugging tasks. For a guide to getting up and running with Lime Suite NG, please refer to the :external+quickstart:ref:`SDR Quick Start `. diff --git a/docs/user/M.2/versions.rst b/docs/user/M.2/versions.rst index fa5d0c0..700b513 100644 --- a/docs/user/M.2/versions.rst +++ b/docs/user/M.2/versions.rst @@ -1,16 +1,21 @@ Board Versions ############## -There are currently two versions of the LimeSDR Micro M.2 board: v1.0 and v1.1. +There are currently two versions of the LimeSDR Micro M.2 board: v1.0, v1.1 and v1.2. -v1.0 and v1.1 boards should be treated the same in terms of hardware functionality and software support. +v1.0, v1.1 and v1.2 boards should be treated the same in terms of hardware functionality and software support. + +.. figure:: /images/LimeSDR-Micro_M.2_2280_v1.2_3D_top.png + :width: 600 + + Figure 1: LimeSDR Micro M.2 v1.2 board top view .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.1_3D_top.png :width: 600 - Figure 1: LimeSDR Micro M.2 v1.1 board top view + Figure 2: LimeSDR Micro M.2 v1.1 board top view .. figure:: /images/LimeSDR-Micro_M.2_2280_v1.0_3D_top.png :width: 600 - Figure 2: LimeSDR Micro M.2 v1.0 board top view \ No newline at end of file + Figure 3: LimeSDR Micro M.2 v1.0 board top view \ No newline at end of file