From 88a4711593f6442a87fc13c412047bd139513627 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Tue, 6 Feb 2024 15:30:55 +0100 Subject: [PATCH] Use servile as base for serving --- doc/reservoir.rst | 1 + doc/serving.png | Bin 0 -> 9392 bytes doc/serving.rst | 94 +++++++++++++++ serving.core | 4 +- serving/serving.v | 241 ++++++++++++-------------------------- serving/serving_arbiter.v | 57 --------- serving/serving_mux.v | 66 ----------- serving/serving_ram.v | 54 ++------- 8 files changed, 178 insertions(+), 339 deletions(-) create mode 100644 doc/serving.png create mode 100644 doc/serving.rst delete mode 100644 serving/serving_arbiter.v delete mode 100644 serving/serving_mux.v diff --git a/doc/reservoir.rst b/doc/reservoir.rst index 5bc58d9c..306473e1 100644 --- a/doc/reservoir.rst +++ b/doc/reservoir.rst @@ -7,4 +7,5 @@ A CPU is only as good as its eosystem. In order to make use of SERV, it needs to Welcome to the reservoir, a pool of ready-made designs and subsystems for different purpsoses that you can use to quickly get started with SERV or integrate it into larger designs. .. include:: servile.rst +.. include:: serving.rst .. include:: servant.rst diff --git a/doc/serving.png b/doc/serving.png new file mode 100644 index 0000000000000000000000000000000000000000..338106c84374bea9340f24ff848ce73b14657255 GIT binary patch literal 9392 zcmXw92|SeD_aBs9LiX$_Ta1~puY(x|!`O%HW-$z78D@~8LKKoEOEiR}NOomQWQjtS ztQ9GHc3IMY-uM0eKcAU-p6A?qzR$Ve`<(lnd(I@HtW3GsMc4rV02ji{#FlX83rA>ni=RiKtKP@djmiuLg)(KSIp zRUrMNN*BQiAy^!Vt_D|C{TJ{b^RQ$u{C}neYr!$$U>wwkL=Lv2`hYc%SjYcN3de?o z5=epn8v$5ZRT=zW134lH`=1np4JY_u|B-@Wbawtn10A36zkw5>mcBrLXDCU_86O-- z^udr(8vlU=dIkIs1VtbFWxA#RfM_`4yuE{w6c`HVWk$53Mq-_)<}i>K*vl)}pM=rE zgc?H~ovm$s9Q^D;v^1#!P-7!2B00z(L<+|`6SZ7Iog)JSk(#g|lB%DLrllX*oJ2)a zkyefwsW{4F+Ot1YmcO_&Rs1hRsM(65Y4 z?U5Fw2vd#V2&#o|grh&y2|=G|IN4OqM3n?5+D8WANpzawa9=`jU?`gGghmF?i81mE zcXTjCV$JEN=1x#GZyZ_^6{vy0tGf{CB2D_#8G%e7_9$zkV4R;h31!0}lD0X3J zsx#S-=n!aa6-q<}d6}uZgb+0dNP?!Z3p_ByJ`9hJgd%+5_8_AGiV2iJbO1WLSb{9b z*0>0eRhY30#5z({6-KnjhM2=5;c#Ry+!o;*WF88II@#D5X_#4?`I}g%BZB`K2F^4X z@2{qYN8n6@OoAy;i%3%_{kbSt~m?u-RmI%%ng zT7Yrpk>PXz6bY%WMzo>$YvKu5AQfi^cX6<>A(Eg$<{^-99468N;-YRBYU)Vxf)5KLWuLf;Q3ecQVqnvvdMFqNoUasut0~P%tvU7Hq2OhjoFVHA&7sE@(}4N4ldMnUj3+I7p=9Kl28U!1>#&12y2N z&=Au=bsr=-936I-zPQ1Xvf4qT#jcoxQ#VHp&Z0~VBLx|lOwK}ILF5@2 z5^vmyk%X6%-vA2DwqH}`l=Ehyb!vVMM7{29)xv*3gyVnAG;Lqgp{!5eXXvzGRj-Iq z6Y>X)S%V$_+@wZ5VcwLnP@!?Cc;RHHGOFv-5h9^22oyw+fO`2MHKFr+{t> zc@g&|__yhWF`X>#Rfb%?w$BN5ciY+wEOQ}j3idRgC;NhYw8^oaQ)TKWgryezM^)-d z1^2gKZRvz;8MMDQ_U~sVGDkq}Y4&q56E%3_LZi4^-SNTJi-vVCr~Xx1%g?6rh(LtS z;6J*T6gv6@V7UkPH*WS`yLPRLy6Mfz#x`_lX?&CiaKJUdbc+Qpw7%=S_kr7UXAx^j zEFLa`ah0K83h_xTHRBJaoujlLuTK+JRi*Wk8ut{#=Q<n2-*TtaH zwFzWbTioT%2)SIDt2xlhh?+CY*EY^McN3d^nr86LAX7jIeGivmv}fVZXn%m+?@YOL zM(<@->nRlDrPy=tg&BR>p11w%Nn`rRuOns5T(EXS$T&F=%V?i7FAQpC_^t&8Cb0P@^X14)j_TFmOMQr~7dUvwwQJ+QhD>#$~ zQ2-S2xkRycu|rJ5!hnXH9Al*`;>KLp%{N~RqRP7^G=ZbB=lN*WPCdcRm2OXHVdLS< zgK22f{nZIRX_?;JZ;tw^vEZRO>HZ^Di%aKDpSoqd(AVYlK8rgJ*U8j8C>f}}RVPON zy&=0XWcps%(9|n=Y38*CYWJNj%@A~o1^kx1X0bgs2dq&g10@o#Qx6t+@5#Qm(^IKuFl`*%3gslvVtunISeKwTJ zEEIdEu|U&Ucvo5{>I|v1D`_|8(~}pPvO~g#5i#RFl@|@e7#IH>?dSNrWGOiV^e`KY z;ewbC4~6|k%VnEWsxwWR1s$`iAj9`GzPL6`8a=f=?X|o7?cOEp6nm$DiE6!hpaq@T zs;*OIR)DqXCNQU{I;Z&q0PpD+(qdto&1qy z+-eFoMS^_6U~C`jY4-0>wx3V$%c*XHS*$hyFIZOk#q6JmWpMt|2$;Mzdx-b^+8$dK zzUI>W=~xh%vkVM&D$aIsPl@&gwTG<6%qGv-Xg{fd?w*&xqxwT z4 z!h1*F#MUa1?|!^0b-N|{NSVA05l)pj5^fSz?=&>&G+7*a%;OTY8KKtX6J#&hxTu8 z!PAVsFTJ5-{vx)z{PIRTl3?~Gt4A&O=^js_B;#%GX%s-E1LnQ(n>KK)^ zdmVXuOI0dTALvkYE`B&8%o~sYn8Hb08Ix@vE_wa+MVqa+K*TFLfjl$}lDs~xWoB;f zE#hV&C1IZ?{qIn2mDY~LYj|wUJ`t*Ldo_|^Z7_3cZEF18wlCwzb7ztIfFm<%d2p~! zQ-F;0a>$g>%bP!Xc$mjus2G=E1@;=HjJ+qgGup17aoFiyFJ2KI$wDXX>5~^xr7bPt zYa%Y?r#ias2oCL6X)1ZFpEa9W(xv;9Zb>2$7Zs^Hdlm6emgU>^lL%kgO!w)0o$e0B z7tM=?t-N2~XRW=@Umki~(-d$QP*%Wx*@3Ti1tVmr6TZso<>j@S6!+mFSwA^7HQ}*o zs*$~Y#-J-kF_EhB{HzV3EUoA2^*_7k*9-E7Xy4i6T?e>HZ8Jjdkxy@ba!$H?DNnB& z=E_I=TY*}etaE-Y1Ii|iJr}-8pN-W#%9m)tQtKxVRgeFrC)L_!(oZU?b?G#%*rxt= zH)9nNMfa5&!h*3v=(1=#&M9b~dH{QHaPXpR8q2RqZ7gtlYFrC1@#zCxNMAA5#?7)&>8E`iM|DMUH23bS$uhOt0%a-KTRX+^%qfQ z)Rt%A_K%epZ6CrvCh}dX-u9h;mkix$wXeV5XCCd7Q(yC-XyykwWsrn$!Ug^r7nC5l;tZ}#P{YuMi-yjgm_tOtG>UtAi ztYD%4z8M&*z~%Keofajmz~K@Kk)n_g*nxEBy_a31ESPxn>K=Z)E@fr=&{ z(sbiM(J60ji-FKV4jSdxEQ>)K(ed#14|%(>_PfHO8!o8TEa>+4hn$|QhD%N4vAfC1 zSgT3DJ4D&EAwcwIm)SW&f?-pLlw-`v##;pEusTzV-g)HG$QI)1qh|-U_b{)vAF8d0 z?o8?R$CtUiR^pJ{JKk2J)EFbU>l+i!*S&F7hkRb!5%f#wSF(m=B+ z1^3HPh04^Fo+NyNyP^9ZFwUeJ5?GuqtXkB<$veCt^yW?e=Q`_3*NL1Qk1wrARciKO z@xZCUN;gq-i&M|e3x{X9!~iAi$uY%Y(^lOuaV&v*+~w`-+u~7XjB}YMf4Ytzx+VL_ z8NTpnOPS?4LP>@2@$>NfwspnvoXDj&n0;f|$-%p{Z+u(x9Hfm2xj*JFD0x?uwtrbj zXHW6>0p8Syl_$;mmaowqtc0wT;D{Hhnp}i$mI8lOwawl5`EZW5R#U z4wg5&R(UFh3RPYHaLtmnN7h0B5c14UAy4DFBuMr_04I|i%v$n_D?24*^|NZYp!r@? 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IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -module serving_arbiter - ( - input wire [31:0] i_wb_cpu_dbus_adr, - input wire [31:0] i_wb_cpu_dbus_dat, - input wire [3:0] i_wb_cpu_dbus_sel, - input wire i_wb_cpu_dbus_we, - input wire i_wb_cpu_dbus_stb, - output wire [31:0] o_wb_cpu_dbus_rdt, - output wire o_wb_cpu_dbus_ack, - - input wire [31:0] i_wb_cpu_ibus_adr, - input wire i_wb_cpu_ibus_stb, - output wire [31:0] o_wb_cpu_ibus_rdt, - output wire o_wb_cpu_ibus_ack, - - output wire [31:0] o_wb_mem_adr, - output wire [31:0] o_wb_mem_dat, - output wire [3:0] o_wb_mem_sel, - output wire o_wb_mem_we, - output wire o_wb_mem_stb, - input wire [31:0] i_wb_mem_rdt, - input wire i_wb_mem_ack); - - assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt; - assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb; - - assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt; - assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb; - - assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr; - assign o_wb_mem_dat = i_wb_cpu_dbus_dat; - assign o_wb_mem_sel = i_wb_cpu_dbus_sel; - assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb; - assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb; - - -endmodule diff --git a/serving/serving_mux.v b/serving/serving_mux.v deleted file mode 100644 index daa1be8e..00000000 --- a/serving/serving_mux.v +++ /dev/null @@ -1,66 +0,0 @@ -/* serving_mux.v : Simple Wishbone mux for the serving SoC - * - * ISC License - * - * Copyright (C) 2020 Olof Kindgren - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -module serving_mux - ( - input wire i_clk, - input wire i_rst, - - input wire [31:0] i_wb_cpu_adr, - input wire [31:0] i_wb_cpu_dat, - input wire [3:0] i_wb_cpu_sel, - input wire i_wb_cpu_we, - input wire i_wb_cpu_stb, - output wire [31:0] o_wb_cpu_rdt, - output wire o_wb_cpu_ack, - - output wire [31:0] o_wb_mem_adr, - output wire [31:0] o_wb_mem_dat, - output wire [3:0] o_wb_mem_sel, - output wire o_wb_mem_we, - output wire o_wb_mem_stb, - input wire [31:0] i_wb_mem_rdt, - input wire i_wb_mem_ack, - - output wire [31:0] o_wb_ext_adr, - output wire [31:0] o_wb_ext_dat, - output wire [3:0] o_wb_ext_sel, - output wire o_wb_ext_we, - output wire o_wb_ext_stb, - input wire [31:0] i_wb_ext_rdt, - input wire i_wb_ext_ack); - - wire ext = (i_wb_cpu_adr[31:30] != 2'b00); - - assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt; - assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack; - - assign o_wb_mem_adr = i_wb_cpu_adr; - assign o_wb_mem_dat = i_wb_cpu_dat; - assign o_wb_mem_sel = i_wb_cpu_sel; - assign o_wb_mem_we = i_wb_cpu_we; - assign o_wb_mem_stb = i_wb_cpu_stb & !ext; - - assign o_wb_ext_adr = i_wb_cpu_adr; - assign o_wb_ext_dat = i_wb_cpu_dat; - assign o_wb_ext_sel = i_wb_cpu_sel; - assign o_wb_ext_we = i_wb_cpu_we; - assign o_wb_ext_stb = i_wb_cpu_stb & ext; - -endmodule diff --git a/serving/serving_ram.v b/serving/serving_ram.v index 7acf64fa..a8017ced 100644 --- a/serving/serving_ram.v +++ b/serving/serving_ram.v @@ -1,4 +1,4 @@ -/* serving_ram.v : Shared RF I/D SRAM for the serving SoC +/* serving_ram.v : I/D SRAM for the serving SoC * * ISC License * @@ -23,50 +23,18 @@ module serving_ram parameter depth = 256, parameter aw = $clog2(depth), parameter memfile = "") - (input wire i_clk, - input wire [aw-1:0] i_waddr, - input wire [7:0] i_wdata, - input wire i_wen, - input wire [aw-1:0] i_raddr, - output wire [7:0] o_rdata, + (input wire i_clk, + input wire [aw-1:0] i_waddr, + input wire [7:0] i_wdata, + input wire i_wen, + input wire [aw-1:0] i_raddr, + output reg [7:0] o_rdata); - input wire [aw-1:2] i_wb_adr, - input wire [31:0] i_wb_dat, - input wire [3:0] i_wb_sel, - input wire i_wb_we, - input wire i_wb_stb, - output wire [31:0] o_wb_rdt, - output reg o_wb_ack); - - reg [1:0] bsel; - reg [7:0] rdata; - - wire wb_en = i_wb_stb & !i_wen & !o_wb_ack; - - wire wb_we = i_wb_we & i_wb_sel[bsel]; - - wire we = wb_en ? wb_we : i_wen; - - reg [7:0] mem [0:depth-1] /* verilator public */; - - wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr; - wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata; - wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr; - - reg [23:0] wb_rdt; - assign o_wb_rdt = {rdata, wb_rdt}; + reg [7:0] mem [0:depth-1] /* verilator public */; always @(posedge i_clk) begin - if (wb_en) bsel <= bsel + 2'd1; - o_wb_ack <= wb_en & &bsel; - if (bsel == 2'b01) wb_rdt[7:0] <= rdata; - if (bsel == 2'b10) wb_rdt[15:8] <= rdata; - if (bsel == 2'b11) wb_rdt[23:16] <= rdata; - end - - always @(posedge i_clk) begin - if (we) mem[waddr] <= wdata; - rdata <= mem[raddr]; + if (i_wen) mem[i_waddr] <= i_wdata; + o_rdata <= mem[i_raddr]; end initial @@ -74,6 +42,4 @@ module serving_ram $display("Preloading %m from %s", memfile); $readmemh(memfile, mem); end - - assign o_rdata = rdata; endmodule