use TOPOEXT on recent Zhaoxin CPUs

[bgoglin]

According to this recent Linux kernel patch "x86/cpu: detect extended topology for Zhaoxin CPUs"
(https://lore-kernel.gnuweeb.org/lkml/20250825112201.39487-1-TonyWWang-oc@zhaoxin.com/T/#u) we can use TOPOEXT in Zhaoxin CPU. It's currently explicitly blacklisted in our x86 backend.

When I enable it on ur existing CPUID dump, the topology is slightly different:

• on Shanghai KaiSheng ZXC+, topoext report a single L2 per core instead of shared by 8 cores
• on CentaurHauls ZXD 4600, topoext reports a single L2 per core instead of shared by 4 cores, and that L2 isn't inclusive anymore.
• on CentaurHauls KaiSheng KH 40000, topoext reports the same topology, but the L2 isn't inclusive anymore as well

Solutions:

1. The current topology (without topoext) could be wrong. Would be surprising since the cache topology (L2 sharing) was likely checked by Zhaoxin developers in the past. Also the web seems to confirm that the L2 is shared by 4 cores on ZXD 4600.
2. My dumps could be wrong (from early prototypes), so ignore the problem.
3. Topoext was buggily implemented in the past, so only enabled on recent generation. How do implement this?

@mormenthan Do you by chance have any info about this? I tried to contact Tony who sent the kernel patch, no reply unfortunately.

[bgoglin]

This was a misunderstanding on my side. Topoext is not supported, we already use Intel's 0xb/0x1f if available. Buggy cache information was due to testing other leaves (0x80000006) which do not support sharing and were designed before multicore CPUs.