Merge pull request #69 from pc2/22-latency-inference-2

Implement Latency Template Inference!

Author: VonTum

CHANGELOG.md

@@ -25,6 +25,8 @@
 - Add if/when distinction
 - Add `assert`, `clog2` and `sizeof`
 - Rename standard library: stl => std
+- Add doc-comments
+
 
 ### Technical Changes
 - Hindley-Milner for Concrete Typing

Cargo.toml

@@ -26,7 +26,6 @@ members = [
 ariadne = "0.4.1" # for nice errors
 num = "0.4"
 clap = { version = "4.5.21", features = ["derive", "wrap_help"] }
-arrayvec = "0.7.6"
 
 # Tree sitter
 tree-sitter = "~0.24.7"

README.md

@@ -161,7 +161,7 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Generative Code
 - [x] Generative Parameters
 - [x] Type Templates
-- [ ] Full Template Inference
+- [x] Full Template Inference
 - [ ] Actions, Triggers and Queries
 
 ### Language Features
@@ -180,7 +180,7 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Get rid of semicolons
 - [x] Access module inputs / outputs through field names
 - [ ] Array Slices
-- [ ] Bound Specifiers
+- [ ] Sized Integers
 - [ ] Structs
 - [ ] Conditional Bindings
 - [x] Generative variables and assignments
@@ -190,7 +190,7 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Generative Parameters
 - [ ] Generative Parameter Default Arguments
 - [x] Type Parameters
-- [ ] Generative Asserts
+- [x] Generative Asserts
 - [x] Multi-Interface Syntax
 - [x] Native Module integration syntax
 - [x] Intrinsic Modules
@@ -219,7 +219,7 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Hindley-Milner typing for Concrete Types
 - [x] Template Type Inference
 - [x] Generative Parameter Inference
-- [ ] Latency Count Inference
+- [x] Latency Count Inference
 - [ ] Let-syntax
 
 ### Latency Counting
@@ -233,7 +233,8 @@ In this example, we create a memory block with a read port and a write port. Thi
 - [x] Integrate into Verilog generation
 - [x] Latency cuts
 - [x] Latency Offset
-- [ ] Latency Cuts & Latency Counting for "disjoint Input-Output blocks"
+- [x] Latency Cuts & Latency Counting for "disjoint Input-Output blocks"
+- [x] Latency Count Inference
 - [ ] ~~Split Latencies~~
 
 ### LSP

src/alloc.rs

@@ -502,6 +502,21 @@ impl<T, IndexMarker> Default for FlatAlloc<T, IndexMarker> {
     }
 }
 
+/// TODO replace once get_many_mut stabilizes (In Rust 1.86 apparently)
+pub fn get2_mut<T>(slice: &mut [T], a: usize, b: usize) -> Option<(&mut T, &mut T)> {
+    match b.cmp(&a) {
+        Ordering::Equal => None,
+        Ordering::Less => {
+            let (l, r) = slice.split_at_mut(a);
+            Some((&mut r[0], &mut l[b]))
+        }
+        Ordering::Greater => {
+            let (l, r) = slice.split_at_mut(b);
+            Some((&mut l[a], &mut r[0]))
+        }
+    }
+}
+
 impl<T, IndexMarker> FlatAlloc<T, IndexMarker> {
     pub const EMPTY_FLAT_ALLOC: Self = Self::new();
 
@@ -528,6 +543,14 @@ impl<T, IndexMarker> FlatAlloc<T, IndexMarker> {
             _ph: PhantomData,
         }
     }
+    #[cfg(test)]
+    // Only for testing, so only enabled with test flag
+    pub fn from_vec(data: Vec<T>) -> Self {
+        Self {
+            data,
+            _ph: PhantomData,
+        }
+    }
     pub fn get_next_alloc_id(&self) -> UUID<IndexMarker> {
         let uuid = self.data.len();
         UUID(uuid, PhantomData)
@@ -571,6 +594,16 @@ impl<T, IndexMarker> FlatAlloc<T, IndexMarker> {
             _ph: PhantomData,
         }
     }
+    pub fn map2<T2, OT>(
+        &self,
+        second: &FlatAlloc<T2, IndexMarker>,
+        f: impl FnMut((UUID<IndexMarker>, &T, &T2)) -> OT,
+    ) -> FlatAlloc<OT, IndexMarker> {
+        FlatAlloc {
+            data: Vec::from_iter(zip_eq(self.iter(), second.iter()).map(f)),
+            _ph: PhantomData,
+        }
+    }
     pub fn find(
         &self,
         mut predicate: impl FnMut(UUID<IndexMarker>, &T) -> bool,
@@ -588,17 +621,7 @@ impl<T, IndexMarker> FlatAlloc<T, IndexMarker> {
         id_a: UUID<IndexMarker>,
         id_b: UUID<IndexMarker>,
     ) -> Option<(&mut T, &mut T)> {
-        match id_b.0.cmp(&id_a.0) {
-            Ordering::Equal => None,
-            Ordering::Less => {
-                let (l, r) = self.data.split_at_mut(id_a.0);
-                Some((&mut r[0], &mut l[id_b.0]))
-            }
-            Ordering::Greater => {
-                let (l, r) = self.data.split_at_mut(id_b.0);
-                Some((&mut l[id_a.0], &mut r[0]))
-            }
-        }
+        get2_mut(&mut self.data, id_a.0, id_b.0)
     }
     pub fn get(&self, id: UUID<IndexMarker>) -> Option<&T> {
         self.data.get(id.0)
@@ -639,7 +662,9 @@ impl<T, IndexMarker> IndexMut<UUID<IndexMarker>> for FlatAlloc<T, IndexMarker> {
 
 impl<T: Debug, IndexMarker> Debug for FlatAlloc<T, IndexMarker> {
     fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        self.data.fmt(f)
+        f.write_str("FlatAlloc::from_vec(vec!")?;
+        self.data.fmt(f)?;
+        f.write_str(")")
     }
 }
 
@@ -735,6 +760,41 @@ impl<'a, T, IndexMarker> IntoIterator for &'a mut FlatAlloc<T, IndexMarker> {
     }
 }
 
+#[derive(Debug)]
+pub struct FlatAllocConsumingIter<T, IndexMarker> {
+    iter: Enumerate<std::vec::IntoIter<T>>,
+    _ph: PhantomData<IndexMarker>,
+}
+
+impl<T, IndexMarker> Iterator for FlatAllocConsumingIter<T, IndexMarker> {
+    type Item = (UUID<IndexMarker>, T);
+
+    fn next(&mut self) -> Option<Self::Item> {
+        self.iter.next().map(|(id, v)| (UUID(id, PhantomData), v))
+    }
+    fn size_hint(&self) -> (usize, Option<usize>) {
+        self.iter.size_hint()
+    }
+}
+impl<T, IndexMarker> ExactSizeIterator for FlatAllocConsumingIter<T, IndexMarker> {
+    fn len(&self) -> usize {
+        self.iter.len()
+    }
+}
+
+impl<T, IndexMarker> IntoIterator for FlatAlloc<T, IndexMarker> {
+    type Item = (UUID<IndexMarker>, T);
+
+    type IntoIter = FlatAllocConsumingIter<T, IndexMarker>;
+
+    fn into_iter(self) -> Self::IntoIter {
+        FlatAllocConsumingIter {
+            iter: self.data.into_iter().enumerate(),
+            _ph: PhantomData,
+        }
+    }
+}
+
 #[derive(Debug)]
 pub struct ZippedIterator<
     IDMarker,
@@ -757,6 +817,7 @@ impl<
 {
     type Item = (UUID<IDMarker>, OA, OB);
 
+    #[track_caller]
     fn next(&mut self) -> Option<Self::Item> {
         match (self.iter_a.next(), self.iter_b.next()) {
             (None, None) => None,
@@ -806,6 +867,7 @@ impl<
 {
     type Item = (UUID<IDMarker>, OA, OB, OC);
 
+    #[track_caller]
     fn next(&mut self) -> Option<Self::Item> {
         match (self.iter_a.next(), self.iter_b.next(), self.iter_c.next()) {
             (None, None, None) => None,

src/codegen/system_verilog.rs

@@ -1,13 +1,13 @@
 use std::borrow::Cow;
 use std::ops::Deref;
 
+use crate::latency::CALCULATE_LATENCY_LATER;
 use crate::linker::{IsExtern, LinkInfo};
 use crate::prelude::*;
 
 use crate::flattening::{DeclarationKind, Instruction, Module, Port};
 use crate::instantiation::{
     InstantiatedModule, MultiplexerSource, RealWire, RealWireDataSource, RealWirePathElem,
-    CALCULATE_LATENCY_LATER,
 };
 use crate::typing::template::TVec;
 use crate::{typing::concrete_type::ConcreteType, value::Value};

src/config.rs

@@ -1,10 +1,10 @@
 use clap::{Arg, Command, ValueEnum};
+use std::sync::OnceLock;
 use std::{
     collections::HashSet,
     env,
     ffi::{OsStr, OsString},
     path::PathBuf,
-    sync::LazyLock,
 };
 
 /// Describes at what point in the compilation process we should exit early.
@@ -176,14 +176,18 @@ where
     })
 }
 
+static CONFIG: OnceLock<ConfigStruct> = OnceLock::new();
+
+pub fn initialize_config_from_cli_args() {
+    match parse_args(std::env::args_os()) {
+        Ok(parsed_args) => CONFIG.set(parsed_args).unwrap(),
+        Err(err) => err.exit(),
+    }
+}
+
 /// Access the singleton [ConfigStruct] representing the CLI arguments passed to `sus_compiler`
 pub fn config() -> &'static ConfigStruct {
-    static CONFIG: LazyLock<ConfigStruct> = LazyLock::new(|| {
-        parse_args(std::env::args_os())
-            .map_err(|err| err.exit())
-            .unwrap()
-    });
-    &CONFIG
+    CONFIG.get().unwrap()
 }
 
 #[cfg(test)]

src/dev_aid/lsp/hover_info.rs

@@ -1,13 +1,14 @@
 use std::borrow::Cow;
 
 use crate::alloc::ArenaAllocator;
+use crate::latency::CALCULATE_LATENCY_LATER;
 use crate::prelude::*;
 use crate::to_string::pretty_print_concrete_instance;
 
 use lsp_types::{LanguageString, MarkedString};
 
 use crate::flattening::{DeclarationKind, IdentifierType, InterfaceToDomainMap, Module};
-use crate::instantiation::{SubModuleOrWire, CALCULATE_LATENCY_LATER};
+use crate::instantiation::SubModuleOrWire;
 use crate::linker::{Documentation, FileData, GlobalUUID, LinkInfo};
 
 use crate::typing::{

src/flattening/initialization.rs

@@ -1,4 +1,3 @@
-use arrayvec::ArrayVec;
 use sus_proc_macro::{field, kind, kw};
 
 use crate::errors::ErrorStore;
@@ -360,7 +359,7 @@ fn initialize_global_object(
         errors: ErrorStore::new(),
         is_extern,
         resolved_globals: ResolvedGlobals::empty(),
-        checkpoints: ArrayVec::new(),
+        checkpoints: Vec::new(),
     };
 
     link_info.reabsorb_errors_globals(
@@ -374,6 +373,7 @@ fn initialize_global_object(
                 link_info,
                 ports: ctx.ports,
                 latency_inference_info: PortLatencyInferenceInfo::default(),
+                named_domains: ctx.domains.id_range(),
                 domains: ctx.domains,
                 implicit_clk_domain: ctx.implicit_clk_domain,
                 interfaces: ctx.interfaces,

src/flattening/mod.rs

@@ -6,7 +6,7 @@ mod parser;
 mod typechecking;
 mod walk;
 
-use crate::alloc::UUIDAllocator;
+use crate::alloc::{UUIDAllocator, UUIDRange};
 use crate::prelude::*;
 use crate::typing::abstract_type::DomainType;
 use crate::typing::type_inference::{DomainVariableIDMarker, TypeVariableIDMarker};
@@ -50,13 +50,18 @@ pub struct Module {
     /// Created in Stage 1: Initialization
     ///
     /// [Port::declaration_instruction] are set in Stage 2: Flattening
+    ///
+    /// Ports can only use domains in [Self::named_domains]
     pub ports: FlatAlloc<Port, PortIDMarker>,
 
     /// Created in Stage 2: Flattening
     pub latency_inference_info: PortLatencyInferenceInfo,
 
     /// Created in Stage 1: Initialization
+    ///
+    /// [Self::domains] is then extended during abstract typechecking to add unnamed domains
     pub domains: FlatAlloc<DomainInfo, DomainIDMarker>,
+    pub named_domains: UUIDRange<DomainIDMarker>,
     pub implicit_clk_domain: bool,
 
     /// Created in Stage 1: Initialization

src/instantiation/concrete_typecheck.rs

@@ -251,6 +251,8 @@ impl InstantiationContext<'_, '_> {
 
         self.typecheck_all_wires();
 
+        delayed_constraints.push(LatencyInferenceDelayedConstraint {});
+
         delayed_constraints.resolve_delayed_constraints(self);
 
         self.finalize();
@@ -355,18 +357,8 @@ fn concretize_written_type_with_possible_template_args(
     }
 }
 
-impl SubmoduleTypecheckConstraint {
-    /// Directly named type and value parameters are immediately unified, but latency count deltas can only be computed from the latency counting graph
-    fn try_infer_latency_counts(&mut self, _context: &mut InstantiationContext) {
-        // TODO
-    }
-}
-
 impl DelayedConstraint<InstantiationContext<'_, '_>> for SubmoduleTypecheckConstraint {
     fn try_apply(&mut self, context: &mut InstantiationContext) -> DelayedConstraintStatus {
-        // Try to infer template arguments based on the connections to the ports of the module.
-        self.try_infer_latency_counts(context);
-
         let sm = &mut context.submodules[self.sm_id];
 
         let submod_instr =
@@ -500,3 +492,12 @@ impl DelayedConstraint<InstantiationContext<'_, '_>> for SubmoduleTypecheckConst
             .error(submod_instr.get_most_relevant_span(), message);
     }
 }
+
+pub struct LatencyInferenceDelayedConstraint {}
+impl DelayedConstraint<InstantiationContext<'_, '_>> for LatencyInferenceDelayedConstraint {
+    fn try_apply(&mut self, context: &mut InstantiationContext<'_, '_>) -> DelayedConstraintStatus {
+        context.infer_parameters_for_latencies()
+    }
+
+    fn report_could_not_resolve_error(&self, _context: &InstantiationContext<'_, '_>) {} // Handled by incomplete submodules themselves
+}

src/instantiation/execute.rs

@@ -6,6 +6,7 @@
 
 use std::ops::{Deref, Index, IndexMut};
 
+use crate::latency::CALCULATE_LATENCY_LATER;
 use crate::linker::IsExtern;
 use crate::prelude::*;
 use crate::typing::template::GlobalReference;

src/instantiation/mod.rs

@@ -22,9 +22,6 @@ use crate::{
 
 use crate::typing::concrete_type::ConcreteType;
 
-// Temporary value before proper latency is given
-pub const CALCULATE_LATENCY_LATER: i64 = i64::MIN;
-
 /// See [MultiplexerSource]
 ///
 /// This is the post-instantiation equivalent of [crate::flattening::WireReferencePathElement]