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memory_out.vvp
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#! /usr/local/Cellar/icarus-verilog/12.0/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
S_0x7fa322919880 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
v0x7fa32292be30_0 .var "ALU_ResultM", 31 0;
v0x7fa32292bf20_0 .net "ALU_ResultW", 31 0, L_0x7fa32292ce60; 1 drivers
v0x7fa32292bfb0_0 .var "MemWriteM", 0 0;
v0x7fa32292c040_0 .var "PCPlus4M", 31 0;
v0x7fa32292c0d0_0 .net "PCPlus4W", 31 0, L_0x7fa32292cdb0; 1 drivers
v0x7fa32292c1a0_0 .var "RD_M", 4 0;
v0x7fa32292c250_0 .net "RD_W", 4 0, L_0x7fa32292cd00; 1 drivers
v0x7fa32292c300_0 .net "ReadDataW", 31 0, L_0x7fa32292cf40; 1 drivers
v0x7fa32292c3b0_0 .var "RegWriteM", 0 0;
v0x7fa32292c4e0_0 .net "RegWriteW", 0 0, L_0x7fa32292cbe0; 1 drivers
v0x7fa32292c570_0 .var "ResultSrcM", 1 0;
v0x7fa32292c600_0 .net "ResultSrcW", 1 0, L_0x7fa32292cc90; 1 drivers
v0x7fa32292c690_0 .var "WriteDataM", 31 0;
v0x7fa32292c760_0 .var "clk", 0 0;
v0x7fa32292c830_0 .var "rst", 0 0;
S_0x7fa322919520 .scope module, "dut" "memory_cycle" 2 11, 3 2 0, S_0x7fa322919880;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "RegWriteM";
.port_info 3 /INPUT 1 "MemWriteM";
.port_info 4 /INPUT 2 "ResultSrcM";
.port_info 5 /INPUT 5 "RD_M";
.port_info 6 /INPUT 32 "PCPlus4M";
.port_info 7 /INPUT 32 "WriteDataM";
.port_info 8 /INPUT 32 "ALU_ResultM";
.port_info 9 /OUTPUT 1 "RegWriteW";
.port_info 10 /OUTPUT 2 "ResultSrcW";
.port_info 11 /OUTPUT 5 "RD_W";
.port_info 12 /OUTPUT 32 "PCPlus4W";
.port_info 13 /OUTPUT 32 "ALU_ResultW";
.port_info 14 /OUTPUT 32 "ReadDataW";
L_0x7fa32292cbe0 .functor BUFZ 1, v0x7fa32292b700_0, C4<0>, C4<0>, C4<0>;
L_0x7fa32292cc90 .functor BUFZ 2, v0x7fa32292b9f0_0, C4<00>, C4<00>, C4<00>;
L_0x7fa32292cd00 .functor BUFZ 5, v0x7fa32292b2d0_0, C4<00000>, C4<00000>, C4<00000>;
L_0x7fa32292cdb0 .functor BUFZ 32, v0x7fa32292b0c0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0x7fa32292ce60 .functor BUFZ 32, v0x7fa32292ae00_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0x7fa32292cf40 .functor BUFZ 32, v0x7fa32292b550_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
v0x7fa32292ad70_0 .net "ALU_ResultM", 31 0, v0x7fa32292be30_0; 1 drivers
v0x7fa32292ae00_0 .var "ALU_ResultM_r", 31 0;
v0x7fa32292ae90_0 .net "ALU_ResultW", 31 0, L_0x7fa32292ce60; alias, 1 drivers
v0x7fa32292af30_0 .net "MemWriteM", 0 0, v0x7fa32292bfb0_0; 1 drivers
v0x7fa32292afe0_0 .net "PCPlus4M", 31 0, v0x7fa32292c040_0; 1 drivers
v0x7fa32292b0c0_0 .var "PCPlus4M_r", 31 0;
v0x7fa32292b170_0 .net "PCPlus4W", 31 0, L_0x7fa32292cdb0; alias, 1 drivers
v0x7fa32292b220_0 .net "RD_M", 4 0, v0x7fa32292c1a0_0; 1 drivers
v0x7fa32292b2d0_0 .var "RD_M_r", 4 0;
v0x7fa32292b3e0_0 .net "RD_W", 4 0, L_0x7fa32292cd00; alias, 1 drivers
v0x7fa32292b490_0 .net "ReadDataM", 31 0, L_0x7fa32292ca40; 1 drivers
v0x7fa32292b550_0 .var "ReadDataM_r", 31 0;
v0x7fa32292b5e0_0 .net "ReadDataW", 31 0, L_0x7fa32292cf40; alias, 1 drivers
v0x7fa32292b670_0 .net "RegWriteM", 0 0, v0x7fa32292c3b0_0; 1 drivers
v0x7fa32292b700_0 .var "RegWriteM_r", 0 0;
v0x7fa32292b7a0_0 .net "RegWriteW", 0 0, L_0x7fa32292cbe0; alias, 1 drivers
v0x7fa32292b840_0 .net "ResultSrcM", 1 0, v0x7fa32292c570_0; 1 drivers
v0x7fa32292b9f0_0 .var "ResultSrcM_r", 1 0;
v0x7fa32292baa0_0 .net "ResultSrcW", 1 0, L_0x7fa32292cc90; alias, 1 drivers
v0x7fa32292bb50_0 .net "WriteDataM", 31 0, v0x7fa32292c690_0; 1 drivers
v0x7fa32292bc10_0 .net "clk", 0 0, v0x7fa32292c760_0; 1 drivers
v0x7fa32292bca0_0 .net "rst", 0 0, v0x7fa32292c830_0; 1 drivers
S_0x7fa322918e60 .scope module, "dmem" "Data_Memory" 3 16, 4 3 0, S_0x7fa322919520;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "WE";
.port_info 3 /INPUT 32 "WD";
.port_info 4 /INPUT 32 "A";
.port_info 5 /OUTPUT 32 "RD";
L_0x7fa32292c900 .functor NOT 1, v0x7fa32292c830_0, C4<0>, C4<0>, C4<0>;
v0x7fa322917eb0_0 .net "A", 31 0, v0x7fa32292be30_0; alias, 1 drivers
v0x7fa32292a660_0 .net "RD", 31 0, L_0x7fa32292ca40; alias, 1 drivers
v0x7fa32292a700_0 .net "WD", 31 0, v0x7fa32292c690_0; alias, 1 drivers
v0x7fa32292a7b0_0 .net "WE", 0 0, v0x7fa32292bfb0_0; alias, 1 drivers
v0x7fa32292a850_0 .net *"_ivl_0", 0 0, L_0x7fa32292c900; 1 drivers
L_0x7fa322a63008 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x7fa32292a940_0 .net/2u *"_ivl_2", 31 0, L_0x7fa322a63008; 1 drivers
v0x7fa32292a9f0_0 .net *"_ivl_4", 31 0, L_0x7fa32292c9a0; 1 drivers
v0x7fa32292aaa0_0 .net "clk", 0 0, v0x7fa32292c760_0; alias, 1 drivers
v0x7fa32292ab40 .array "mem", 0 1023, 31 0;
v0x7fa32292ac50_0 .net "rst", 0 0, v0x7fa32292c830_0; alias, 1 drivers
E_0x7fa322918c70 .event posedge, v0x7fa32292aaa0_0;
L_0x7fa32292c9a0 .array/port v0x7fa32292ab40, v0x7fa32292be30_0;
L_0x7fa32292ca40 .functor MUXZ 32, L_0x7fa32292c9a0, L_0x7fa322a63008, L_0x7fa32292c900, C4<>;
.scope S_0x7fa322918e60;
T_0 ;
%wait E_0x7fa322918c70;
%load/vec4 v0x7fa32292a7b0_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%load/vec4 v0x7fa32292a700_0;
%ix/getv 3, v0x7fa322917eb0_0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x7fa32292ab40, 0, 4;
T_0.0 ;
%jmp T_0;
.thread T_0;
.scope S_0x7fa322918e60;
T_1 ;
%pushi/vec4 32, 0, 32;
%ix/load 4, 28, 0;
%flag_set/imm 4, 0;
%store/vec4a v0x7fa32292ab40, 4, 0;
%end;
.thread T_1;
.scope S_0x7fa322919520;
T_2 ;
%wait E_0x7fa322918c70;
%load/vec4 v0x7fa32292bca0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_2.0, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7fa32292b700_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x7fa32292b9f0_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v0x7fa32292b2d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x7fa32292b0c0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x7fa32292ae00_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x7fa32292b550_0, 0;
%jmp T_2.1;
T_2.0 ;
%load/vec4 v0x7fa32292b670_0;
%assign/vec4 v0x7fa32292b700_0, 0;
%load/vec4 v0x7fa32292b840_0;
%assign/vec4 v0x7fa32292b9f0_0, 0;
%load/vec4 v0x7fa32292b220_0;
%assign/vec4 v0x7fa32292b2d0_0, 0;
%load/vec4 v0x7fa32292afe0_0;
%assign/vec4 v0x7fa32292b0c0_0, 0;
%load/vec4 v0x7fa32292ad70_0;
%assign/vec4 v0x7fa32292ae00_0, 0;
%load/vec4 v0x7fa32292b490_0;
%assign/vec4 v0x7fa32292b550_0, 0;
T_2.1 ;
%jmp T_2;
.thread T_2;
.scope S_0x7fa322919880;
T_3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x7fa32292c760_0, 0, 1;
%end;
.thread T_3;
.scope S_0x7fa322919880;
T_4 ;
%load/vec4 v0x7fa32292c760_0;
%inv;
%store/vec4 v0x7fa32292c760_0, 0, 1;
%delay 50, 0;
%jmp T_4;
.thread T_4;
.scope S_0x7fa322919880;
T_5 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7fa32292c830_0, 0;
%delay 300, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7fa32292c830_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x7fa32292c3b0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x7fa32292bfb0_0, 0;
%pushi/vec4 1, 0, 2;
%assign/vec4 v0x7fa32292c570_0, 0;
%pushi/vec4 128, 0, 32;
%assign/vec4 v0x7fa32292be30_0, 0;
%pushi/vec4 53248, 0, 32;
%assign/vec4 v0x7fa32292c690_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v0x7fa32292c1a0_0, 0;
%pushi/vec4 14680064, 0, 32;
%assign/vec4 v0x7fa32292c040_0, 0;
%delay 500, 0;
%vpi_call 2 31 "$finish" {0 0 0};
%end;
.thread T_5;
.scope S_0x7fa322919880;
T_6 ;
%vpi_call 2 36 "$dumpfile", "memory_dump.vcd" {0 0 0};
%vpi_call 2 37 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x7fa322919880 {0 0 0};
%end;
.thread T_6;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"Memory_Cycle_tb.v";
"Memory_Cycle.v";
"./Data_Memory.v";