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thommythomasothommythomaso
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vcs-sim: Add scripts to run VCS sims, modify TBs to properly run in batch mode
1 parent 3781060 commit f1939d2

17 files changed

+391
-31
lines changed

‎Makefile

Lines changed: 27 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,37 +14,46 @@
1414
ifneq (,$(wildcard /etc/iis.version))
1515
VSIM ?= questa-2022.3 vsim
1616
SYNOPSYS_DC ?= synopsys-2022.03 dcnxt_shell
17+
VLOGAN ?= vcs-2020.12 vlogan
18+
VCS ?= vcs-2020.12 vcs
1719
else
1820
VSIM ?= vsim
1921
SYNOPSYS_DC ?= dc_shell
22+
VLOGAN ?= vlogan
23+
VCS ?= vcs
2024
endif
2125

2226
TBS ?= axi_addr_test \
2327
axi_atop_filter \
24-
axi_cdc axi_delayer \
28+
axi_bus_compare \
29+
axi_cdc \
30+
axi_delayer \
2531
axi_dw_downsizer \
2632
axi_dw_upsizer \
2733
axi_fifo \
2834
axi_isolate \
2935
axi_iw_converter \
36+
axi_lite_mailbox \
3037
axi_lite_regs \
3138
axi_lite_to_apb \
3239
axi_lite_to_axi \
33-
axi_lite_mailbox \
3440
axi_lite_xbar \
3541
axi_modify_address \
3642
axi_serializer \
3743
axi_sim_mem \
44+
axi_slave_compare \
3845
axi_to_axi_lite \
3946
axi_to_mem_banked \
4047
axi_xbar
4148

42-
SIM_TARGETS := $(addsuffix .log,$(addprefix sim-,$(TBS)))
49+
50+
SIM_TARGETS := $(addsuffix .log,$(addprefix sim-,$(TBS)))
51+
SIMVCS_TARGETS := $(addsuffix .log,$(addprefix sim_vcs-,$(TBS)))
4352

4453

4554
.SHELL: bash
4655

47-
.PHONY: help all sim_all clean
56+
.PHONY: help all sim_all sim_vcs_all clean
4857

4958

5059
help:
@@ -65,6 +74,9 @@ all: compile.log elab.log sim_all
6574
sim_all: $(SIM_TARGETS)
6675

6776

77+
sim_vcs_all: $(SIMVCS_TARGETS)
78+
79+
6880
build:
6981
mkdir -p $@
7082

@@ -85,6 +97,17 @@ sim-%.log: compile.log
8597
(! grep -n "Fatal:" $@)
8698

8799

100+
compile_vcs.log: Bender.yml | build
101+
export VLOGAN="$(VLOGAN)"; cd build && ../scripts/compile_vcs.sh | tee ../$@
102+
(! grep -n "Error-" $@)
103+
104+
105+
sim_vcs-%.log: compile_vcs.log
106+
export VCS="$(VCS)"; cd build && ../scripts/run_vcs.sh --random-seed $* | tee ../$@
107+
(! grep -n "Error" $@)
108+
(! grep -n "Fatal" $@)
109+
110+
88111
clean:
89112
rm -rf build
90113
rm -f *.log

‎scripts/compile_vcs.sh

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
#!/bin/bash
2+
# Copyright (c) 2022 ETH Zurich, University of Bologna
3+
#
4+
# Copyright and related rights are licensed under the Solderpad Hardware
5+
# License, Version 0.51 (the "License"); you may not use this file except in
6+
# compliance with the License. You may obtain a copy of the License at
7+
# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
8+
# or agreed to in writing, software, hardware and materials distributed under
9+
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
10+
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
11+
# specific language governing permissions and limitations under the License.
12+
#
13+
# Authors:
14+
# - Thomas Benz <[email protected]>
15+
16+
set -e
17+
18+
[ ! -z "$VLOGAN" ] || VLOGAN=vlogan
19+
20+
bender script vcs -t test -t rtl -t simulation \
21+
--vlog-arg="-full64" \
22+
--vlog-arg="-nc" \
23+
--vlog-arg="-q" \
24+
--vlog-arg="-assert svaext" \
25+
--vlog-arg="-timescale=1ns/1ps" \
26+
--vlogan-bin="$VLOGAN" \
27+
| grep -v "ROOT=" | sed '3 i ROOT="../"' \
28+
> compile_vcs.sh
29+
30+
source compile_vcs.sh

‎scripts/run_vcs.sh

Lines changed: 278 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,278 @@
1+
#!/bin/bash
2+
# Copyright (c) 2022 ETH Zurich, University of Bologna
3+
#
4+
# Copyright and related rights are licensed under the Solderpad Hardware
5+
# License, Version 0.51 (the "License"); you may not use this file except in
6+
# compliance with the License. You may obtain a copy of the License at
7+
# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
8+
# or agreed to in writing, software, hardware and materials distributed under
9+
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
10+
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
11+
# specific language governing permissions and limitations under the License.
12+
#
13+
# Authors:
14+
# - Thomas Benz <[email protected]>
15+
16+
set -euo pipefail
17+
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
18+
19+
# Seed values for `sv_seed`; can be extended with specific values on a per-TB basis, as well as with
20+
# a random number by passing the `--random` flag. The default value, 0, is always included to stay
21+
# regression-consistent.
22+
SEEDS=(0)
23+
24+
call_vcs() {
25+
$VCS -Mlib=work-"${@: -1}" -Mdir=work-"${@: -1}" -debug_access+r -CFLAGS "-Os" -full64 -xprop=xmerge "$@"
26+
for seed in ${SEEDS[@]}; do
27+
echo
28+
echo "----"
29+
echo "Running with seed: $seed"
30+
./"${@: -1}" +ntb_random_seed=$seed -exitstatus | tee "${@: -1}"_$seed.log 2>&1
31+
(! grep -n "Error" "${@: -1}"_$seed.log)
32+
(! grep -n "Fatal" "${@: -1}"_$seed.log)
33+
done
34+
# cleanup
35+
echo
36+
echo "----"
37+
echo "Cleanup"
38+
rm -rf work-"${@: -1}"
39+
rm -rf "${@: -1}".daidir
40+
rm -f "${@: -1}"
41+
echo "Done"
42+
echo "----"
43+
echo
44+
echo
45+
}
46+
47+
exec_test() {
48+
if [ ! -e "$ROOT/test/tb_$1.sv" ]; then
49+
echo "Testbench for '$1' not found!"
50+
exit 1
51+
fi
52+
case "$1" in
53+
axi_atop_filter)
54+
for MAX_TXNS in 1 3 12; do
55+
call_vcs tb_axi_atop_filter \
56+
-pvalue+TB_N_TXNS=1000 \
57+
-pvalue+TB_AXI_MAX_WRITE_TXNS=$MAX_TXNS \
58+
-o tb_axi_atop_filter_${MAX_TXNS}.vcs
59+
done
60+
;;
61+
axi_cdc)
62+
call_vcs tb_axi_cdc -o tb_axi_cdc.vcs
63+
;;
64+
axi_delayer)
65+
call_vcs tb_axi_delayer -o tb_axi_delayer.vcs
66+
;;
67+
axi_dw_downsizer)
68+
for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do
69+
for (( AxiMstPortDataWidth = 8; \
70+
AxiMstPortDataWidth < $AxiSlvPortDataWidth; \
71+
AxiMstPortDataWidth *= 2 )); \
72+
do
73+
call_vcs tb_axi_dw_downsizer \
74+
-pvalue+TbAxiSlvPortDataWidth=$AxiSlvPortDataWidth \
75+
-pvalue+TbAxiMstPortDataWidth=$AxiMstPortDataWidth \
76+
-o tb_axi_dw_downsizer_${AxiSlvPortDataWidth}_${AxiMstPortDataWidth}.vcs
77+
done
78+
done
79+
;;
80+
axi_dw_upsizer)
81+
for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do
82+
for (( AxiMstPortDataWidth = $AxiSlvPortDataWidth*2; \
83+
AxiMstPortDataWidth <= 1024; \
84+
AxiMstPortDataWidth *= 2 )); \
85+
do
86+
call_vcs tb_axi_dw_upsizer \
87+
-pvalue+TbAxiSlvPortDataWidth=$AxiSlvPortDataWidth \
88+
-pvalue+TbAxiMstPortDataWidth=$AxiMstPortDataWidth \
89+
-o tb_axi_dw_upsizer_${AxiSlvPortDataWidth}_${AxiMstPortDataWidth}.vcs
90+
done
91+
done
92+
;;
93+
axi_fifo)
94+
for DEPTH in 0 1 16; do
95+
for FALL_THROUGH in 0 1; do
96+
call_vcs tb_axi_fifo \
97+
-pvalue+Depth=$DEPTH \
98+
-pvalue+FallThrough=$FALL_THROUGH \
99+
-o tb_axi_fifo_${DEPTH}_${FALL_THROUGH}.vcs
100+
done
101+
done
102+
;;
103+
axi_iw_converter)
104+
for SLV_PORT_IW in 1 2 3 4 8; do
105+
MAX_SLV_PORT_IDS=$((2**SLV_PORT_IW))
106+
MAX_UNIQ_SLV_PORT_IDS_OPTS=(1 2)
107+
EXCL_OPTS=(0)
108+
if [ $SLV_PORT_IW -eq 3 ]; then
109+
# Save time by not testing exclusive accesses for every parametrization.
110+
EXCL_OPTS+=(1)
111+
fi
112+
for EXCL in "${EXCL_OPTS[@]}"; do
113+
if [ $MAX_SLV_PORT_IDS -gt 2 ]; then
114+
MAX_UNIQ_SLV_PORT_IDS_OPTS+=(3 4)
115+
fi
116+
if [ $(($MAX_SLV_PORT_IDS/2)) -ge 4 ]; then
117+
MAX_UNIQ_SLV_PORT_IDS_OPTS+=($((MAX_SLV_PORT_IDS/2-1)))
118+
fi
119+
MAX_UNIQ_SLV_PORT_IDS_OPTS+=($MAX_SLV_PORT_IDS)
120+
for MST_PORT_IW in 1 2 3 4; do
121+
if [ $MST_PORT_IW -lt $SLV_PORT_IW ]; then # downsize
122+
for MAX_UNIQ_SLV_PORT_IDS in "${MAX_UNIQ_SLV_PORT_IDS_OPTS[@]}"; do
123+
MAX_MST_PORT_IDS=$((2**MST_PORT_IW))
124+
if [ $MAX_UNIQ_SLV_PORT_IDS -le $MAX_MST_PORT_IDS ]; then
125+
call_vcs tb_axi_iw_converter \
126+
-pvalue+TbEnExcl=$EXCL \
127+
-pvalue+TbAxiSlvPortIdWidth=$SLV_PORT_IW \
128+
-pvalue+TbAxiMstPortIdWidth=$MST_PORT_IW \
129+
-pvalue+TbAxiSlvPortMaxUniqIds=$MAX_UNIQ_SLV_PORT_IDS \
130+
-pvalue+TbAxiSlvPortMaxTxnsPerId=5 \
131+
-o tb_axi_iw_converter_${EXCL}_${SLV_PORT_IW}_${MST_PORT_IW}_${MAX_UNIQ_SLV_PORT_IDS}.vcs
132+
else
133+
call_vcs tb_axi_iw_converter \
134+
-pvalue+TbEnExcl=$EXCL \
135+
-pvalue+TbAxiSlvPortIdWidth=$SLV_PORT_IW \
136+
-pvalue+TbAxiMstPortIdWidth=$MST_PORT_IW \
137+
-pvalue+TbAxiSlvPortMaxUniqIds=$MAX_UNIQ_SLV_PORT_IDS \
138+
-pvalue+TbAxiSlvPortMaxTxns=31 \
139+
-pvalue+TbAxiMstPortMaxUniqIds=$((2**MST_PORT_IW)) \
140+
-pvalue+TbAxiMstPortMaxTxnsPerId=7 \
141+
-o tb_axi_iw_converter_${EXCL}_${SLV_PORT_IW}_${MST_PORT_IW}_${MAX_UNIQ_SLV_PORT_IDS}_$((2**MST_PORT_IW)).vcs
142+
fi
143+
done
144+
else
145+
call_vcs tb_axi_iw_converter \
146+
-pvalue+TbEnExcl=$EXCL \
147+
-pvalue+TbAxiSlvPortIdWidth=$SLV_PORT_IW \
148+
-pvalue+TbAxiMstPortIdWidth=$MST_PORT_IW \
149+
-pvalue+TbAxiSlvPortMaxTxnsPerId=3 \
150+
-o tb_axi_iw_converter_${EXCL}_${SLV_PORT_IW}_${MST_PORT_IW}.vcs
151+
fi
152+
done
153+
done
154+
done
155+
;;
156+
axi_lite_regs)
157+
for PRIV in 0 1; do
158+
for SECU in 0 1; do
159+
for BYTES in 42 369; do
160+
call_vcs tb_axi_lite_regs \
161+
-pvalue+TbPrivProtOnly=$PRIV \
162+
-pvalue+TbSecuProtOnly=$SECU \
163+
-pvalue+TbRegNumBytes=$BYTES \
164+
-o tb_axi_lite_regs_${PRIV}_${SECU}_${BYTES}.vcs
165+
done
166+
done
167+
done
168+
;;
169+
axi_lite_to_apb)
170+
for PIPE_REQ in 0 1; do
171+
for PIPE_RESP in 0 1; do
172+
call_vcs tb_axi_lite_to_apb \
173+
-pvalue+TbPipelineRequest=$PIPE_REQ \
174+
-pvalue+TbPipelineResponse=$PIPE_RESP \
175+
-o tb_axi_lite_to_apb_${PIPE_REQ}_${PIPE_RESP}.vcs
176+
done
177+
done
178+
;;
179+
axi_lite_to_axi)
180+
for DW in 8 16 32 64 128 256 512 1024; do
181+
call_vcs tb_axi_lite_to_axi \
182+
-pvalue+TB_DW=$DW \
183+
-o tb_axi_lite_to_axi_${DW}.vcs
184+
done
185+
;;
186+
axi_sim_mem)
187+
for AW in 16 32 64; do
188+
for DW in 32 64 128 256 512 1024; do
189+
call_vcs tb_axi_sim_mem \
190+
-pvalue+TbAddrWidth=$AW \
191+
-pvalue+TbDataWidth=$DW \
192+
-o tb_axi_sim_mem_${AW}_${DW}.vcs
193+
done
194+
done
195+
;;
196+
axi_xbar)
197+
for NumMst in 1 6; do
198+
for NumSlv in 1 8; do
199+
for Atop in 0 1; do
200+
for Exclusive in 0 1; do
201+
for UniqueIds in 0 1; do
202+
for DataWidth in 64 256; do
203+
for Pipe in 0 1; do
204+
call_vcs tb_axi_xbar \
205+
-pvalue+TbNumMasters=$NumMst \
206+
-pvalue+TbNumSlaves=$NumSlv \
207+
-pvalue+TbEnAtop=$Atop \
208+
-pvalue+TbEnExcl=$Exclusive \
209+
-pvalue+TbUniqueIds=$UniqueIds \
210+
-pvalue+TbAxiDataWidth=$DataWidth \
211+
-pvalue+TbPipeline=$Pipe \
212+
-o tb_axi_xbar_${NumMst}_${NumSlv}_${Atop}_${Exclusive}_${UniqueIds}_${DataWidth}_${Pipe}.vcs
213+
done
214+
done
215+
done
216+
done
217+
done
218+
done
219+
done
220+
;;
221+
axi_to_mem_banked)
222+
for MEM_LAT in 1 2; do
223+
for BANK_FACTOR in 1 2; do
224+
for NUM_BANKS in 1 2 ; do
225+
for AXI_DATA_WIDTH in 64 256 ; do
226+
ACT_BANKS=$((2*$BANK_FACTOR*$NUM_BANKS))
227+
MEM_DATA_WIDTH=$(($AXI_DATA_WIDTH/$NUM_BANKS))
228+
call_vcs tb_axi_to_mem_banked \
229+
-pvalue+TbAxiDataWidth=$AXI_DATA_WIDTH \
230+
-pvalue+TbNumWords=2048 \
231+
-pvalue+TbNumBanks=$ACT_BANKS \
232+
-pvalue+TbMemDataWidth=$MEM_DATA_WIDTH \
233+
-pvalue+TbMemLatency=$MEM_LAT \
234+
-pvalue+TbNumWrites=2000 \
235+
-pvalue+TbNumReads=2000 \
236+
-o tb_axi_to_mem_banked_${AXI_DATA_WIDTH}_${ACT_BANKS}_${MEM_DATA_WIDTH}_${MEM_LAT}.vcs
237+
done
238+
done
239+
done
240+
done
241+
;;
242+
*)
243+
call_vcs tb_$1 -o tb_${1}.vcs
244+
;;
245+
esac
246+
}
247+
248+
# Parse flags.
249+
PARAMS=""
250+
while (( "$#" )); do
251+
case "$1" in
252+
--random-seed)
253+
SEEDS+=($RANDOM)
254+
shift;;
255+
-*--*) # unsupported flag
256+
echo "Error: Unsupported flag '$1'." >&2
257+
exit 1;;
258+
*) # preserve positional arguments
259+
PARAMS="$PARAMS $1"
260+
shift;;
261+
esac
262+
done
263+
eval set -- "$PARAMS"
264+
265+
if [ "$#" -eq 0 ]; then
266+
tests=()
267+
while IFS= read -r -d $'\0'; do
268+
tb_name="$(basename -s .sv $REPLY)"
269+
dut_name="${tb_name#tb_}"
270+
tests+=("$dut_name")
271+
done < <(find "$ROOT/test" -name 'tb_*.sv' -a \( ! -name '*_pkg.sv' \) -print0)
272+
else
273+
tests=("$@")
274+
fi
275+
276+
for t in "${tests[@]}"; do
277+
exec_test $t
278+
done

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