Add src files

Author: recurze

Integrated.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+
+entity DP_C is
+    port(
+        clk: in std_logic;
+        rst: in std_logic
+    );
+end entity;
+
+architecture DP_C_arc of DP_C is
+
+    -- for datapath
+    signal result: std_logic_vector(31 downto 0);
+    signal instruction: std_logic_vector(31 downto 0);
+
+    -- out from datapath into controller
+    signal NZCV: std_logic_vector(3 downto 0):= "0000";
+
+    -- Control signals
+    -- Actrl
+    signal op: std_logic_vector(3 downto 0);
+
+    -- Bctrl
+    signal p:std_logic;
+
+    -- Main Controller
+    signal PW: std_logic;
+    signal IW: std_logic;
+    signal DW: std_logic;
+    signal AW: std_logic;
+    signal BW: std_logic;
+    signal resW: std_logic;
+    signal Fset: std_logic;
+    signal RW: std_logic;
+    signal MR: std_logic;
+    signal MW: std_logic;
+    signal IorD: std_logic;
+    signal Asrc1: std_logic;
+    signal Asrc2: std_logic_vector(1 downto 0);
+    signal Rsrc: std_logic;
+    signal M2R: std_logic;
+
+    signal I: std_logic;
+    signal M: std_logic;
+begin
+
+    DP:
+    entity WORK.datapath port map(
+        clk=>clk,
+        rst=>rst,
+
+        op=>op,
+        p=>p,
+
+        PW=>PW,
+        IW=>IW,
+        DW=>DW,
+        AW=>AW,
+        BW=>BW,
+        resW=>resW,
+        Fset=>Fset,
+        RW=>RW,
+        MR=>MR,
+        MW=>MW,
+        IorD=>IorD,
+        Asrc1=>Asrc1,
+        Asrc2=>Asrc2,
+        Rsrc=>Rsrc,
+        M2R=>M2R,
+
+        I=>I,
+        M=>M,
+
+        out_flags=>NZCV,
+        instruction=>instruction,
+        result=>result
+    );
+
+    Controller:
+    entity WORK.Controller port map(
+        clk=>clk,
+        rst=>rst,
+        NZCV=>NZCV,
+        ins=>instruction,
+
+        op=>op,
+
+        p=>p,
+
+        PW=>PW,
+        IW=>IW,
+        DW=>DW,
+        AW=>AW,
+        BW=>BW,
+        resW=>resW,
+        Fset=>Fset,
+        RW=>RW,
+        MR=>MR,
+        MW=>MW,
+        IorD=>IorD,
+        Asrc1=>Asrc1,
+        Asrc2=>Asrc2,
+        Rsrc=>Rsrc,
+        M2R=>M2R,
+
+        I=>I,
+        M=>M
+    );
+end architecture;

controller/src/Actrl.vhd

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+library IEEE;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use WORK.mytypes.all;
+entity Actrl is
+    port (
+        -- 27-26, 24-20, 7-4
+        state: in state;
+        ins: in std_logic_vector(10 downto 0);
+        op: out std_logic_vector(3 downto 0)
+    );
+end Actrl;
+
+architecture Actrl_arc of Actrl is
+    signal F: std_logic_vector(1 downto 0);
+    signal opcode: std_logic_vector(3 downto 0);
+    signal L, U : std_logic;
+    signal M: std_logic_vector(3 downto 0); --Checking for Mul.
+begin
+    F<=ins(10 downto 9);
+    opcode<=ins(8 downto 5);
+    U<=ins(7);
+    -- not really needed.
+    -- too lazy to change everywhere.
+    L<=ins(4);
+    M<=ins(3 downto 0);
+
+    process(F, opcode, L, M, U, state) begin
+        if state=fetch  then
+            op<="0100";
+        elsif F="00" then --DP
+            if M="1001" then
+                op<="1101";
+            else
+                op<=opcode;
+            end if;
+        elsif F="01" then --DT
+            if U='1' then
+                op<="0100";
+            else
+                op<="0010";
+            end if;
+        else
+            op<="0100";
+        end if;
+    end process;
+end architecture;

controller/src/Bctrl.vhd

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+library IEEE;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity Bctrl is
+    port (
+        cond: in std_logic_vector(3 downto 0);
+        NZCV: in std_logic_vector(3 downto 0);
+        p: out std_logic
+    );
+end Bctrl;
+
+architecture Bctrl_arc of Bctrl is
+    signal N,C,Z,V, temp: std_logic;
+begin
+    N<=NZCV(3);
+    Z<=NZCV(2);
+    C<=NZCV(1);
+    V<=NZCV(0);
+
+    p<=temp;
+    process(cond, N, C, Z, V, temp) begin
+        case cond is
+            when "0000" => temp<=Z;
+            when "0001" => temp<=not Z;
+            when "0010" => temp<=C;
+            when "0011" => temp<=not C;
+            when "0100" => temp<=N;
+            when "0101" => temp<=not N;
+            when "0110" => temp<=V;
+            when "0111" => temp<=not V;
+            when "1000" => temp<=C and (not Z);
+            when "1001" => temp<=Z and (not C);
+            when "1010" => temp<=not (N xor V);
+            when "1011" => temp<=N xor V;
+            when "1100" => temp<=(not Z) and (not (N xor V));
+            when "1101" => temp<=Z or (N xor V);
+            when "1110" => temp<='1';
+            when others => temp<='1';
+        end case;
+    end process;
+end architecture;

controller/src/Controller.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use WORK.mytypes.all;
+
+entity Controller is
+    port (
+        clk :in std_logic;
+        rst: in std_logic;
+        NZCV: in std_logic_vector(3 downto 0);
+        ins :in std_logic_vector(31 downto 0);
+
+        -- output of Actrl.
+        op:out std_logic_vector(3 downto 0);
+
+        -- output of Bctrl.
+        p: out std_logic;
+
+        -- output of Main Controller
+        PW:out std_logic;
+        IW:out std_logic;
+        DW:out std_logic;
+        AW:out std_logic;
+        BW:out std_logic;
+        resW:out std_logic;
+        Fset:out std_logic;
+        RW:out std_logic;
+        MR:out std_logic;
+        MW:out std_logic;
+        IorD:out std_logic;
+        Asrc1:out std_logic;
+        Asrc2:out std_logic_vector(1 downto 0);
+        Rsrc:out std_logic;
+        M2R:out std_logic;
+        I:out std_logic;
+        M:out std_logic
+
+        -- not_implemented:out std_logic;
+        -- undefined:out std_logic;
+    );
+end entity Controller;
+
+architecture Controller_arc of Controller is
+    signal actrl_ins: std_logic_vector(10 downto 0);
+    signal MC_ins: std_logic_vector(4 downto 0);
+    signal ns_ins: std_logic_vector(2 downto 0);
+    signal flag: std_logic;
+    signal cs, ns: state;
+begin
+    p<=flag;
+    actrl_ins<=ins(27 downto 26)&ins(24 downto 20)&ins(7 downto 4);
+
+    Actrl:
+    entity WORK.Actrl port map(
+        state=> cs,
+        ins=> actrl_ins,
+        op=>op
+    );
+
+    Bctrl:
+    entity WORK.Bctrl port map(
+        cond=>ins(31 downto 28),
+        NZCV=>NZCV,
+        p=>flag
+    );
+
+    MC_ins<=ins(25)&ins(7 downto 4);
+    MC:
+    entity WORK.Main_Controller port map(
+        p=>flag,
+        ins=>MC_ins,
+        current_state=>cs,
+
+        PW=>PW,
+        IW=>IW,
+        DW=>DW,
+        AW=>AW,
+        BW=>BW,
+        resW=>resW,
+        RW=>RW,
+        MR=>MR,
+        MW=>MW,
+        IorD=>IorD,
+        Fset=>Fset,
+        Asrc1=>Asrc1,
+        Asrc2=>Asrc2,
+        Rsrc=>Rsrc,
+        M2R=>M2R,
+
+        I=>I,
+        M=>M
+    );
+
+    ns_ins<=ins(27 downto 26)&ins(20);
+    Next_State:
+    entity WORK.next_state port map(
+        ins=>ns_ins,
+        current_state=>cs,
+        next_state=>ns
+    );
+
+    Control_state:
+    entity WORK.control_state port map(
+        clk=>clk,
+        rst=>rst,
+        next_state=>ns,
+        current_state=>cs
+    );
+
+    -- ID:
+    -- entity WORK.Instruction_decoder port map (
+        -- clk=>clk,
+        -- ins=>dec_ins,
+        -- not_implemented=>not_implemented,
+        -- undefined=>undefined
+    -- );
+end architecture;

controller/src/Instruction_decoder.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity Instruction_decoder is
+    port (
+        clk :in  std_logic;
+        --27-20, 11-4
+        ins:in std_logic_vector(15 downto 0);
+        not_implemented:out std_logic;
+        undefined:out std_logic
+    );
+end Instruction_decoder;
+
+architecture arc_Imstruction_decoder of Instruction_decoder is
+    signal n1,n2,n3,n4,n5,n6,n7,n8:std_logic;
+begin
+    undefined<=(NOT (ins(15)) AND ins(14) )AND ins(13) AND ins(4);
+    not_implemented<=n1 or n2 or n3 or n4 or n5 or n6 or n7 or n8;
+    n1<=ins(14) AND ins(15);
+    n2<=ins(15) AND NOT (ins(14)) AND (NOT(ins(13)));
+    n3<=NOT(ins(15)) AND NOT(ins(14)) AND ins(13);
+    n4<=NOT(ins(15)) AND NOT(ins(14)) AND (NOT ins(13)) AND NOT(ins(0));
+    n5<=NOT(ins(15)) AND NOT(ins(14)) AND (NOT ins(13)) AND ins(0) AND NOT(ins(7)) AND ins(6) AND ins(5) AND ins(4) AND ins(3);
+    n6<=NOT(NOT(ins(15)) AND NOT(ins(14)) AND (NOT ins(13)) AND ins(0) AND ins(7) AND NOT (ins(2)) AND NOT(ins(1)));
+    n7<=NOT(ins(15)) AND NOT(ins(14)) AND (NOT ins(13)) AND ins(0) AND ins(7) AND NOT (ins(2)) AND NOT(ins(1)) AND NOT(ins(12)) AND ins(11);
+    n8<=NOT(ins(15)) AND NOT(ins(14)) AND (NOT ins(13)) AND ins(0) AND ins(7) AND NOT (ins(2)) AND NOT(ins(1)) AND ins(12);
+end architecture arc_Imstruction_decoder;