Update examples to use new macros.

Author: thejpster

examples/mps3-an536/reference/abt-exception-armv8r-none-eabihf.out

@@ -0,0 +1,9 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+DFAR (Faulting Address Register): Dfar(4097)
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+DFAR (Faulting Address Register): Dfar(4097)

examples/mps3-an536/reference/hello-armv8r-none-eabihf.out

@@ -3,7 +3,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/hello.rs",
-        line: 26,
+        line: 22,
         col: 5,
     },
     can_unwind: true,

examples/mps3-an536/reference/svc-armv8r-none-eabihf.out

@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc.rs",
-        line: 29,
+        line: 25,
         col: 5,
     },
     can_unwind: true,

examples/mps3-an536/src/bin/abt-exception-a32.rs

@@ -6,7 +6,11 @@
 use core::sync::atomic::{AtomicU32, Ordering};
 
 use cortex_ar::register::{Dfar, Dfsr, Sctlr};
+
 // pull in our start-up code
+use cortex_r_rt::{entry, exception};
+
+// pull in our library
 use mps3_an536 as _;
 
 use semihosting::println;
@@ -17,14 +21,7 @@ static COUNTER: AtomicU32 = AtomicU32::new(0);
 /// The entry-point to the Rust application.
 ///
 /// It is called by the start-up.
-#[no_mangle]
-pub extern "C" fn kmain() -> ! {
-    main();
-}
-
-/// The main function of our Rust application.
-#[export_name = "main"]
-#[allow(unreachable_code)]
+#[entry]
 fn main() -> ! {
     // Enable alignment check for Armv7-R. Was not required
     // on Cortex-A for some reason, even though the bit was not set.
@@ -73,18 +70,18 @@ fn disable_alignment_check() {
     Sctlr::write(sctrl);
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _undefined_handler(_addr: u32) -> ! {
+#[exception(UndefinedHandler)]
+fn undefined_handler(_addr: usize) -> ! {
     panic!("unexpected undefined exception");
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _prefetch_handler(_addr: u32) -> ! {
+#[exception(PrefetchHandler)]
+fn prefetch_handler(_addr: usize) -> ! {
     panic!("unexpected prefetch exception");
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _abort_handler(addr: usize) -> usize {
+#[exception(AbortHandler)]
+fn abort_handler(addr: usize) -> usize {
     println!("data abort occurred");
     // If this is not disabled, reading DFAR will trigger an alignment fault on Armv8-R, leading
     // to a loop.

examples/mps3-an536/src/bin/abt-exception-t32.rs

@@ -6,7 +6,11 @@
 use core::sync::atomic::{AtomicU32, Ordering};
 
 use cortex_ar::register::{Dfar, Dfsr, Sctlr};
+
 // pull in our start-up code
+use cortex_r_rt::{entry, exception};
+
+// pull in our library
 use mps3_an536 as _;
 
 use semihosting::println;
@@ -17,14 +21,7 @@ static COUNTER: AtomicU32 = AtomicU32::new(0);
 /// The entry-point to the Rust application.
 ///
 /// It is called by the start-up.
-#[no_mangle]
-pub extern "C" fn kmain() -> ! {
-    main();
-}
-
-/// The main function of our Rust application.
-#[export_name = "main"]
-#[allow(unreachable_code)]
+#[entry]
 fn main() -> ! {
     // Enable alignment check for Armv7-R. Was not required
     // on Cortex-A for some reason, even though the bit was not set.
@@ -73,18 +70,18 @@ fn disable_alignment_check() {
     Sctlr::write(sctrl);
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _undefined_handler(_addr: u32) -> ! {
+#[exception(UndefinedHandler)]
+fn undefined_handler(_addr: usize) -> ! {
     panic!("unexpected undefined exception");
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _prefetch_handler(_addr: u32) -> ! {
+#[exception(PrefetchHandler)]
+fn prefetch_handler(_addr: usize) -> ! {
     panic!("unexpected prefetch exception");
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _abort_handler(addr: usize) -> usize {
+#[exception(AbortHandler)]
+fn abort_handler(addr: usize) -> usize {
     println!("data abort occurred");
     // If this is not disabled, reading DFAR will trigger an alignment fault on Armv8-R, leading
     // to a loop.

examples/mps3-an536/src/bin/generic_timer.rs

@@ -4,21 +4,18 @@
 #![no_main]
 
 // pull in our start-up code
+use cortex_r_rt::entry;
+
+// pull in our library
 use mps3_an536 as _;
 
 use semihosting::println;
 
 /// The entry-point to the Rust application.
 ///
-/// It is called by the start-up code in `cortex-m-rt`.
-#[no_mangle]
-pub extern "C" fn kmain() {
-    main();
-    semihosting::process::exit(0);
-}
-
-/// Let's test some timers!
-fn main() {
+/// It is called by the start-up code in `cortex-r-rt`.
+#[entry]
+fn main() -> ! {
     use cortex_ar::generic_timer::{El1PhysicalTimer, El1VirtualTimer, GenericTimer};
     let cntfrq = cortex_ar::register::Cntfrq::read().0;
     println!("cntfrq = {:.03} MHz", cntfrq as f32 / 1_000_000.0);
@@ -59,4 +56,6 @@ fn main() {
         }
         println!("{} countdown hit zero!", name,);
     }
+
+    semihosting::process::exit(0);
 }

examples/mps3-an536/src/bin/gic.rs

@@ -4,6 +4,9 @@
 #![no_main]
 
 // pull in our start-up code
+use cortex_r_rt::{entry, exception};
+
+// pull in our library
 use mps3_an536 as _;
 
 use arm_gic::{
@@ -22,15 +25,8 @@ const GICR_BASE_OFFSET: usize = 0x0010_0000usize;
 
 /// The entry-point to the Rust application.
 ///
-/// It is called by the start-up code in `cortex-m-rt`.
-#[no_mangle]
-pub extern "C" fn kmain() {
-    main();
-}
-
-/// The main function of our Rust application.
-///
-/// Called by [`kmain`].
+/// It is called by the start-up code in `cortex-r-rt`.
+#[entry]
 fn main() -> ! {
     // Get the GIC address by reading CBAR
     let periphbase = cortex_ar::register::ImpCbar::read().periphbase();
@@ -89,8 +85,8 @@ fn dump_cpsr() {
     println!("CPSR: {:?}", cpsr);
 }
 
-#[no_mangle]
-unsafe extern "C" fn _irq_handler() {
+#[exception(IrqHandler)]
+fn irq_handler() {
     println!("> IRQ");
     while let Some(int_id) = SingleCoreGic::get_and_acknowledge_interrupt() {
         println!("- IRQ handle {:?}", int_id);

examples/mps3-an536/src/bin/hello.rs

@@ -4,21 +4,17 @@
 #![no_main]
 
 // pull in our start-up code
+use cortex_r_rt::entry;
+
+// pull in our library
 use mps3_an536 as _;
 
 use semihosting::println;
 
 /// The entry-point to the Rust application.
 ///
-/// It is called by the start-up code in `cortex-m-rt`.
-#[no_mangle]
-pub extern "C" fn kmain() {
-    main();
-}
-
-/// The main function of our Rust application.
-///
-/// Called by [`kmain`].
+/// It is called by the start-up code in `cortex-r-rt`.
+#[entry]
 fn main() -> ! {
     let x = 1.0f64;
     let y = x * 2.0;

examples/mps3-an536/src/bin/prefetch-exception-a32.rs

@@ -8,15 +8,18 @@ use cortex_ar::register::{Ifar, Ifsr};
 use semihosting::println;
 
 // pull in our start-up code
+use cortex_r_rt::{entry, exception};
+
+// pull in our library
 use mps3_an536 as _;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
 /// The entry-point to the Rust application.
 ///
 /// It is called by the start-up.
-#[no_mangle]
-pub extern "C" fn kmain() -> ! {
+#[entry]
+fn main() -> ! {
     println!("Hello, this is a prefetch exception example");
 
     // A BKPT instruction triggers a Prefetch Abort except when Halting debug-mode is enabled.
@@ -49,13 +52,13 @@ core::arch::global_asm!(
 "#
 );
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _undefined_handler(_addr: usize) -> ! {
+#[exception(UndefinedHandler)]
+fn undefined_handler(_addr: usize) -> ! {
     panic!("unexpected undefined exception");
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _prefetch_handler(addr: usize) -> usize {
+#[exception(PrefetchHandler)]
+fn prefetch_handler(addr: usize) -> usize {
     println!("prefetch abort occurred");
     let ifsr = Ifsr::read();
     println!("IFSR (Fault Status Register): {:?}", ifsr);
@@ -92,7 +95,7 @@ unsafe extern "C" fn _prefetch_handler(addr: usize) -> usize {
     }
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _abort_handler(_addr: usize) -> ! {
+#[exception(AbortHandler)]
+fn abort_handler(_addr: usize) -> ! {
     panic!("unexpected abort exception");
 }

examples/mps3-an536/src/bin/prefetch-exception-t32.rs

@@ -8,15 +8,18 @@ use cortex_ar::register::{Ifar, Ifsr};
 use semihosting::println;
 
 // pull in our start-up code
+use cortex_r_rt::{entry, exception};
+
+// pull in our library
 use mps3_an536 as _;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
 /// The entry-point to the Rust application.
 ///
 /// It is called by the start-up.
-#[no_mangle]
-pub extern "C" fn kmain() -> ! {
+#[entry]
+fn main() -> ! {
     println!("Hello, this is a prefetch exception example");
 
     // A BKPT instruction triggers a Prefetch Abort except when Halting debug-mode is enabled.
@@ -49,13 +52,13 @@ core::arch::global_asm!(
 "#
 );
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _undefined_handler(_addr: usize) -> ! {
+#[exception(UndefinedHandler)]
+fn undefined_handler(_addr: usize) -> ! {
     panic!("unexpected undefined exception");
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _prefetch_handler(addr: usize) -> usize {
+#[exception(PrefetchHandler)]
+fn prefetch_handler(addr: usize) -> usize {
     println!("prefetch abort occurred");
     let ifsr = Ifsr::read();
     println!("IFSR (Fault Status Register): {:?}", ifsr);
@@ -95,7 +98,7 @@ unsafe extern "C" fn _prefetch_handler(addr: usize) -> usize {
     }
 }
 
-#[unsafe(no_mangle)]
-unsafe extern "C" fn _abort_handler(_addr: usize) -> ! {
+#[exception(AbortHandler)]
+fn abort_handler(_addr: usize) -> ! {
     panic!("unexpected abort exception");
 }

examples/mps3-an536/src/bin/registers.rs

@@ -4,22 +4,18 @@
 #![no_main]
 
 // pull in our start-up code
+use cortex_r_rt::entry;
+
+// pull in our library
 use mps3_an536 as _;
 
 use semihosting::println;
 
 /// The entry-point to the Rust application.
 ///
-/// It is called by the start-up code in `cortex-m-rt`.
-#[no_mangle]
-pub extern "C" fn kmain() {
-    main();
-}
-
-/// The entry-point to the Rust application.
-///
-/// Called by [`kmain`].
-pub fn main() -> ! {
+/// It is called by the start-up code in `cortex-r-rt`.
+#[entry]
+fn main() -> ! {
     chip_info();
     #[cfg(arm_architecture = "v7-r")]
     mpu_pmsa_v7();

examples/mps3-an536/src/bin/smp_test.rs

@@ -14,6 +14,9 @@ use core::cell::{RefCell, UnsafeCell};
 use core::sync::atomic::{AtomicBool, AtomicU32, Ordering};
 
 // pull in our start-up code
+use cortex_r_rt::entry;
+
+// pull in our library
 use mps3_an536 as _;
 
 use semihosting::println;
@@ -58,9 +61,9 @@ const CS_MUTEX_LOOPS: u32 = 1000;
 
 /// The entry-point to the Rust application.
 ///
-/// It is called by the start-up code in `cortex-m-rt`.
-#[no_mangle]
-pub extern "C" fn kmain() {
+/// It is called by the start-up code in `cortex-r-rt`.
+#[entry]
+fn main() -> ! {
     let fpga_led = 0xE020_2000 as *mut u32;
     extern "C" {
         static mut _core1_stack_pointer: usize;