Add default implementation to ACLINT structs

Author: romancardenas

riscv-peripheral/src/aclint.rs

@@ -33,7 +33,7 @@ pub unsafe trait Clint: Copy {
 /// Each HART has an assigned index starting from 0 to up to 4_094.
 /// In this way, each HART's timer and software interrupts can be independently configured.
 #[allow(clippy::upper_case_acronyms)]
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
 pub struct CLINT<C> {
     _marker: core::marker::PhantomData<C>,
 }

riscv-peripheral/src/aclint/mswi.rs

@@ -25,7 +25,7 @@ unsafe impl<C: Clint> Mswi for C {
 }
 
 /// MSWI peripheral.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
 pub struct MSWI<M> {
     _marker: core::marker::PhantomData<M>,
 }

riscv-peripheral/src/aclint/mtimer.rs

@@ -36,7 +36,7 @@ unsafe impl<C: Clint> Mtimer for C {
 ///
 /// It has a single fixed-frequency monotonic time counter ([`MTIME`])
 /// register and a time compare register ([`MTIMECMP`]) for each HART.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
 pub struct MTIMER<M> {
     _marker: core::marker::PhantomData<M>,
 }

riscv-peripheral/src/aclint/sswi.rs

@@ -16,7 +16,7 @@ pub unsafe trait Sswi: Copy {
 }
 
 /// SSWI peripheral.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, Eq, PartialEq)]
 pub struct SSWI<M> {
     _marker: core::marker::PhantomData<M>,
 }