riscv: add the mvien + mvienh CSR

Adds the `mvien` + `mvienh` CSR to represent the `Machine Virtual
Interrupt Enable` registers.

Author: 0xllx0

riscv/CHANGELOG.md

@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add `miselect` CSR
 - Improved assembly macro handling in asm.rs
 - New `rt` and `rt-v-trap` features to opt-in `riscv-rt`-related code in `riscv::pac_enum` macro.
+- Add `mvien` + `mvienh` CSR
 
 # Changed
 

riscv/src/register.rs

@@ -91,6 +91,9 @@ pub mod mscratch;
 pub mod mtinst;
 pub mod mtval;
 pub mod mtval2;
+pub mod mvien;
+#[cfg(any(test, target_arch = "riscv32"))]
+pub mod mvienh;
 
 // Machine Protection and Translation
 mod pmpcfgx;

riscv/src/register/mvien.rs

@@ -0,0 +1,65 @@
+//! mvien register
+
+#[cfg(target_arch = "riscv32")]
+const MASK: usize = 0xffff_e222;
+#[cfg(not(target_arch = "riscv32"))]
+const MASK: usize = 0xffff_ffff_ffff_e222;
+
+read_write_csr! {
+    /// `mvien` register
+    Mvien: 0x308,
+    mask: MASK,
+}
+
+read_write_csr_field! {
+    Mvien,
+    /// Alias of `mip.SSIP`
+    ssip: 1,
+}
+
+read_write_csr_field! {
+    Mvien,
+    /// Alias of `mip.STIP`
+    stip: 5,
+}
+
+read_write_csr_field! {
+    Mvien,
+    /// Alias of `mip.SEIP`
+    seip: 9,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Mvien,
+    /// Represents the enable status of a virtual major interrupt.
+    interrupt: 13..=31,
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Mvien,
+    /// Represents the enable status of a virtual major interrupt.
+    interrupt: 13..=63,
+}
+
+set!(0x308);
+clear!(0x308);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mvien() {
+        let mut m = Mvien::from_bits(0);
+
+        test_csr_field!(m, ssip);
+        test_csr_field!(m, stip);
+        test_csr_field!(m, seip);
+
+        (13..64).for_each(|idx| {
+            test_csr_field!(m, interrupt, idx);
+        });
+    }
+}

riscv/src/register/mvienh.rs

@@ -0,0 +1,30 @@
+//! mvienh register
+
+read_write_csr! {
+    /// `mvienh` register
+    Mvienh: 0x318,
+    mask: 0xffff_ffff,
+}
+
+read_write_csr_field! {
+    Mvienh,
+    /// Represents the enable status of a virtual major interrupt.
+    interrupt: 0..=31,
+}
+
+set!(0x318);
+clear!(0x318);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mvienh() {
+        let mut m = Mvienh::from_bits(0);
+
+        (0..32).for_each(|idx| {
+            test_csr_field!(m, interrupt, idx);
+        });
+    }
+}