Adapt riscv-semihosting to edition 2024

Author: romancardenas

.github/workflows/riscv-semihosting.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

riscv-semihosting/Cargo.toml

@@ -4,7 +4,7 @@ authors = [
     "Jorge Aparicio <[email protected]>",
     "The RISC-V Team <[email protected]>",
 ]
-description = "Semihosting for RISCV processors"
+description = "Semihosting for RISC-V processors"
 documentation = "https://docs.rs/riscv-semihosting"
 keywords = ["semihosting", "riscv"]
 categories = ["no-std", "embedded"]
@@ -13,8 +13,8 @@ name = "riscv-semihosting"
 readme = "README.md"
 repository = "https://github.com/riscv-rust/riscv"
 version = "0.2.0"
-edition = "2021"
-rust-version = "1.67"
+edition = "2024"
+rust-version = "1.85"
 
 [features]
 u-mode = []

riscv-semihosting/README.md

@@ -35,12 +35,12 @@ While `riscv-semihosting` is a good starting point for developing semihosted app
 
 # Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.60.0 and up. It **won't**
+This crate is guaranteed to compile on stable Rust 1.85.0 and up. It **won't**
 compile with older versions.
 
 ## License
 
-Copyright 2018-2023 [RISC-V team][team]
+Copyright 2018-2025 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice
@@ -69,4 +69,4 @@ to intervene to uphold that code of conduct.
 [CoC]: ../CODE_OF_CONDUCT.md
 [team]: https://github.com/rust-embedded/wg#the-risc-v-team
 [`semihosting`]: https://crates.io/crates/semihosting
-[`cortex-m-semihosting`]: https://docs.rs/cortex-m-semihosting
+[`cortex-m-semihosting`]: https://docs.rs/cortex-m-semihosting

riscv-semihosting/src/lib.rs

@@ -202,7 +202,7 @@ pub mod nr;
 /// [semihosting operation]: https://developer.arm.com/documentation/dui0471/i/semihosting/semihosting-operations?lang=en
 #[inline(always)]
 pub unsafe fn syscall<T>(nr: usize, arg: &T) -> usize {
-    syscall1(nr, arg as *const T as usize)
+    unsafe { syscall1(nr, arg as *const T as usize) }
 }
 
 /// Performs a semihosting operation, takes one integer as an argument
@@ -221,7 +221,8 @@ pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize {
             // it will be treated as a regular break, hence the norvc option.
             //
             // See https://github.com/riscv/riscv-semihosting-spec for more details.
-            asm!("
+            unsafe {
+                asm!("
                 .balign 16
                 .option push
                 .option norvc
@@ -230,10 +231,11 @@ pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize {
                 srai x0, x0, 0x7
                 .option pop
             ",
-            inout("a0") nr,
-            inout("a1") arg => _,
-            options(nostack, preserves_flags),
-            );
+                inout("a0") nr,
+                inout("a1") arg => _,
+                options(nostack, preserves_flags),
+                )
+            };
             nr
         }
         #[cfg(all(riscv, feature = "no-semihosting"))]