diff --git a/Cargo.toml b/Cargo.toml
index d15e82f9..3f4d21da 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -2,7 +2,7 @@
 resolver = "2"
 members = [
     "riscv",
-    "riscv-pac",
+    "riscv-types",
     "riscv-peripheral",
     "riscv-rt",
     "riscv-semihosting",
@@ -13,7 +13,7 @@ members = [
 
 default-members = [
     "riscv",
-    "riscv-pac",
+    "riscv-types",
     "riscv-peripheral",
     "riscv-rt",
     "riscv-semihosting",
diff --git a/riscv-peripheral/Cargo.toml b/riscv-peripheral/Cargo.toml
index c0caff29..36972af2 100644
--- a/riscv-peripheral/Cargo.toml
+++ b/riscv-peripheral/Cargo.toml
@@ -17,7 +17,7 @@ license = "ISC"
 embedded-hal = "1.0.0"
 paste = "1.0"
 riscv = { path = "../riscv", version = "0.15.0" }
-riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
+riscv-types = { path = "../riscv-types", version = "0.2.0" }
 
 [package.metadata.docs.rs]
 all-features = true
diff --git a/riscv-peripheral/src/aclint.rs b/riscv-peripheral/src/aclint.rs
index 998edf24..9dc2362a 100644
--- a/riscv-peripheral/src/aclint.rs
+++ b/riscv-peripheral/src/aclint.rs
@@ -7,7 +7,7 @@ pub mod mswi;
 pub mod mtimer;
 pub mod sswi;
 
-pub use riscv_pac::HartIdNumber; // re-export useful riscv-pac traits
+pub use riscv_types::HartIdNumber; // re-export useful riscv-types traits
 
 /// Trait for a CLINT peripheral.
 ///
diff --git a/riscv-peripheral/src/lib.rs b/riscv-peripheral/src/lib.rs
index be677477..5fb96a30 100644
--- a/riscv-peripheral/src/lib.rs
+++ b/riscv-peripheral/src/lib.rs
@@ -3,7 +3,7 @@
 #![deny(missing_docs)]
 #![no_std]
 
-pub use riscv_pac::result; // re-export the result module
+pub use riscv_types::result; // re-export the result module
 
 pub mod common; // common definitions for all peripherals
 pub mod hal; // trait implementations for embedded-hal
diff --git a/riscv-peripheral/src/macros.rs b/riscv-peripheral/src/macros.rs
index c5c559dd..78fbd514 100644
--- a/riscv-peripheral/src/macros.rs
+++ b/riscv-peripheral/src/macros.rs
@@ -31,7 +31,7 @@ pub use paste::paste;
 /// ## Base address and per-HART mtimecmp registers, private `fn new()` function
 ///
 /// ```
-/// use riscv_pac::result::{Error, Result};
+/// use riscv_types::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -142,7 +142,7 @@ macro_rules! clint_codegen {
 /// ## Base address and per-HART context proxies, private `fn new()` function
 ///
 /// ```
-/// use riscv_pac::result::{Error, Result};
+/// use riscv_types::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]
diff --git a/riscv-peripheral/src/plic.rs b/riscv-peripheral/src/plic.rs
index af0300b8..491aee0d 100644
--- a/riscv-peripheral/src/plic.rs
+++ b/riscv-peripheral/src/plic.rs
@@ -8,8 +8,8 @@ pub mod pendings;
 pub mod priorities;
 pub mod threshold;
 
-// re-export useful riscv-pac traits
-pub use riscv_pac::{HartIdNumber, InterruptNumber, PriorityNumber};
+// re-export useful riscv-types traits
+pub use riscv_types::{HartIdNumber, InterruptNumber, PriorityNumber};
 
 use riscv::register::{mhartid, mie, mip};
 
@@ -200,7 +200,7 @@ impl<P: Plic> CTX<P> {
 #[cfg(test)]
 pub(crate) mod test {
     use crate::test::HartId;
-    use riscv_pac::HartIdNumber;
+    use riscv_types::HartIdNumber;
 
     #[allow(dead_code)]
     #[test]
diff --git a/riscv-peripheral/src/plic/claim.rs b/riscv-peripheral/src/plic/claim.rs
index 945f2b35..f4620de9 100644
--- a/riscv-peripheral/src/plic/claim.rs
+++ b/riscv-peripheral/src/plic/claim.rs
@@ -1,7 +1,7 @@
 //! Interrupt claim/complete register
 
 use crate::common::unsafe_peripheral;
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 unsafe_peripheral!(CLAIM, u32, RW);
 
@@ -32,7 +32,7 @@ impl CLAIM {
 mod test {
     use super::*;
     use crate::test::Interrupt;
-    use riscv_pac::InterruptNumber;
+    use riscv_types::InterruptNumber;
 
     #[test]
     fn test_claim() {
diff --git a/riscv-peripheral/src/plic/enables.rs b/riscv-peripheral/src/plic/enables.rs
index 016eb863..c4a59934 100644
--- a/riscv-peripheral/src/plic/enables.rs
+++ b/riscv-peripheral/src/plic/enables.rs
@@ -1,7 +1,7 @@
 //! Interrupt enables register of a PLIC context.
 
 use crate::common::{Reg, RW};
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 /// Enables register of a PLIC context.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
diff --git a/riscv-peripheral/src/plic/pendings.rs b/riscv-peripheral/src/plic/pendings.rs
index 12b170ce..f0cb9334 100644
--- a/riscv-peripheral/src/plic/pendings.rs
+++ b/riscv-peripheral/src/plic/pendings.rs
@@ -1,7 +1,7 @@
 //! Interrupt pending bits register.
 
 use crate::common::{Reg, RO};
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 /// Interrupts pending bits register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
diff --git a/riscv-peripheral/src/plic/priorities.rs b/riscv-peripheral/src/plic/priorities.rs
index 725cd6d9..44b9c7ab 100644
--- a/riscv-peripheral/src/plic/priorities.rs
+++ b/riscv-peripheral/src/plic/priorities.rs
@@ -1,7 +1,7 @@
 //! Interrupts Priorities register.
 
 use crate::common::{Reg, RW};
-use riscv_pac::{ExternalInterruptNumber, PriorityNumber};
+use riscv_types::{ExternalInterruptNumber, PriorityNumber};
 
 /// Interrupts priorities register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -71,7 +71,7 @@ impl PRIORITIES {
 mod test {
     use super::*;
     use crate::test::{Interrupt, Priority};
-    use riscv_pac::InterruptNumber;
+    use riscv_types::InterruptNumber;
 
     #[test]
     fn test_priorities() {
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 920c9ae7..847d066b 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,10 +7,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-### Changed
-
-- Adapted to new `riscv` version.
-
 ## [v0.16.0] - 2025-09-08
 
 ### Added
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 009227be..f8212561 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -24,8 +24,8 @@ targets = [
 riscv-target-parser = { path = "../riscv-target-parser", version = "0.1.2" }
 
 [dependencies]
-riscv = { path = "../riscv", version = "0.15.0", features = ["rt"] }
-riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
+riscv = { path = "../riscv", version = "0.15.0" }
+riscv-types = { path = "../riscv-types", version = "0.2.0" }
 riscv-rt-macros = { path = "macros", version = "0.6.0" }
 
 defmt = { version = "1.0.1", optional = true }
@@ -38,7 +38,7 @@ pre-init = []
 post-init = []
 s-mode = ["riscv-rt-macros/s-mode"]
 single-hart = []
-v-trap = ["riscv-rt-macros/v-trap", "riscv/rt-v-trap"]
+v-trap = ["riscv-rt-macros/v-trap"]
 u-boot = ["riscv-rt-macros/u-boot", "single-hart"]
 no-interrupts = []
 no-exceptions = []
diff --git a/riscv-rt/src/interrupts.rs b/riscv-rt/src/interrupts.rs
index 71b77014..44561f86 100644
--- a/riscv-rt/src/interrupts.rs
+++ b/riscv-rt/src/interrupts.rs
@@ -17,10 +17,10 @@
 //! you may need to opt out this module. To do so, activate the `no-interrupts` feature of the
 //! `riscv-rt` crate.
 
+// In vectored mode, we also must provide a vector table
 #[riscv::pac_enum(unsafe CoreInterruptNumber)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[allow(dead_code)] // otherwise compiler complains about Interrupt not being used
 enum Interrupt {
     SupervisorSoft = 1,
     MachineSoft = 3,
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 4c3b79b5..f73ba325 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -662,8 +662,8 @@ use riscv::register::{
     mtvec::{self as xtvec, Mtvec as Xtvec, TrapMode},
 };
 
-pub use riscv_pac::*;
 pub use riscv_rt_macros::{core_interrupt, entry, exception, external_interrupt};
+pub use riscv_types::*;
 
 #[cfg(feature = "post-init")]
 pub use riscv_rt_macros::post_init;
diff --git a/riscv-pac/CHANGELOG.md b/riscv-types/CHANGELOG.md
similarity index 93%
rename from riscv-pac/CHANGELOG.md
rename to riscv-types/CHANGELOG.md
index 9dcfcd6a..11319775 100644
--- a/riscv-pac/CHANGELOG.md
+++ b/riscv-types/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Rename all instances of `riscv-pac` with `riscv-types`
+
 ## [v0.2.0] - 2024-10-19
 
 ### Added
diff --git a/riscv-pac/Cargo.toml b/riscv-types/Cargo.toml
similarity index 90%
rename from riscv-pac/Cargo.toml
rename to riscv-types/Cargo.toml
index b5ba86b2..dda8cf71 100644
--- a/riscv-pac/Cargo.toml
+++ b/riscv-types/Cargo.toml
@@ -1,5 +1,5 @@
 [package]
-name = "riscv-pac"
+name = "riscv-types"
 version = "0.2.0"
 edition = "2021"
 rust-version = "1.60"
@@ -7,7 +7,7 @@ repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
-documentation = "https://docs.rs/riscv-pac"
+documentation = "https://docs.rs/riscv-types"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 
diff --git a/riscv-pac/README.md b/riscv-types/README.md
similarity index 100%
rename from riscv-pac/README.md
rename to riscv-types/README.md
diff --git a/riscv-pac/src/lib.rs b/riscv-types/src/lib.rs
similarity index 100%
rename from riscv-pac/src/lib.rs
rename to riscv-types/src/lib.rs
diff --git a/riscv-pac/src/result.rs b/riscv-types/src/result.rs
similarity index 100%
rename from riscv-pac/src/result.rs
rename to riscv-types/src/result.rs
diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 795bb67b..23756a28 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -12,11 +12,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
 - Add `miselect` CSR
 - Improved assembly macro handling in asm.rs
-- New `rt` and `rt-v-trap` features to opt-in `riscv-rt`-related code in `riscv::pac_enum` macro.
-
-# Changed
-
-- Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled.
 
 ## [v0.15.0] - 2025-09-08
 
diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml
index 945a1e94..765f70fb 100644
--- a/riscv/Cargo.toml
+++ b/riscv/Cargo.toml
@@ -23,12 +23,10 @@ targets = [
 default = ["riscv-macros"]
 s-mode = []
 critical-section-single-hart = ["critical-section/restore-state-bool"]
-rt = ["riscv-macros/rt"]
-rt-v-trap = ["rt", "riscv-macros/rt-v-trap"]
 
 [dependencies]
 critical-section = "1.2.0"
 embedded-hal = "1.0.0"
-riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
+riscv-types = { path = "../riscv-types", version = "0.2.0" }
 riscv-macros = { path = "macros", version = "0.3.0", optional = true }
 paste = "1.0.15"
diff --git a/riscv/macros/Cargo.toml b/riscv/macros/Cargo.toml
index 749d8e5e..43773c7a 100644
--- a/riscv/macros/Cargo.toml
+++ b/riscv/macros/Cargo.toml
@@ -15,10 +15,6 @@ edition = "2021"
 [lib]
 proc-macro = true
 
-[features]
-rt = []
-rt-v-trap = ["rt"]
-
 [dependencies]
 proc-macro2 = "1.0"
 quote = "1.0"
diff --git a/riscv/macros/src/lib.rs b/riscv/macros/src/lib.rs
index 3192f1ad..5c34ae76 100644
--- a/riscv/macros/src/lib.rs
+++ b/riscv/macros/src/lib.rs
@@ -11,7 +11,6 @@ use syn::{
 };
 
 /// Struct to represent a function parameter.
-#[cfg(feature = "rt")]
 struct FunctionParam {
     /// Name of the parameter.
     param_name: TokenStream2,
@@ -21,7 +20,6 @@ struct FunctionParam {
 
 /// Configuration parameters of a trap. It is useful to abstract the
 /// differences between exception handlers and core interrupt handlers.
-#[cfg(feature = "rt")]
 struct TrapConfig {
     /// Name of the default handler (e.g., `DefaultHandler` for core interrupts).
     default_handler: TokenStream2,
@@ -33,7 +31,6 @@ struct TrapConfig {
     handlers_array_name: TokenStream2,
 }
 
-#[cfg(feature = "rt")]
 impl TrapConfig {
     /// Vector with all the input parameters expected when declaring extern handler functions
     fn extern_signature(&self) -> Vec<TokenStream2> {
@@ -110,7 +107,6 @@ impl PacTrait {
     }
 
     /// For Exception or an Interrupt enums, it returns the trap configuration details.
-    #[cfg(feature = "rt")]
     fn trap_config(&self) -> Option<TrapConfig> {
         match self {
             Self::Exception => Some(TrapConfig {
@@ -167,7 +163,6 @@ impl InterruptType {
     }
 
     /// Returns a token stream representing the name of the array of interrupt service routines
-    #[cfg(feature = "rt")]
     fn isr_array_name(&self) -> TokenStream2 {
         match self {
             Self::Core => quote!(__CORE_INTERRUPTS),
@@ -176,7 +171,6 @@ impl InterruptType {
     }
 
     /// Returns a token stream representing the name of the interrupt dispatch function
-    #[cfg(feature = "rt")]
     fn dispatch_fn_name(&self) -> TokenStream2 {
         match self {
             Self::Core => quote!(_dispatch_core_interrupt),
@@ -185,7 +179,7 @@ impl InterruptType {
     }
 }
 
-/// Struct containing the information needed to implement the `riscv-pac` traits for an enum
+/// Struct containing the information needed to implement the `riscv-types` traits for an enum
 struct PacEnumItem {
     /// The name of the enum
     name: Ident,
@@ -245,7 +239,6 @@ impl PacEnumItem {
     }
 
     /// Returns a vector of token streams representing the interrupt handler functions
-    #[cfg(feature = "rt")]
     fn handlers(&self, trap_config: &TrapConfig) -> Vec<TokenStream2> {
         let signature = trap_config.extern_signature();
         self.numbers
@@ -259,7 +252,6 @@ impl PacEnumItem {
     /// Returns a sorted vector of token streams representing all the elements of the interrupt array.
     /// If an interrupt number is not present in the enum, the corresponding element is `None`.
     /// Otherwise, it is `Some(<interrupt_handler>)`.
-    #[cfg(feature = "rt")]
     fn handlers_array(&self) -> Vec<TokenStream2> {
         let mut vectors = vec![];
         for i in 0..=self.max_number {
@@ -272,7 +264,6 @@ impl PacEnumItem {
         vectors
     }
 
-    #[cfg(feature = "rt-v-trap")]
     fn vector_table(&self) -> TokenStream2 {
         let align = match std::env::var("RISCV_MTVEC_ALIGN") {
             Ok(x) => x.parse::<u32>().ok(),
@@ -289,7 +280,7 @@ impl PacEnumItem {
         };
         let mut asm = format!(
             r#"
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[cfg(all(feature = "v-trap", any(target_arch = "riscv32", target_arch = "riscv64")))]
 core::arch::global_asm!("
     .section .trap.vector, \"ax\"
     .global _vector_table
@@ -337,6 +328,8 @@ core::arch::global_asm!("
         let max_discriminant = self.max_number;
         let valid_matches = self.valid_matches();
 
+        let is_core_interrupt = matches!(attr, PacTrait::Interrupt(InterruptType::Core));
+
         // Push the trait implementation
         res.push(quote! {
             unsafe impl riscv::#trait_name for #name {
@@ -361,64 +354,67 @@ core::arch::global_asm!("
             res.push(quote! { unsafe impl riscv::#marker_trait_name for #name {} });
         }
 
-        #[cfg(feature = "rt")]
         if let Some(trap_config) = attr.trap_config() {
-            match attr {
-                #[cfg(feature = "rt-v-trap")]
-                PacTrait::Interrupt(InterruptType::Core) => {
-                    res.push(self.vector_table());
+            let default_handler = &trap_config.default_handler;
+            let extern_signature = trap_config.extern_signature();
+            let handler_input = trap_config.handler_input();
+            let array_signature = trap_config.array_signature();
+            let dispatch_fn_name = &trap_config.dispatch_fn_name;
+            let dispatch_fn_args = &trap_config.dispatch_fn_signature();
+            let vector_table = &trap_config.handlers_array_name;
+
+            let handlers = self.handlers(&trap_config);
+            let interrupt_array = self.handlers_array();
+            let cfg_v_trap = match is_core_interrupt {
+                true => Some(quote!(#[cfg(not(feature = "v-trap"))])),
+                false => None,
+            };
+
+            // Push the interrupt handler functions and the interrupt array
+            res.push(quote! {
+                #cfg_v_trap
+                extern "C" {
+                    #(#handlers;)*
                 }
-                _ => {
-                    let default_handler = &trap_config.default_handler;
-                    let extern_signature = trap_config.extern_signature();
-                    let handler_input = trap_config.handler_input();
-                    let array_signature = trap_config.array_signature();
-                    let dispatch_fn_name = &trap_config.dispatch_fn_name;
-                    let dispatch_fn_args = &trap_config.dispatch_fn_signature();
-                    let vector_table = &trap_config.handlers_array_name;
-
-                    let handlers = self.handlers(&trap_config);
-                    let interrupt_array = self.handlers_array();
-
-                    res.push(quote! {
-                        extern "C" {
-                            #(#handlers;)*
-                        }
-
-                        #[doc(hidden)]
-                        #[no_mangle]
-                        pub static #vector_table: [Option<unsafe extern "C" fn(#(#array_signature),*)>; #max_discriminant + 1] = [
-                            #(#interrupt_array),*
-                        ];
-
-                        #[inline]
-                        #[no_mangle]
-                        unsafe extern "C" fn #dispatch_fn_name(#(#dispatch_fn_args),*) {
-                            extern "C" {
-                                fn #default_handler(#(#extern_signature),*);
-                            }
-
-                            match #vector_table.get(code) {
-                                Some(Some(handler)) => handler(#(#handler_input),*),
-                                _ => #default_handler(#(#handler_input),*),
-                            }
-                        }
-                    });
+
+                #cfg_v_trap
+                #[doc(hidden)]
+                #[no_mangle]
+                pub static #vector_table: [Option<unsafe extern "C" fn(#(#array_signature),*)>; #max_discriminant + 1] = [
+                    #(#interrupt_array),*
+                ];
+
+                #cfg_v_trap
+                #[inline]
+                #[no_mangle]
+                unsafe extern "C" fn #dispatch_fn_name(#(#dispatch_fn_args),*) {
+                    extern "C" {
+                        fn #default_handler(#(#extern_signature),*);
+                    }
+
+                    match #vector_table.get(code) {
+                        Some(Some(handler)) => handler(#(#handler_input),*),
+                        _ => #default_handler(#(#handler_input),*),
+                    }
                 }
-            }
+            });
+        }
+
+        if is_core_interrupt {
+            res.push(self.vector_table());
         }
 
         res
     }
 }
 
-/// Attribute-like macro that implements the traits of the `riscv-pac` crate for a given enum.
+/// Attribute-like macro that implements the traits of the `riscv-types` crate for a given enum.
 ///
 /// As these traits are unsafe, the macro must be called with the `unsafe` keyword followed by the trait name.
 /// In this way, we warn callers that they must comply with the requirements of the trait.
 ///
-/// The trait name must be one of `ExceptionNumber`, `CoreInterruptNumber`, `ExternalInterruptNumber`,
-/// `PriorityNumber`, or `HartIdNumber`.
+/// The trait name must be one of `ExceptionNumber`, `InterruptNumber`, `PriorityNumber`, or `HartIdNumber`.
+/// Marker traits `CoreInterruptNumber` and `ExternalInterruptNumber` cannot be implemented using this macro.
 ///
 /// # Safety
 ///
diff --git a/riscv/src/interrupt.rs b/riscv/src/interrupt.rs
index 93fda11c..e3265b8c 100644
--- a/riscv/src/interrupt.rs
+++ b/riscv/src/interrupt.rs
@@ -4,8 +4,8 @@
 
 use crate::result::Result;
 
-// re-export useful riscv-pac traits
-pub use riscv_pac::{CoreInterruptNumber, ExceptionNumber, InterruptNumber};
+// re-export useful riscv-types traits
+pub use riscv_types::{CoreInterruptNumber, ExceptionNumber, InterruptNumber};
 
 pub mod machine;
 pub mod supervisor;
diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs
index b8a54fb8..474141b6 100644
--- a/riscv/src/interrupt/machine.rs
+++ b/riscv/src/interrupt/machine.rs
@@ -2,7 +2,7 @@ use crate::{
     interrupt::Trap,
     register::{mcause, mepc, mie, mip, mstatus},
 };
-use riscv_pac::{
+use riscv_types::{
     result::{Error, Result},
     CoreInterruptNumber, ExceptionNumber, InterruptNumber,
 };
diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs
index 33266f2c..796bf55f 100644
--- a/riscv/src/interrupt/supervisor.rs
+++ b/riscv/src/interrupt/supervisor.rs
@@ -2,7 +2,7 @@ use crate::{
     interrupt::Trap,
     register::{scause, sepc, sie, sip, sstatus},
 };
-use riscv_pac::{
+use riscv_types::{
     result::{Error, Result},
     CoreInterruptNumber, ExceptionNumber, InterruptNumber,
 };
diff --git a/riscv/src/lib.rs b/riscv/src/lib.rs
index 0704f75b..131deee7 100644
--- a/riscv/src/lib.rs
+++ b/riscv/src/lib.rs
@@ -31,17 +31,6 @@
 //! and may cause functional problems in systems where some interrupts must NOT be disabled
 //! or critical sections are managed as part of an RTOS. In these cases, you should use
 //! a target-specific implementation instead, typically provided by a HAL or RTOS crate.
-//!
-//! ## `rt`
-//!
-//! This feature enables code related to [`riscv-rt`](https://github.com/rust-embedded/riscv/tree/master/riscv-rt)
-//! runtime support in the `riscv::pac_enum` macro. Namely, it enables the generation of
-//! trap handler functions and dispatch functions.
-//!
-//! ## `rt-v-trap`
-//!
-//! This feature enables code related to vectored trap handling in addition to the `rt` feature.
-//! Namely, it enables the generation of a vector table and the corresponding assembly code for core interrupts.
 
 #![no_std]
 #![allow(clippy::missing_safety_doc)]
@@ -59,7 +48,7 @@ pub mod register;
 // Re-export crates of the RISC-V ecosystem
 #[cfg(feature = "riscv-macros")]
 pub use riscv_macros::*;
-pub use riscv_pac::*;
+pub use riscv_types::*;
 
 #[macro_use]
 mod macros;
diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs
index 0ca87677..98e4da66 100644
--- a/riscv/src/register/mie.rs
+++ b/riscv/src/register/mie.rs
@@ -1,7 +1,7 @@
 //! mie register
 
 use crate::bits::{bf_extract, bf_insert};
-use riscv_pac::CoreInterruptNumber;
+use riscv_types::CoreInterruptNumber;
 
 read_write_csr! {
     /// `mie` register
diff --git a/riscv/src/register/mip.rs b/riscv/src/register/mip.rs
index 10e66526..a34b7f8a 100644
--- a/riscv/src/register/mip.rs
+++ b/riscv/src/register/mip.rs
@@ -1,7 +1,7 @@
 //! mip register
 
 use crate::bits::bf_extract;
-use riscv_pac::CoreInterruptNumber;
+use riscv_types::CoreInterruptNumber;
 
 read_only_csr! {
     /// `mip` register
diff --git a/riscv/src/register/scause.rs b/riscv/src/register/scause.rs
index 2d42646f..3e8e36bc 100644
--- a/riscv/src/register/scause.rs
+++ b/riscv/src/register/scause.rs
@@ -1,7 +1,7 @@
 //! scause register
 
 pub use crate::interrupt::Trap;
-pub use riscv_pac::{CoreInterruptNumber, ExceptionNumber, InterruptNumber}; // re-export useful riscv-pac traits
+pub use riscv_types::{CoreInterruptNumber, ExceptionNumber, InterruptNumber}; // re-export useful riscv-types traits
 
 read_write_csr! {
     /// scause register
diff --git a/riscv/src/register/sie.rs b/riscv/src/register/sie.rs
index dfeecdaa..60720d43 100644
--- a/riscv/src/register/sie.rs
+++ b/riscv/src/register/sie.rs
@@ -1,7 +1,7 @@
 //! sie register
 
 use crate::bits::{bf_extract, bf_insert};
-use riscv_pac::CoreInterruptNumber;
+use riscv_types::CoreInterruptNumber;
 
 read_write_csr! {
 /// sie register
diff --git a/riscv/src/register/sip.rs b/riscv/src/register/sip.rs
index c72602b9..654f324a 100644
--- a/riscv/src/register/sip.rs
+++ b/riscv/src/register/sip.rs
@@ -1,7 +1,7 @@
 //! sip register
 
 use crate::bits::bf_extract;
-use riscv_pac::CoreInterruptNumber;
+use riscv_types::CoreInterruptNumber;
 
 read_only_csr! {
     /// sip register