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light4
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docs: Remove pl011_uart duplicate comments.
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18 files changed

+20
-104
lines changed

18 files changed

+20
-104
lines changed

‎05_drivers_gpio_uart/README.md

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -459,7 +459,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g
459459
diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
460460
--- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
461461
+++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
462-
@@ -0,0 +1,408 @@
462+
@@ -0,0 +1,402 @@
463463
+// SPDX-License-Identifier: MIT OR Apache-2.0
464464
+//
465465
+// Copyright (c) 2018-2021 Andre Richter <[email protected]>
@@ -512,12 +512,6 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri
512512
+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
513513
+ /// LCR_H Register.
514514
+ ///
515-
+ /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
516-
+ /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
517-
+
518-
+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
519-
+ /// LCR_H Register.
520-
+ ///
521515
+ /// - If the FIFO is disabled, this bit is set when the receive holding register is empty.
522516
+ /// - If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
523517
+ RXFE OFFSET(4) NUMBITS(1) [],

‎05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎06_uart_chainloader/README.md

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart
339339
diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
340340
--- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
341341
+++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
342-
@@ -284,7 +284,7 @@
342+
@@ -278,7 +278,7 @@
343343
}
344344

345345
/// Retrieve a character.
@@ -348,7 +348,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
348348
// If RX FIFO is empty,
349349
if self.registers.FR.matches_all(FR::RXFE::SET) {
350350
// immediately return in non-blocking mode.
351-
@@ -299,12 +299,7 @@
351+
@@ -293,12 +293,7 @@
352352
}
353353

354354
// Read one character.
@@ -362,7 +362,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
362362

363363
// Update statistics.
364364
self.chars_read += 1;
365-
@@ -384,14 +379,14 @@
365+
@@ -378,14 +373,14 @@
366366
impl console::interface::Read for PL011Uart {
367367
fn read_char(&self) -> char {
368368
self.inner

‎06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎07_timestamps/README.md

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_times
408408
diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
409409
--- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
410410
+++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
411-
@@ -284,7 +284,7 @@
411+
@@ -278,7 +278,7 @@
412412
}
413413

414414
/// Retrieve a character.
@@ -417,7 +417,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
417417
// If RX FIFO is empty,
418418
if self.registers.FR.matches_all(FR::RXFE::SET) {
419419
// immediately return in non-blocking mode.
420-
@@ -299,7 +299,12 @@
420+
@@ -293,7 +293,12 @@
421421
}
422422

423423
// Read one character.
@@ -431,7 +431,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
431431

432432
// Update statistics.
433433
self.chars_read += 1;
434-
@@ -379,14 +384,14 @@
434+
@@ -373,14 +378,14 @@
435435
impl console::interface::Read for PL011Uart {
436436
fn read_char(&self) -> char {
437437
self.inner

‎07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎08_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎09_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎10_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎11_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎13_exceptions_part2_peripheral_IRQs/README.md

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1867,7 +1867,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
18671867
};
18681868
use core::fmt;
18691869
use tock_registers::{
1870-
@@ -140,6 +140,52 @@
1870+
@@ -134,6 +134,52 @@
18711871
]
18721872
],
18731873

@@ -1920,7 +1920,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
19201920
/// Interrupt Clear Register.
19211921
ICR [
19221922
/// Meta field for all pending interrupts.
1923-
@@ -158,7 +204,10 @@
1923+
@@ -152,7 +198,10 @@
19241924
(0x28 => FBRD: WriteOnly<u32, FBRD::Register>),
19251925
(0x2c => LCR_H: WriteOnly<u32, LCR_H::Register>),
19261926
(0x30 => CR: WriteOnly<u32, CR::Register>),
@@ -1932,7 +1932,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
19321932
(0x44 => ICR: WriteOnly<u32, ICR::Register>),
19331933
(0x48 => @END),
19341934
}
1935-
@@ -188,7 +237,8 @@
1935+
@@ -182,7 +231,8 @@
19361936

19371937
/// Representation of the UART.
19381938
pub struct PL011Uart {
@@ -1942,7 +1942,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
19421942
}
19431943

19441944
//--------------------------------------------------------------------------------------------------
1945-
@@ -256,6 +306,14 @@
1945+
@@ -250,6 +300,14 @@
19461946
.LCR_H
19471947
.write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled);
19481948

@@ -1957,7 +1957,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
19571957
// Turn the UART on.
19581958
self.registers
19591959
.CR
1960-
@@ -338,9 +396,13 @@
1960+
@@ -332,9 +390,13 @@
19611961
/// # Safety
19621962
///
19631963
/// - The user must ensure to provide a correct MMIO start address.
@@ -1973,7 +1973,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
19731973
}
19741974
}
19751975
}
1976-
@@ -360,6 +422,21 @@
1976+
@@ -354,6 +416,21 @@
19771977

19781978
Ok(())
19791979
}
@@ -1995,7 +1995,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
19951995
}
19961996

19971997
impl console::interface::Write for PL011Uart {
1998-
@@ -406,3 +483,24 @@
1998+
@@ -400,3 +477,24 @@
19991999
self.inner.lock(|inner| inner.chars_read)
20002000
}
20012001
}

‎13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

‎14_virtual_mem_part2_mmio_remap/README.md

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1266,7 +1266,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
12661266
use tock_registers::{
12671267
interfaces::{Readable, Writeable},
12681268
register_bitfields, register_structs,
1269-
@@ -237,6 +240,8 @@
1269+
@@ -231,6 +234,8 @@
12701270

12711271
/// Representation of the UART.
12721272
pub struct PL011Uart {
@@ -1275,7 +1275,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
12751275
inner: IRQSafeNullLock<PL011UartInner>,
12761276
irq_number: bsp::device_driver::IRQNumber,
12771277
}
1278-
@@ -276,7 +281,15 @@
1278+
@@ -270,7 +275,15 @@
12791279
/// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`.
12801280
///
12811281
/// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16modulo`.
@@ -1292,7 +1292,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
12921292
// Execution can arrive here while there are still characters queued in the TX FIFO and
12931293
// actively being sent out by the UART hardware. If the UART is turned off in this case,
12941294
// those queued characters would be lost.
1295-
@@ -318,6 +331,8 @@
1295+
@@ -312,6 +325,8 @@
12961296
self.registers
12971297
.CR
12981298
.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
@@ -1301,7 +1301,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
13011301
}
13021302

13031303
/// Send a character.
1304-
@@ -395,13 +410,18 @@
1304+
@@ -389,13 +404,18 @@
13051305
///
13061306
/// # Safety
13071307
///
@@ -1323,7 +1323,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
13231323
irq_number,
13241324
}
13251325
}
1326-
@@ -418,7 +438,13 @@
1326+
@@ -412,7 +432,13 @@
13271327
}
13281328

13291329
unsafe fn init(&self) -> Result<(), &'static str> {
@@ -1338,7 +1338,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
13381338

13391339
Ok(())
13401340
}
1341-
@@ -437,6 +463,16 @@
1341+
@@ -431,6 +457,16 @@
13421342

13431343
Ok(())
13441344
}

‎14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,6 @@ register_bitfields! {
5050
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
5151
TXFF OFFSET(5) NUMBITS(1) [],
5252

53-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
54-
/// LCR_H Register.
55-
///
56-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
57-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
58-
5953
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
6054
/// LCR_H Register.
6155
///

‎15_virtual_mem_part3_precomputed_tables/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,6 @@ register_bitfields! {
5050
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
5151
TXFF OFFSET(5) NUMBITS(1) [],
5252

53-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
54-
/// LCR_H Register.
55-
///
56-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
57-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
58-
5953
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
6054
/// LCR_H Register.
6155
///

‎16_virtual_mem_part4_higher_half_kernel/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,6 @@ register_bitfields! {
5050
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
5151
TXFF OFFSET(5) NUMBITS(1) [],
5252

53-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
54-
/// LCR_H Register.
55-
///
56-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
57-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
58-
5953
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
6054
/// LCR_H Register.
6155
///

‎X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

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